1.1 diff -r 7422134cbfea -r da23ab8ef7b4 rtl/lm32_instruction_unit.v 1.2 --- a/rtl/lm32_instruction_unit.v Tue Mar 08 09:59:34 2011 +0000 1.3 +++ b/rtl/lm32_instruction_unit.v Sat Aug 06 01:32:07 2011 +0100 1.4 @@ -1,18 +1,39 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 +// ================================================================== 1.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.16 +// ------------------------------------------------------------------ 1.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.18 +// ALL RIGHTS RESERVED 1.19 +// ------------------------------------------------------------------ 1.20 +// 1.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.22 +// 1.23 +// Permission: 1.24 +// 1.25 +// Lattice Semiconductor grants permission to use this code 1.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.27 +// Open Source License Agreement. 1.28 +// 1.29 +// Disclaimer: 1.30 // 1.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.34 -// U.S.A email: techsupport@latticesemi.com 1.35 -// =============================================================================/ 1.36 +// Lattice Semiconductor provides no warranty regarding the use or 1.37 +// functionality of this code. It is the user's responsibility to 1.38 +// verify the user’s design for consistency and functionality through 1.39 +// the use of formal verification methods. 1.40 +// 1.41 +// -------------------------------------------------------------------- 1.42 +// 1.43 +// Lattice Semiconductor Corporation 1.44 +// 5555 NE Moore Court 1.45 +// Hillsboro, OR 97214 1.46 +// U.S.A 1.47 +// 1.48 +// TEL: 1-800-Lattice (USA and Canada) 1.49 +// 503-286-8001 (other locations) 1.50 +// 1.51 +// web: http://www.latticesemi.com/ 1.52 +// email: techsupport@latticesemi.com 1.53 +// 1.54 +// -------------------------------------------------------------------- 1.55 // FILE DETAILS 1.56 // Project : LatticeMico32 1.57 // File : lm32_instruction_unit.v 1.58 @@ -42,6 +63,9 @@ 1.59 // : instruction cache) to lock up in to an infinite loop due to a 1.60 // : instruction bus error when EBA was set to instruction inline 1.61 // : memory. 1.62 +// Version : 3.8 1.63 +// : Feature: Support for dynamically switching EBA to DEBA via a 1.64 +// : GPIO. 1.65 // ============================================================================= 1.66 1.67 `include "lm32_include.v" 1.68 @@ -54,6 +78,11 @@ 1.69 // ----- Inputs ------- 1.70 clk_i, 1.71 rst_i, 1.72 +`ifdef CFG_DEBUG_ENABLED 1.73 + `ifdef CFG_ALTERNATE_EBA 1.74 + at_debug, 1.75 + `endif 1.76 +`endif 1.77 // From pipeline 1.78 stall_a, 1.79 stall_f, 1.80 @@ -161,6 +190,12 @@ 1.81 input clk_i; // Clock 1.82 input rst_i; // Reset 1.83 1.84 +`ifdef CFG_DEBUG_ENABLED 1.85 + `ifdef CFG_ALTERNATE_EBA 1.86 + input at_debug; // GPIO input that maps EBA to DEBA 1.87 + `endif 1.88 +`endif 1.89 + 1.90 input stall_a; // Stall A stage instruction 1.91 input stall_f; // Stall F stage instruction 1.92 input stall_d; // Stall D stage instruction 1.93 @@ -334,6 +369,10 @@ 1.94 reg jtag_access; // Indicates if a JTAG WB access is in progress 1.95 `endif 1.96 1.97 +`ifdef CFG_ALTERNATE_EBA 1.98 + reg alternate_eba_taken; 1.99 +`endif 1.100 + 1.101 ///////////////////////////////////////////////////// 1.102 // Functions 1.103 ///////////////////////////////////////////////////// 1.104 @@ -381,8 +420,8 @@ 1.105 .ResetB (rst_i), 1.106 .DataInA ({32{1'b0}}), 1.107 .DataInB (irom_store_data_m), 1.108 - .AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.109 - .AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.110 + .AddressA (pc_a[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), 1.111 + .AddressB (irom_address_xm[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), 1.112 .ClockEnA (!stall_a), 1.113 .ClockEnB (!stall_x || !stall_m), 1.114 .WrA (`FALSE), 1.115 @@ -469,7 +508,7 @@ 1.116 pc_a = restart_address; 1.117 else 1.118 `endif 1.119 - pc_a = pc_f + 1'b1; 1.120 + pc_a = pc_f + 1'b1; 1.121 end 1.122 1.123 // Select where instruction should be fetched from 1.124 @@ -542,28 +581,39 @@ 1.125 1.126 // PC 1.127 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.128 -begin 1.129 - if (rst_i == `TRUE) 1.130 - begin 1.131 - pc_f <= (`CFG_EBA_RESET-4)/4; 1.132 - pc_d <= {`LM32_PC_WIDTH{1'b0}}; 1.133 - pc_x <= {`LM32_PC_WIDTH{1'b0}}; 1.134 - pc_m <= {`LM32_PC_WIDTH{1'b0}}; 1.135 - pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.136 - end 1.137 - else 1.138 - begin 1.139 - if (stall_f == `FALSE) 1.140 + begin 1.141 + if (rst_i == `TRUE) 1.142 + begin 1.143 +`ifdef CFG_DEBUG_ENABLED 1.144 + `ifdef CFG_ALTERNATE_EBA 1.145 + if (at_debug == `TRUE) 1.146 + pc_f <= (`CFG_DEBA_RESET-4)/4; 1.147 + else 1.148 + pc_f <= (`CFG_EBA_RESET-4)/4; 1.149 + `else 1.150 + pc_f <= (`CFG_EBA_RESET-4)/4; 1.151 + `endif 1.152 +`else 1.153 + pc_f <= (`CFG_EBA_RESET-4)/4; 1.154 +`endif 1.155 + pc_d <= {`LM32_PC_WIDTH{1'b0}}; 1.156 + pc_x <= {`LM32_PC_WIDTH{1'b0}}; 1.157 + pc_m <= {`LM32_PC_WIDTH{1'b0}}; 1.158 + pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.159 + end 1.160 + else 1.161 + begin 1.162 + if (stall_f == `FALSE) 1.163 pc_f <= pc_a; 1.164 - if (stall_d == `FALSE) 1.165 + if (stall_d == `FALSE) 1.166 pc_d <= pc_f; 1.167 - if (stall_x == `FALSE) 1.168 + if (stall_x == `FALSE) 1.169 pc_x <= pc_d; 1.170 - if (stall_m == `FALSE) 1.171 + if (stall_m == `FALSE) 1.172 pc_m <= pc_x; 1.173 - pc_w <= pc_m; 1.174 - end 1.175 -end 1.176 + pc_w <= pc_m; 1.177 + end 1.178 + end 1.179 1.180 `ifdef LM32_CACHE_ENABLED 1.181 // Address to restart from after a cache miss has been handled