Sun, 04 Apr 2010 20:42:58 +0100
remove need for system_conf.v
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : lm32_dcache.v
19 // Title : Data cache
20 // Dependencies : lm32_include.v
21 // Version : 6.1.17
22 // : Initial Release
23 // Version : 7.0SP2, 3.0
24 // : No Change
25 // Version : 3.1
26 // : Support for user-selected resource usage when implementing
27 // : cache memory. Additional parameters must be defined when
28 // : invoking lm32_ram.v
29 // =============================================================================
31 `include "lm32_include.v"
33 `ifdef CFG_DCACHE_ENABLED
35 `define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
36 `define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
37 `define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
38 `define LM32_DC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
40 `define LM32_DC_TMEM_ADDR_WIDTH addr_set_width
41 `define LM32_DC_TMEM_ADDR_RNG (`LM32_DC_TMEM_ADDR_WIDTH-1):0
42 `define LM32_DC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
43 `define LM32_DC_DMEM_ADDR_RNG (`LM32_DC_DMEM_ADDR_WIDTH-1):0
45 `define LM32_DC_TAGS_WIDTH (addr_tag_width+1)
46 `define LM32_DC_TAGS_RNG (`LM32_DC_TAGS_WIDTH-1):0
47 `define LM32_DC_TAGS_TAG_RNG (`LM32_DC_TAGS_WIDTH-1):1
48 `define LM32_DC_TAGS_VALID_RNG 0
50 `define LM32_DC_STATE_RNG 2:0
51 `define LM32_DC_STATE_FLUSH 3'b001
52 `define LM32_DC_STATE_CHECK 3'b010
53 `define LM32_DC_STATE_REFILL 3'b100
55 /////////////////////////////////////////////////////
56 // Module interface
57 /////////////////////////////////////////////////////
59 module lm32_dcache (
60 // ----- Inputs -----
61 clk_i,
62 rst_i,
63 stall_a,
64 stall_x,
65 stall_m,
66 address_x,
67 address_m,
68 load_q_m,
69 store_q_m,
70 store_data,
71 store_byte_select,
72 refill_ready,
73 refill_data,
74 dflush,
75 // ----- Outputs -----
76 stall_request,
77 restart_request,
78 refill_request,
79 refill_address,
80 refilling,
81 load_data
82 );
84 /////////////////////////////////////////////////////
85 // Parameters
86 /////////////////////////////////////////////////////
88 parameter associativity = 1; // Associativity of the cache (Number of ways)
89 parameter sets = 512; // Number of sets
90 parameter bytes_per_line = 16; // Number of bytes per cache line
91 parameter base_address = 0; // Base address of cachable memory
92 parameter limit = 0; // Limit (highest address) of cachable memory
94 localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
95 localparam addr_set_width = clogb2(sets)-1;
96 localparam addr_offset_lsb = 2;
97 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
98 localparam addr_set_lsb = (addr_offset_msb+1);
99 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
100 localparam addr_tag_lsb = (addr_set_msb+1);
101 localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1;
102 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
104 /////////////////////////////////////////////////////
105 // Inputs
106 /////////////////////////////////////////////////////
108 input clk_i; // Clock
109 input rst_i; // Reset
111 input stall_a; // Stall A stage
112 input stall_x; // Stall X stage
113 input stall_m; // Stall M stage
115 input [`LM32_WORD_RNG] address_x; // X stage load/store address
116 input [`LM32_WORD_RNG] address_m; // M stage load/store address
117 input load_q_m; // Load instruction in M stage
118 input store_q_m; // Store instruction in M stage
119 input [`LM32_WORD_RNG] store_data; // Data to store
120 input [`LM32_BYTE_SELECT_RNG] store_byte_select; // Which bytes in store data should be modified
122 input refill_ready; // Indicates next word of refill data is ready
123 input [`LM32_WORD_RNG] refill_data; // Refill data
125 input dflush; // Indicates cache should be flushed
127 /////////////////////////////////////////////////////
128 // Outputs
129 /////////////////////////////////////////////////////
131 output stall_request; // Request pipeline be stalled because cache is busy
132 wire stall_request;
133 output restart_request; // Request to restart instruction that caused the cache miss
134 reg restart_request;
135 output refill_request; // Request a refill
136 reg refill_request;
137 output [`LM32_WORD_RNG] refill_address; // Address to refill from
138 reg [`LM32_WORD_RNG] refill_address;
139 output refilling; // Indicates if the cache is currently refilling
140 reg refilling;
141 output [`LM32_WORD_RNG] load_data; // Data read from cache
142 wire [`LM32_WORD_RNG] load_data;
144 /////////////////////////////////////////////////////
145 // Internal nets and registers
146 /////////////////////////////////////////////////////
148 wire read_port_enable; // Cache memory read port clock enable
149 wire write_port_enable; // Cache memory write port clock enable
150 wire [0:associativity-1] way_tmem_we; // Tag memory write enable
151 wire [0:associativity-1] way_dmem_we; // Data memory write enable
152 wire [`LM32_WORD_RNG] way_data[0:associativity-1]; // Data read from data memory
153 wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory
154 wire [0:associativity-1] way_valid; // Indicates which ways are valid
155 wire [0:associativity-1] way_match; // Indicates which ways matched
156 wire miss; // Indicates no ways matched
158 wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read address
159 wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address
160 wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address
161 wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address
162 wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data
163 reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data
165 reg [`LM32_DC_STATE_RNG] state; // Current state of FSM
166 wire flushing; // Indicates if cache is currently flushing
167 wire check; // Indicates if cache is currently checking for hits/misses
168 wire refill; // Indicates if cache is currently refilling
170 wire valid_store; // Indicates if there is a valid store instruction
171 reg [associativity-1:0] refill_way_select; // Which way should be refilled
172 reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache line should be refilled
173 wire last_refill; // Indicates when on last cycle of cache refill
174 reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed
176 genvar i, j;
178 /////////////////////////////////////////////////////
179 // Functions
180 /////////////////////////////////////////////////////
182 `include "lm32_functions.v"
184 /////////////////////////////////////////////////////
185 // Instantiations
186 /////////////////////////////////////////////////////
188 generate
189 for (i = 0; i < associativity; i = i + 1)
190 begin : memories
191 // Way data
192 if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
193 begin : data_memories
194 lm32_ram
195 #(
196 // ----- Parameters -------
197 .data_width (32),
198 .address_width (`LM32_DC_DMEM_ADDR_WIDTH),
199 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
200 .RAM_IMPLEMENTATION ("EBR"),
201 .RAM_TYPE ("RAM_DP_TRUE")
202 `else
203 `ifdef CFG_DCACHE_DAT_USE_SLICE
204 .RAM_IMPLEMENTATION ("SLICE")
205 `else
206 .RAM_IMPLEMENTATION ("AUTO")
207 `endif
208 `endif
209 ) way_0_data_ram
210 (
211 // ----- Inputs -------
212 .read_clk (clk_i),
213 .write_clk (clk_i),
214 .reset (rst_i),
215 .read_address (dmem_read_address),
216 .enable_read (read_port_enable),
217 .write_address (dmem_write_address),
218 .enable_write (write_port_enable),
219 .write_enable (way_dmem_we[i]),
220 .write_data (dmem_write_data),
221 // ----- Outputs -------
222 .read_data (way_data[i])
223 );
224 end
225 else
226 begin
227 for (j = 0; j < 4; j = j + 1)
228 begin : byte_memories
229 lm32_ram
230 #(
231 // ----- Parameters -------
232 .data_width (8),
233 .address_width (`LM32_DC_DMEM_ADDR_WIDTH),
234 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
235 .RAM_IMPLEMENTATION ("EBR"),
236 .RAM_TYPE ("RAM_DP_TRUE")
237 `else
238 `ifdef CFG_DCACHE_DAT_USE_SLICE
239 .RAM_IMPLEMENTATION ("SLICE")
240 `else
241 .RAM_IMPLEMENTATION ("AUTO")
242 `endif
243 `endif
244 ) way_0_data_ram
245 (
246 // ----- Inputs -------
247 .read_clk (clk_i),
248 .write_clk (clk_i),
249 .reset (rst_i),
250 .read_address (dmem_read_address),
251 .enable_read (read_port_enable),
252 .write_address (dmem_write_address),
253 .enable_write (write_port_enable),
254 .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
255 .write_data (dmem_write_data[(j+1)*8-1:j*8]),
256 // ----- Outputs -------
257 .read_data (way_data[i][(j+1)*8-1:j*8])
258 );
259 end
260 end
262 // Way tags
263 lm32_ram
264 #(
265 // ----- Parameters -------
266 .data_width (`LM32_DC_TAGS_WIDTH),
267 .address_width (`LM32_DC_TMEM_ADDR_WIDTH),
268 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
269 .RAM_IMPLEMENTATION ("EBR"),
270 .RAM_TYPE ("RAM_DP_TRUE")
271 `else
272 `ifdef CFG_DCACHE_DAT_USE_SLICE
273 .RAM_IMPLEMENTATION ("SLICE")
274 `else
275 .RAM_IMPLEMENTATION ("AUTO")
276 `endif
277 `endif
278 ) way_0_tag_ram
279 (
280 // ----- Inputs -------
281 .read_clk (clk_i),
282 .write_clk (clk_i),
283 .reset (rst_i),
284 .read_address (tmem_read_address),
285 .enable_read (read_port_enable),
286 .write_address (tmem_write_address),
287 .enable_write (`TRUE),
288 .write_enable (way_tmem_we[i]),
289 .write_data (tmem_write_data),
290 // ----- Outputs -------
291 .read_data ({way_tag[i], way_valid[i]})
292 );
293 end
295 endgenerate
297 /////////////////////////////////////////////////////
298 // Combinational logic
299 /////////////////////////////////////////////////////
301 // Compute which ways in the cache match the address being read
302 generate
303 for (i = 0; i < associativity; i = i + 1)
304 begin : match
305 assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
306 end
307 endgenerate
309 // Select data from way that matched the address being read
310 generate
311 if (associativity == 1)
312 begin : data_1
313 assign load_data = way_data[0];
314 end
315 else if (associativity == 2)
316 begin : data_2
317 assign load_data = way_match[0] ? way_data[0] : way_data[1];
318 end
319 endgenerate
321 generate
322 if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
323 begin
324 // Select data to write to data memories
325 always @(*)
326 begin
327 if (refill == `TRUE)
328 dmem_write_data = refill_data;
329 else
330 begin
331 dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG];
332 dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG];
333 dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG];
334 dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG];
335 end
336 end
337 end
338 else
339 begin
340 // Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work
341 always @(*)
342 begin
343 if (refill == `TRUE)
344 dmem_write_data = refill_data;
345 else
346 dmem_write_data = store_data;
347 end
348 end
349 endgenerate
351 // Compute address to use to index into the data memories
352 generate
353 if (bytes_per_line > 4)
354 assign dmem_write_address = (refill == `TRUE)
355 ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
356 : address_m[`LM32_DC_ADDR_IDX_RNG];
357 else
358 assign dmem_write_address = (refill == `TRUE)
359 ? refill_address[`LM32_DC_ADDR_SET_RNG]
360 : address_m[`LM32_DC_ADDR_IDX_RNG];
361 endgenerate
362 assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
363 // Compute address to use to index into the tag memories
364 assign tmem_write_address = (flushing == `TRUE)
365 ? flush_set
366 : refill_address[`LM32_DC_ADDR_SET_RNG];
367 assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
369 // Compute signal to indicate when we are on the last refill accesses
370 generate
371 if (bytes_per_line > 4)
372 assign last_refill = refill_offset == {addr_offset_width{1'b1}};
373 else
374 assign last_refill = `TRUE;
375 endgenerate
377 // Compute data and tag memory access enable
378 assign read_port_enable = (stall_x == `FALSE);
379 assign write_port_enable = (refill_ready == `TRUE) || !stall_m;
381 // Determine when we have a valid store
382 assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
384 // Compute data and tag memory write enables
385 generate
386 if (associativity == 1)
387 begin : we_1
388 assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
389 assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
390 end
391 else
392 begin : we_2
393 assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
394 assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
395 assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE);
396 assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE);
397 end
398 endgenerate
400 // On the last refill cycle set the valid bit, for all other writes it should be cleared
401 assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE);
402 assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG];
404 // Signals that indicate which state we are in
405 assign flushing = state[0];
406 assign check = state[1];
407 assign refill = state[2];
409 assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE);
410 assign stall_request = (check == `FALSE);
412 /////////////////////////////////////////////////////
413 // Sequential logic
414 /////////////////////////////////////////////////////
416 // Record way selected for replacement on a cache miss
417 generate
418 if (associativity >= 2)
419 begin : way_select
420 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
421 begin
422 if (rst_i == `TRUE)
423 refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
424 else
425 begin
426 if (refill_request == `TRUE)
427 refill_way_select <= {refill_way_select[0], refill_way_select[1]};
428 end
429 end
430 end
431 endgenerate
433 // Record whether we are currently refilling
434 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
435 begin
436 if (rst_i == `TRUE)
437 refilling <= `FALSE;
438 else
439 refilling <= refill;
440 end
442 // Instruction cache control FSM
443 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
444 begin
445 if (rst_i == `TRUE)
446 begin
447 state <= `LM32_DC_STATE_FLUSH;
448 flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
449 refill_request <= `FALSE;
450 refill_address <= {`LM32_WORD_WIDTH{1'bx}};
451 restart_request <= `FALSE;
452 end
453 else
454 begin
455 case (state)
457 // Flush the cache
458 `LM32_DC_STATE_FLUSH:
459 begin
460 if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
461 state <= `LM32_DC_STATE_CHECK;
462 flush_set <= flush_set - 1'b1;
463 end
465 // Check for cache misses
466 `LM32_DC_STATE_CHECK:
467 begin
468 if (stall_a == `FALSE)
469 restart_request <= `FALSE;
470 if (miss == `TRUE)
471 begin
472 refill_request <= `TRUE;
473 refill_address <= address_m;
474 state <= `LM32_DC_STATE_REFILL;
475 end
476 else if (dflush == `TRUE)
477 state <= `LM32_DC_STATE_FLUSH;
478 end
480 // Refill a cache line
481 `LM32_DC_STATE_REFILL:
482 begin
483 refill_request <= `FALSE;
484 if (refill_ready == `TRUE)
485 begin
486 if (last_refill == `TRUE)
487 begin
488 restart_request <= `TRUE;
489 state <= `LM32_DC_STATE_CHECK;
490 end
491 end
492 end
494 endcase
495 end
496 end
498 generate
499 if (bytes_per_line > 4)
500 begin
501 // Refill offset
502 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
503 begin
504 if (rst_i == `TRUE)
505 refill_offset <= {addr_offset_width{1'b0}};
506 else
507 begin
508 case (state)
510 // Check for cache misses
511 `LM32_DC_STATE_CHECK:
512 begin
513 if (miss == `TRUE)
514 refill_offset <= {addr_offset_width{1'b0}};
515 end
517 // Refill a cache line
518 `LM32_DC_STATE_REFILL:
519 begin
520 if (refill_ready == `TRUE)
521 refill_offset <= refill_offset + 1'b1;
522 end
524 endcase
525 end
526 end
527 end
528 endgenerate
530 endmodule
532 `endif