1.1 diff -r cd0b58aa6f83 -r 07be9df9fee8 document/lm32.htm 1.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 +++ b/document/lm32.htm Fri Aug 13 01:13:04 2010 +0100 1.4 @@ -0,0 +1,645 @@ 1.5 +<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN"> 1.6 + 1.7 +<html> 1.8 + 1.9 +<head> 1.10 +<title>LatticeMico32 processor</title> 1.11 +<meta http-equiv="content-type" content="text/html; charset=windows-1252"> 1.12 +<meta name="generator" content="RoboHelp by eHelp Corporation www.ehelp.com"> 1.13 +<link rel="stylesheet" href="lever40_ns.css"><script type="text/javascript" language="JavaScript" title="WebHelpSplitCss"> 1.14 +<!-- 1.15 +if (navigator.appName !="Netscape") 1.16 +{ document.write("<link rel='stylesheet' href='lever40.css'>");} 1.17 +//--> 1.18 +</script> 1.19 +<style> 1.20 +<!-- 1.21 +body { border-left-style:None; border-right-style:None; border-top-style:None; border-bottom-style:None; } 1.22 +--> 1.23 +</style><style type="text/css"> 1.24 +<!-- 1.25 +img_whs1 { border:none; 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1.108 + 1.109 + } 1.110 + 1.111 + 1.112 + if (window.setRelStartPage) 1.113 + { 1.114 + setRelStartPage("MSB_Peripherals.htm"); 1.115 + 1.116 + autoSync(0); 1.117 + sendSyncInfo(); 1.118 + sendAveInfoOut(); 1.119 + } 1.120 + 1.121 +} 1.122 +else 1.123 + if (window.gbIE4) 1.124 + document.location.reload(); 1.125 +//--> 1.126 +</script> 1.127 +</head> 1.128 +<body><script type="text/javascript" language="javascript1.2"> 1.129 +<!-- 1.130 +if (window.writeIntopicBar) 1.131 + writeIntopicBar(4); 1.132 +//--> 1.133 +</script> 1.134 +<h1>LatticeMico32 Processor <a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1> 1.135 + 1.136 +<p>The LatticeMico32 processor is a high-performance 32-bit microprocessor 1.137 + optimized for Lattice Semiconductor field-programmable gate arrays. </p> 1.138 + 1.139 +<p class="whs2"><span style="font-style: italic;"><I>*If the 1.140 + processor manual fails to open, see the note at the bottom of this page.</I></span></p> 1.141 + 1.142 +<h2>Revision History</h2> 1.143 + 1.144 +<table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3"> 1.145 +<script language='JavaScript'><!-- 1.146 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' width='738' height='84' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>"); 1.147 +//--></script> 1.148 +<col class="whs4"> 1.149 +<col class="whs5"> 1.150 + 1.151 +<tr valign="top" class="whs6"> 1.152 +<td bgcolor="#DEE8F4" width="93px" class="whs7"> 1.153 +<p class=Table 1.154 + style="font-weight: bold;">Version</td> 1.155 +<td bgcolor="#DEE8F4" width="598px" class="whs8"> 1.156 +<p class=Table 1.157 + style="font-weight: bold;">Description</td></tr> 1.158 + 1.159 +<tr valign="top" class="whs6"> 1.160 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.161 +<p class=Table 1.162 + style="font-weight: normal;">3.5</td> 1.163 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.164 +<p class=whs10 1.165 + style="margin-left: 0px;">Support added to allow Inline Memories to 1.166 + be generated as non-power-of-two, as long as they are a multiple of 1024 1.167 + bytes</td></tr> 1.168 + 1.169 +<tr valign="top" class="whs6"> 1.170 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.171 +<p class=Table 1.172 + style="font-weight: normal;">3.3</td> 1.173 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.174 +<p class=whs10 1.175 + style="margin-left: 0px;">Added Inline Memory to support on-chip memory 1.176 + connected through a local bus.</td></tr> 1.177 + 1.178 +<tr valign="top" class="whs6"> 1.179 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.180 +<p class=Table 1.181 + style="font-weight: normal;">3.2</td> 1.182 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.183 +<p class=whs10 1.184 + style="margin-left: 0px;">Added Memory Type to instruction cache and 1.185 + data cache.</td></tr> 1.186 + 1.187 +<tr valign="top" class="whs6"> 1.188 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.189 +<p class=Table 1.190 + style="font-weight: normal;">3.1</td> 1.191 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.192 +<p class="whs11">Added static predictor to improve the behavior 1.193 + of branches.</p> 1.194 +<p class="whs11">Added support for optionally mapping the register 1.195 + file to EBRs (on-chip memory).</p> 1.196 +<p class="whs11">Added support for selecting between distributed 1.197 + RAM and EBRs (pseudo-dual port or true-dual port) for instruction and 1.198 + data caches.</td></tr> 1.199 + 1.200 +<tr valign="top" class="whs6"> 1.201 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.202 +<p class=Table 1.203 + style="font-weight: normal;"><span style="font-weight: normal;">3.0 1.204 + </span></td> 1.205 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.206 +<p class="whs11">Fixed incorrect handling of data cache miss 1.207 + in the presence of an instruction cache miss.</td></tr> 1.208 + 1.209 +<tr valign="top" class="whs6"> 1.210 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.211 +<p class="whs11">1.0</td> 1.212 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.213 +<p class="whs11">Initial version.</td></tr> 1.214 +<script language='JavaScript'><!-- 1.215 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>"); 1.216 +//--></script> 1.217 +</table> 1.218 + 1.219 + 1.220 + 1.221 +<h2>Dialog Box Parameters – 1.222 + General Tab</h2> 1.223 + 1.224 +<table x-use-null-cells cellspacing="0" class="whs12"> 1.225 +<col class="whs13"> 1.226 +<col class="whs14"> 1.227 + 1.228 +<tr valign="top" class="whs15"> 1.229 +<td bgcolor="#DEE8F4" width="167px" class="whs16"> 1.230 +<p class=Table 1.231 + style="font-weight: bold;">Parameter</td> 1.232 +<td bgcolor="#DEE8F4" width="524px" class="whs17"> 1.233 +<p class=Table 1.234 + style="font-weight: bold;">Description</td></tr> 1.235 + 1.236 +<tr valign="top" class="whs15"> 1.237 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.238 +<p class=Table 1.239 + style="font-weight: normal;">Instance Name</td> 1.240 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.241 +<p class=Table 1.242 + style="margin-left: 14px;">Specifies the name of the LatticeMico32 1.243 + processor. Alphanumeric values and underscores are supported. The default 1.244 + is LM32.</td></tr> 1.245 + 1.246 +<tr valign="top" class="whs15"> 1.247 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.248 +<p class=Table 1.249 + style="font-weight: bold;">Settings</td> 1.250 +</tr> 1.251 + 1.252 +<tr valign="top" class="whs15"> 1.253 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.254 +<p class=Table>Use EBRs for Register File</td> 1.255 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.256 +<p class=Table>Uses embedded block RAMS for the register file.</td></tr> 1.257 + 1.258 +<tr valign="top" class="whs15"> 1.259 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.260 +<p class=Table>Enable Divide</td> 1.261 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.262 +<p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, 1.263 + modu</span>).</td></tr> 1.264 + 1.265 +<tr valign="top" class="whs15"> 1.266 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.267 +<p class=Table>Enable Sign Extend</td> 1.268 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.269 +<p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, 1.270 + sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr> 1.271 + 1.272 +<tr valign="top" class="whs15"> 1.273 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.274 +<p class=Table>Location of Exception Handlers</td> 1.275 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.276 +<p class=Table>Specifies the default value for the vector table. This can 1.277 + be changed by updating the EBA control register or status register.</p> 1.278 +<p class=Table>This address must be aligned to a 256-byte boundary, since 1.279 + the hardware ignores the least-significant byte. Unpredictable behavior 1.280 + occurs when the exception base address and the exception vectors are not 1.281 + aligned on a 256-byte boundary.</td></tr> 1.282 + 1.283 +<tr valign="top" class="whs15"> 1.284 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.285 +<p class=Table 1.286 + style="font-weight: bold;">Multiplier Settings</td> 1.287 +</tr> 1.288 + 1.289 +<tr valign="top" class="whs15"> 1.290 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.291 +<p class=Table>Enable Multiplier</td> 1.292 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.293 +<p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, 1.294 + muli)</span>.</td></tr> 1.295 + 1.296 +<tr valign="top" class="whs15"> 1.297 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.298 +<p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td> 1.299 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.300 +<p class=Table>Enables the multiplier using the DSP block, if available.</td></tr> 1.301 + 1.302 +<tr valign="top" class="whs15"> 1.303 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.304 +<p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td> 1.305 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.306 +<p class=Table>Enables the multiplier using LUTs.</td></tr> 1.307 + 1.308 +<tr valign="top" class="whs15"> 1.309 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.310 +<p class=Table 1.311 + style="font-weight: bold;">Instruction Cache</td> 1.312 +</tr> 1.313 + 1.314 +<tr valign="top" class="whs15"> 1.315 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.316 +<p class=Table>Instruction Cache Enabled</td> 1.317 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.318 +<p class=Table 1.319 + style="margin-left: 14px;">Determines whether an instruction cache 1.320 + is implemented.</td></tr> 1.321 + 1.322 +<tr valign="top" class="whs15"> 1.323 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.324 +<p class=Table>Number of Sets</td> 1.325 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.326 +<p class=Table 1.327 + style="margin-left: 14px;">Specifies the number of sets in the instruction 1.328 + cache. Supported values are 128, 256, 512, 1024.</td></tr> 1.329 + 1.330 +<tr valign="top" class="whs15"> 1.331 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.332 +<p class=Table>Set Associativity</td> 1.333 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.334 +<p class=Table 1.335 + style="margin-left: 14px;">Specifies the associativity of the instruction 1.336 + cache. Supported values are 1, 2.</td></tr> 1.337 + 1.338 +<tr valign="top" class="whs15"> 1.339 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.340 +<p class=Table>Bytes/Cache Line</td> 1.341 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.342 +<p class=Table 1.343 + style="margin-left: 15px;">Specifies the number of bytes per instruction 1.344 + cache line. Supported values are 4, 8, 16.</td></tr> 1.345 + 1.346 +<tr valign="top" class="whs15"> 1.347 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.348 +<p class=Table>Memory Type</td> 1.349 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.350 +<p class=Table 1.351 + style="margin-left: 15px;">Determines the FPGA resource to be used 1.352 + to implement the instruction cache. The decision can be left to the synthesis 1.353 + tool (Auto), or you can select from the following options:</p> 1.354 +<ul type="disc" class="whs22"> 1.355 + 1.356 + <li class=kadov-p-CBullet><p class=Bullet>Auto – 1.357 + Leaves the implementation of the instruction cache to the synthesis tool.</p></li> 1.358 + 1.359 + <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM – 1.360 + Implements the instruction cache as distributed RAM.</p></li> 1.361 + 1.362 + <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR – 1.363 + Implements the instruction cache as dual-port EBR (two read/write ports).</p></li> 1.364 + 1.365 + <li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR – Implements 1.366 + the instruction cache as pseudo-dual-port EBR (one read port and one write 1.367 + port). </p></li> 1.368 +</ul></td></tr> 1.369 + 1.370 +<tr valign="top" class="whs15"> 1.371 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.372 +<p class=Table 1.373 + style="font-weight: bold;">Debug Setting</td> 1.374 +</tr> 1.375 + 1.376 +<tr valign="top" class="whs15"> 1.377 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.378 +<p class=Table>Enable Debug Interface</td> 1.379 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.380 +<p class=Table>Includes the debugger stub in the CPU, which is required 1.381 + for debugging.</td></tr> 1.382 + 1.383 +<tr valign="top" class="whs15"> 1.384 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.385 +<p class=Table># of H/W Watchpoint Registers</td> 1.386 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.387 +<p class=Table 1.388 + style="font-weight: normal;">Specifies the number of hardware watchpoint 1.389 + registers to be used in the debugging process.</td></tr> 1.390 + 1.391 +<tr valign="top" class="whs15"> 1.392 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.393 +<p class=Table>Enable Debugging Code in Flash or ROM</td> 1.394 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.395 +<p class=Table 1.396 + style="font-weight: normal;">Enables you to set hardware breakpoints 1.397 + in read-only memory.</td></tr> 1.398 + 1.399 +<tr valign="top" class="whs15"> 1.400 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.401 +<p class=Table># of H/W Breakpoint Registers</td> 1.402 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.403 +<p class=Table>Specifies the number of hardware breakpoint registers to 1.404 + be used in the debugging process.</td></tr> 1.405 + 1.406 +<tr valign="top" class="whs15"> 1.407 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.408 +<p class=Table>Enable PC Trace</td> 1.409 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.410 +<p class=Table>Enables the Program Counter Trace feature, which enables 1.411 + you to run the program trace during debug to find items in your C or C++ 1.412 + Code during debug, such as breakpoints and exceptions. Refer to <span 1.413 + style="font-weight: bold;"><B>Help > Help Contents > Lattice Software 1.414 + Project Environment > Concepts > Program Counter Trace</B></span> for 1.415 + more information on Program Counter Trace.</td></tr> 1.416 + 1.417 +<tr valign="top" class="whs15"> 1.418 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.419 +<p class=Table>Trace Depth</td> 1.420 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.421 +<p class=Table>Enables you to specify the depth of the Program Counter 1.422 + Trace buffer. Refer to <span style="font-weight: bold;"><B>Help > Help 1.423 + Contents > Lattice Software Project Environment > 1.424 + Concepts > Program Counter Trace</B></span> for more information on Program 1.425 + Counter Trace.</td></tr> 1.426 + 1.427 +<tr valign="top" class="whs15"> 1.428 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.429 +<p class=Table 1.430 + style="font-weight: bold;">Shifter Settings</td> 1.431 +</tr> 1.432 + 1.433 +<tr valign="top" class="whs15"> 1.434 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.435 +<p class=Table>Enable Shifter</td> 1.436 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.437 +<p>Enables the multi-bit shift instructions (sr, sri, sru, srui, sl, sli). 1.438 + </td></tr> 1.439 + 1.440 +<tr valign="top" class="whs15"> 1.441 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.442 +<p class=Table>Enable Piplined Barrel Shifter</td> 1.443 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.444 +<p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 1.445 + to perform a shift operation in three cycles.</td></tr> 1.446 + 1.447 +<tr valign="top" class="whs15"> 1.448 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.449 +<p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td> 1.450 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.451 +<p>Enables multi-cycle shift operation for the barrel shifter. The barrel 1.452 + shifter is implemented to shift one bit per cycle and take thirty-two 1.453 + cycles to complete.</td></tr> 1.454 + 1.455 +<tr valign="top" class="whs15"> 1.456 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.457 +<p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td> 1.458 +</tr> 1.459 + 1.460 +<tr valign="top" class="whs15"> 1.461 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.462 +<p class=Table>Data Cache Enabled</td> 1.463 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.464 +<p class=Table>Determines whether a data cache is implemented.</td></tr> 1.465 + 1.466 +<tr valign="top" class="whs15"> 1.467 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.468 +<p class=Table>Number of Sets</td> 1.469 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.470 +<p class=Table>Specifies the number of sets in the data cache. Supported 1.471 + values are 128, 256, 512, 1024.</td></tr> 1.472 + 1.473 +<tr valign="top" class="whs15"> 1.474 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.475 +<p class=Table>Set Associativity</td> 1.476 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.477 +<p class=Table>Specifies the associativity of the data cache. Supported 1.478 + values are 1, 2.</td></tr> 1.479 + 1.480 +<tr valign="top" class="whs15"> 1.481 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.482 +<p class=Table>Bytes/Cache Line</td> 1.483 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.484 +<p class=Table>Specifies the number of bytes per data cache line. Supported 1.485 + values are 4, 8, 16.</td></tr> 1.486 + 1.487 +<tr valign="top" class="whs15"> 1.488 +<td colspan="1" rowspan="1" width="167px" class="whs23"> 1.489 +<p class=Table>Memory Type</td> 1.490 +<td colspan="1" rowspan="1" width="524px" class="whs24"> 1.491 +<p class=Table>Determines the FPGA resource to be used to implement the 1.492 + data cache. The decision can be left to the synthesis tool (Auto), or 1.493 + you can select from the following options:</p> 1.494 +<ul> 1.495 + 1.496 + <li class=kadov-p-CBullet><p class=Bullet>Auto – 1.497 + Leaves the implementation of the data cache to the synthesis tool.</p></li> 1.498 + 1.499 + <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM – 1.500 + Implements the data cache as distributed RAM.</p></li> 1.501 + 1.502 + <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR – 1.503 + Implements the data cache as dual-port EBR (two read/write ports).</p></li> 1.504 +</ul></td></tr> 1.505 +</table> 1.506 + 1.507 +<p> </p> 1.508 + 1.509 +<h2>Dialog Box Parameters – 1.510 + Inline Memory Tab</h2> 1.511 + 1.512 +<table x-use-null-cells cellspacing="0" class="whs12"> 1.513 +<col class="whs13"> 1.514 +<col class="whs14"> 1.515 + 1.516 +<tr valign="top" class="whs15"> 1.517 +<td bgcolor="#DEE8F4" width="167px" class="whs25"> 1.518 +<p class=Table 1.519 + style="font-weight: bold;">Parameter</td> 1.520 +<td bgcolor="#DEE8F4" width="524px" class="whs26"> 1.521 +<p class=Table 1.522 + style="font-weight: bold;">Description</td></tr> 1.523 + 1.524 +<tr valign="top" class="whs15"> 1.525 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 1.526 +<p class=Table 1.527 + style="font-weight: bold;">Instruction Inline Memory</td> 1.528 +</tr> 1.529 + 1.530 +<tr valign="top" class="whs15"> 1.531 +<td width="167px" class="whs28"> 1.532 +<p class=Table>Enable</td> 1.533 +<td width="524px" class="whs29"> 1.534 +<p class=Table>Enables the instruction inline memory</td></tr> 1.535 + 1.536 +<tr valign="top" class="whs15"> 1.537 +<td width="167px" class="whs28"> 1.538 +<p class=Table>Instance Name</td> 1.539 +<td width="524px" class="whs29"> 1.540 +<p class=Table>Specifics the name of the instruction inline memory. Alphanumeric 1.541 + values and underscores are supported. The default is Instruction_IM.</td></tr> 1.542 + 1.543 +<tr valign="top" class="whs15"> 1.544 +<td width="167px" class="whs28"> 1.545 +<p class=Table>Base Address</td> 1.546 +<td width="524px" class="whs29"> 1.547 +<p class=Table>Specifies the base address for the instruction inline memory. 1.548 + The default is 0x10000000.</td></tr> 1.549 + 1.550 +<tr valign="top" class="whs15"> 1.551 +<td width="167px" class="whs28"> 1.552 +<p class=Table>Size of Memory in Bytes</td> 1.553 +<td width="524px" class="whs29"> 1.554 +<p class=Table>Specifies the size of the instruction inline memory.</td></tr> 1.555 + 1.556 +<tr valign="top" class="whs15"> 1.557 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 1.558 +<p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td> 1.559 +</tr> 1.560 + 1.561 +<tr valign="top" class="whs15"> 1.562 +<td width="167px" class="whs28"> 1.563 +<p class=Table>Initialization File Name</td> 1.564 +<td width="524px" class="whs29"> 1.565 +<p class=Table>Specifies the name of the memory initialization file for 1.566 + instruction inline memory.</td></tr> 1.567 + 1.568 +<tr valign="top" class="whs15"> 1.569 +<td width="167px" class="whs28"> 1.570 +<p class=Table>File Format</td> 1.571 +<td width="524px" class="whs29"> 1.572 +<p class=Table>Specifies the format of the memory initialization file: 1.573 + hex or binary.</td></tr> 1.574 + 1.575 +<tr valign="top" class="whs15"> 1.576 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 1.577 +<p class=Table 1.578 + style="font-weight: bold;">Data Inline Memory</td> 1.579 +</tr> 1.580 + 1.581 +<tr valign="top" class="whs15"> 1.582 +<td width="167px" class="whs28"> 1.583 +<p class=Table>Enabled</td> 1.584 +<td width="524px" class="whs29"> 1.585 +<p class=Table>Enables the data inline memory.</td></tr> 1.586 + 1.587 +<tr valign="top" class="whs15"> 1.588 +<td width="167px" class="whs28"> 1.589 +<p class=Table>Instance Name</td> 1.590 +<td width="524px" class="whs29"> 1.591 +<p class=Table>Specifies the name of the data inline memory. Alphanumeric 1.592 + values and underscores are supported. The default is Data_IM.</td></tr> 1.593 + 1.594 +<tr valign="top" class="whs15"> 1.595 +<td width="167px" class="whs28"> 1.596 +<p class=Table>Base Address</td> 1.597 +<td width="524px" class="whs29"> 1.598 +<p class=Table>Specifies the base address for the data inline memory. The 1.599 + default is 0x20000000.</td></tr> 1.600 + 1.601 +<tr valign="top" class="whs15"> 1.602 +<td width="167px" class="whs28"> 1.603 +<p class=Table>Size of Memory in Bytes</td> 1.604 +<td width="524px" class="whs29"> 1.605 +<p class=Table>Specifies the size of the data inline memory.</td></tr> 1.606 + 1.607 +<tr valign="top" class="whs15"> 1.608 +<td colspan="2" rowspan="1" width="691px" class="whs27"> 1.609 +<p class=Table 1.610 + style="font-weight: bold;">Memory File</td> 1.611 +</tr> 1.612 + 1.613 +<tr valign="top" class="whs15"> 1.614 +<td colspan="1" rowspan="1" width="167px" class="whs28"> 1.615 +<p class=Table>Initialization File Name</td> 1.616 +<td colspan="1" rowspan="1" width="524px" class="whs29"> 1.617 +<p class=Table>Specifies the name of the memory initialization file for 1.618 + data inline memory.</td></tr> 1.619 + 1.620 +<tr valign="top" class="whs15"> 1.621 +<td colspan="1" rowspan="1" width="167px" class="whs30"> 1.622 +<p class=Table>File Format</td> 1.623 +<td colspan="1" rowspan="1" width="524px" class="whs31"> 1.624 +<p class=Table>Specifies the format of the memory initialization file: 1.625 + hex or binary.</td></tr> 1.626 +</table> 1.627 + 1.628 +<p> </p> 1.629 + 1.630 +<p>For the revision history of the component RTL files, refer to the header 1.631 + of each component Verilog source file. </p> 1.632 + 1.633 +<p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual 1.634 + fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, 1.635 + and then click the note button.</p> 1.636 + 1.637 +<script type="text/javascript" language="JavaScript"> 1.638 +<!-- 1.639 + if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) 1.640 + document.write("<div id='tooltip' class='WebHelpPopupMenu'></div>"); 1.641 +//--> 1.642 +</script><script type="text/javascript" language="javascript1.2"> 1.643 +<!-- 1.644 +if (window.writeIntopicBar) 1.645 + writeIntopicBar(0); 1.646 +//--> 1.647 +</script> 1.648 +</body> 1.649 +</html>