1.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_cpu.v 1.2 --- a/lm32_cpu.v Sun Mar 06 21:14:43 2011 +0000 1.3 +++ b/lm32_cpu.v Sat Aug 06 00:02:46 2011 +0100 1.4 @@ -1,24 +1,50 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 +// ================================================================== 1.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.16 +// ------------------------------------------------------------------ 1.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.18 +// ALL RIGHTS RESERVED 1.19 +// ------------------------------------------------------------------ 1.20 +// 1.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.22 +// 1.23 +// Permission: 1.24 +// 1.25 +// Lattice Semiconductor grants permission to use this code 1.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.27 +// Open Source License Agreement. 1.28 +// 1.29 +// Disclaimer: 1.30 // 1.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.34 -// U.S.A email: techsupport@latticesemi.com 1.35 -// =============================================================================/ 1.36 +// Lattice Semiconductor provides no warranty regarding the use or 1.37 +// functionality of this code. It is the user's responsibility to 1.38 +// verify the user’s design for consistency and functionality through 1.39 +// the use of formal verification methods. 1.40 +// 1.41 +// -------------------------------------------------------------------- 1.42 +// 1.43 +// Lattice Semiconductor Corporation 1.44 +// 5555 NE Moore Court 1.45 +// Hillsboro, OR 97214 1.46 +// U.S.A 1.47 +// 1.48 +// TEL: 1-800-Lattice (USA and Canada) 1.49 +// 503-286-8001 (other locations) 1.50 +// 1.51 +// web: http://www.latticesemi.com/ 1.52 +// email: techsupport@latticesemi.com 1.53 +// 1.54 +// -------------------------------------------------------------------- 1.55 // FILE DETAILS 1.56 // Project : LatticeMico32 1.57 // File : lm32_cpu.v 1.58 // Title : Top-level of CPU. 1.59 // Dependencies : lm32_include.v 1.60 // 1.61 +// Version 3.8 1.62 +// 1. Feature: Support for dynamically switching EBA to DEBA via a GPIO. 1.63 +// 2. Bug: EA now reports instruction that caused the data abort, rather than 1.64 +// next instruction. 1.65 +// 1.66 // Version 3.4 1.67 // 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 1.68 // never serviced. 1.69 @@ -75,6 +101,11 @@ 1.70 clk_n_i, 1.71 `endif 1.72 rst_i, 1.73 +`ifdef CFG_DEBUG_ENABLED 1.74 + `ifdef CFG_ALTERNATE_EBA 1.75 + at_debug, 1.76 + `endif 1.77 +`endif 1.78 // From external devices 1.79 `ifdef CFG_INTERRUPTS_ENABLED 1.80 interrupt_n, 1.81 @@ -212,6 +243,12 @@ 1.82 `endif 1.83 input rst_i; // Reset 1.84 1.85 +`ifdef CFG_DEBUG_ENABLED 1.86 + `ifdef CFG_ALTERNATE_EBA 1.87 + input at_debug; // GPIO input that maps EBA to DEBA 1.88 + `endif 1.89 +`endif 1.90 + 1.91 `ifdef CFG_INTERRUPTS_ENABLED 1.92 input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low 1.93 `endif 1.94 @@ -751,6 +788,11 @@ 1.95 // ----- Inputs ------- 1.96 .clk_i (clk_i), 1.97 .rst_i (rst_i), 1.98 +`ifdef CFG_DEBUG_ENABLED 1.99 + `ifdef CFG_ALTERNATE_EBA 1.100 + .at_debug (at_debug), 1.101 + `endif 1.102 +`endif 1.103 // From pipeline 1.104 .stall_a (stall_a), 1.105 .stall_f (stall_f), 1.106 @@ -1256,15 +1298,15 @@ 1.107 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.108 if (rst_i == `TRUE) 1.109 begin 1.110 - regfile_raw_0 <= 1'b0; 1.111 - regfile_raw_1 <= 1'b0; 1.112 - w_result_d <= 32'b0; 1.113 + regfile_raw_0 <= #1 1'b0; 1.114 + regfile_raw_1 <= #1 1'b0; 1.115 + w_result_d <= #1 32'b0; 1.116 end 1.117 else 1.118 begin 1.119 - regfile_raw_0 <= regfile_raw_0_nxt; 1.120 - regfile_raw_1 <= regfile_raw_1_nxt; 1.121 - w_result_d <= w_result; 1.122 + regfile_raw_0 <= #1 regfile_raw_0_nxt; 1.123 + regfile_raw_1 <= #1 regfile_raw_1_nxt; 1.124 + w_result_d <= #1 w_result; 1.125 end 1.126 1.127 /*---------------------------------------------------------------------- 1.128 @@ -2090,14 +2132,14 @@ 1.129 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.130 begin 1.131 if (rst_i == `TRUE) 1.132 - eba <= eba_reset[`LM32_PC_WIDTH+2-1:8]; 1.133 + eba <= #1 eba_reset[`LM32_PC_WIDTH+2-1:8]; 1.134 else 1.135 begin 1.136 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE)) 1.137 - eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.138 + eba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.139 `ifdef CFG_HW_DEBUG_ENABLED 1.140 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA)) 1.141 - eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.142 + eba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.143 `endif 1.144 end 1.145 end 1.146 @@ -2107,14 +2149,14 @@ 1.147 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.148 begin 1.149 if (rst_i == `TRUE) 1.150 - deba <= deba_reset[`LM32_PC_WIDTH+2-1:8]; 1.151 + deba <= #1 deba_reset[`LM32_PC_WIDTH+2-1:8]; 1.152 else 1.153 begin 1.154 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE)) 1.155 - deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.156 + deba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.157 `ifdef CFG_HW_DEBUG_ENABLED 1.158 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA)) 1.159 - deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.160 + deba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.161 `endif 1.162 end 1.163 end 1.164 @@ -2125,9 +2167,9 @@ 1.165 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.166 begin 1.167 if (rst_i == `TRUE) 1.168 - cc <= {`LM32_WORD_WIDTH{1'b0}}; 1.169 + cc <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.170 else 1.171 - cc <= cc + 1'b1; 1.172 + cc <= #1 cc + 1'b1; 1.173 end 1.174 `endif 1.175 1.176 @@ -2136,15 +2178,15 @@ 1.177 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.178 begin 1.179 if (rst_i == `TRUE) 1.180 - data_bus_error_seen <= `FALSE; 1.181 + data_bus_error_seen <= #1 `FALSE; 1.182 else 1.183 begin 1.184 // Set flag when bus error is detected 1.185 if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE)) 1.186 - data_bus_error_seen <= `TRUE; 1.187 + data_bus_error_seen <= #1 `TRUE; 1.188 // Clear flag when exception is taken 1.189 if ((exception_m == `TRUE) && (kill_m == `FALSE)) 1.190 - data_bus_error_seen <= `FALSE; 1.191 + data_bus_error_seen <= #1 `FALSE; 1.192 end 1.193 end 1.194 `endif 1.195 @@ -2195,48 +2237,48 @@ 1.196 begin 1.197 if (rst_i == `TRUE) 1.198 begin 1.199 - valid_f <= `FALSE; 1.200 - valid_d <= `FALSE; 1.201 - valid_x <= `FALSE; 1.202 - valid_m <= `FALSE; 1.203 - valid_w <= `FALSE; 1.204 + valid_f <= #1 `FALSE; 1.205 + valid_d <= #1 `FALSE; 1.206 + valid_x <= #1 `FALSE; 1.207 + valid_m <= #1 `FALSE; 1.208 + valid_w <= #1 `FALSE; 1.209 end 1.210 else 1.211 begin 1.212 if ((kill_f == `TRUE) || (stall_a == `FALSE)) 1.213 `ifdef LM32_CACHE_ENABLED 1.214 - valid_f <= valid_a; 1.215 + valid_f <= #1 valid_a; 1.216 `else 1.217 - valid_f <= `TRUE; 1.218 + valid_f <= #1 `TRUE; 1.219 `endif 1.220 else if (stall_f == `FALSE) 1.221 - valid_f <= `FALSE; 1.222 + valid_f <= #1 `FALSE; 1.223 1.224 if (kill_d == `TRUE) 1.225 - valid_d <= `FALSE; 1.226 + valid_d <= #1 `FALSE; 1.227 else if (stall_f == `FALSE) 1.228 - valid_d <= valid_f & !kill_f; 1.229 + valid_d <= #1 valid_f & !kill_f; 1.230 else if (stall_d == `FALSE) 1.231 - valid_d <= `FALSE; 1.232 + valid_d <= #1 `FALSE; 1.233 1.234 if (stall_d == `FALSE) 1.235 - valid_x <= valid_d & !kill_d; 1.236 + valid_x <= #1 valid_d & !kill_d; 1.237 else if (kill_x == `TRUE) 1.238 - valid_x <= `FALSE; 1.239 + valid_x <= #1 `FALSE; 1.240 else if (stall_x == `FALSE) 1.241 - valid_x <= `FALSE; 1.242 + valid_x <= #1 `FALSE; 1.243 1.244 if (kill_m == `TRUE) 1.245 - valid_m <= `FALSE; 1.246 + valid_m <= #1 `FALSE; 1.247 else if (stall_x == `FALSE) 1.248 - valid_m <= valid_x & !kill_x; 1.249 + valid_m <= #1 valid_x & !kill_x; 1.250 else if (stall_m == `FALSE) 1.251 - valid_m <= `FALSE; 1.252 + valid_m <= #1 `FALSE; 1.253 1.254 if (stall_m == `FALSE) 1.255 - valid_w <= valid_m & !kill_m; 1.256 + valid_w <= #1 valid_m & !kill_m; 1.257 else 1.258 - valid_w <= `FALSE; 1.259 + valid_w <= #1 `FALSE; 1.260 end 1.261 end 1.262 1.263 @@ -2246,113 +2288,113 @@ 1.264 if (rst_i == `TRUE) 1.265 begin 1.266 `ifdef CFG_USER_ENABLED 1.267 - user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}}; 1.268 + user_opcode <= #1 {`LM32_USER_OPCODE_WIDTH{1'b0}}; 1.269 `endif 1.270 - operand_0_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.271 - operand_1_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.272 - store_operand_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.273 - branch_target_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.274 - x_result_sel_csr_x <= `FALSE; 1.275 + operand_0_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.276 + operand_1_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.277 + store_operand_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.278 + branch_target_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.279 + x_result_sel_csr_x <= #1 `FALSE; 1.280 `ifdef LM32_MC_ARITHMETIC_ENABLED 1.281 - x_result_sel_mc_arith_x <= `FALSE; 1.282 + x_result_sel_mc_arith_x <= #1 `FALSE; 1.283 `endif 1.284 `ifdef LM32_NO_BARREL_SHIFT 1.285 - x_result_sel_shift_x <= `FALSE; 1.286 + x_result_sel_shift_x <= #1 `FALSE; 1.287 `endif 1.288 `ifdef CFG_SIGN_EXTEND_ENABLED 1.289 - x_result_sel_sext_x <= `FALSE; 1.290 + x_result_sel_sext_x <= #1 `FALSE; 1.291 `endif 1.292 - x_result_sel_logic_x <= `FALSE; 1.293 + x_result_sel_logic_x <= #1 `FALSE; 1.294 `ifdef CFG_USER_ENABLED 1.295 - x_result_sel_user_x <= `FALSE; 1.296 + x_result_sel_user_x <= #1 `FALSE; 1.297 `endif 1.298 - x_result_sel_add_x <= `FALSE; 1.299 - m_result_sel_compare_x <= `FALSE; 1.300 + x_result_sel_add_x <= #1 `FALSE; 1.301 + m_result_sel_compare_x <= #1 `FALSE; 1.302 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.303 - m_result_sel_shift_x <= `FALSE; 1.304 + m_result_sel_shift_x <= #1 `FALSE; 1.305 `endif 1.306 - w_result_sel_load_x <= `FALSE; 1.307 + w_result_sel_load_x <= #1 `FALSE; 1.308 `ifdef CFG_PL_MULTIPLY_ENABLED 1.309 - w_result_sel_mul_x <= `FALSE; 1.310 + w_result_sel_mul_x <= #1 `FALSE; 1.311 `endif 1.312 - x_bypass_enable_x <= `FALSE; 1.313 - m_bypass_enable_x <= `FALSE; 1.314 - write_enable_x <= `FALSE; 1.315 - write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.316 - csr_x <= {`LM32_CSR_WIDTH{1'b0}}; 1.317 - load_x <= `FALSE; 1.318 - store_x <= `FALSE; 1.319 - size_x <= {`LM32_SIZE_WIDTH{1'b0}}; 1.320 - sign_extend_x <= `FALSE; 1.321 - adder_op_x <= `FALSE; 1.322 - adder_op_x_n <= `FALSE; 1.323 - logic_op_x <= 4'h0; 1.324 + x_bypass_enable_x <= #1 `FALSE; 1.325 + m_bypass_enable_x <= #1 `FALSE; 1.326 + write_enable_x <= #1 `FALSE; 1.327 + write_idx_x <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 1.328 + csr_x <= #1 {`LM32_CSR_WIDTH{1'b0}}; 1.329 + load_x <= #1 `FALSE; 1.330 + store_x <= #1 `FALSE; 1.331 + size_x <= #1 {`LM32_SIZE_WIDTH{1'b0}}; 1.332 + sign_extend_x <= #1 `FALSE; 1.333 + adder_op_x <= #1 `FALSE; 1.334 + adder_op_x_n <= #1 `FALSE; 1.335 + logic_op_x <= #1 4'h0; 1.336 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.337 - direction_x <= `FALSE; 1.338 + direction_x <= #1 `FALSE; 1.339 `endif 1.340 `ifdef CFG_ROTATE_ENABLED 1.341 - rotate_x <= `FALSE; 1.342 + rotate_x <= #1 `FALSE; 1.343 1.344 `endif 1.345 - branch_x <= `FALSE; 1.346 - branch_predict_x <= `FALSE; 1.347 - branch_predict_taken_x <= `FALSE; 1.348 - condition_x <= `LM32_CONDITION_U1; 1.349 + branch_x <= #1 `FALSE; 1.350 + branch_predict_x <= #1 `FALSE; 1.351 + branch_predict_taken_x <= #1 `FALSE; 1.352 + condition_x <= #1 `LM32_CONDITION_U1; 1.353 `ifdef CFG_DEBUG_ENABLED 1.354 - break_x <= `FALSE; 1.355 + break_x <= #1 `FALSE; 1.356 `endif 1.357 - scall_x <= `FALSE; 1.358 - eret_x <= `FALSE; 1.359 + scall_x <= #1 `FALSE; 1.360 + eret_x <= #1 `FALSE; 1.361 `ifdef CFG_DEBUG_ENABLED 1.362 - bret_x <= `FALSE; 1.363 + bret_x <= #1 `FALSE; 1.364 `endif 1.365 `ifdef CFG_BUS_ERRORS_ENABLED 1.366 - bus_error_x <= `FALSE; 1.367 - data_bus_error_exception_m <= `FALSE; 1.368 + bus_error_x <= #1 `FALSE; 1.369 + data_bus_error_exception_m <= #1 `FALSE; 1.370 `endif 1.371 - csr_write_enable_x <= `FALSE; 1.372 - operand_m <= {`LM32_WORD_WIDTH{1'b0}}; 1.373 - branch_target_m <= {`LM32_WORD_WIDTH{1'b0}}; 1.374 - m_result_sel_compare_m <= `FALSE; 1.375 + csr_write_enable_x <= #1 `FALSE; 1.376 + operand_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.377 + branch_target_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.378 + m_result_sel_compare_m <= #1 `FALSE; 1.379 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.380 - m_result_sel_shift_m <= `FALSE; 1.381 + m_result_sel_shift_m <= #1 `FALSE; 1.382 `endif 1.383 - w_result_sel_load_m <= `FALSE; 1.384 + w_result_sel_load_m <= #1 `FALSE; 1.385 `ifdef CFG_PL_MULTIPLY_ENABLED 1.386 - w_result_sel_mul_m <= `FALSE; 1.387 + w_result_sel_mul_m <= #1 `FALSE; 1.388 `endif 1.389 - m_bypass_enable_m <= `FALSE; 1.390 - branch_m <= `FALSE; 1.391 - branch_predict_m <= `FALSE; 1.392 - branch_predict_taken_m <= `FALSE; 1.393 - exception_m <= `FALSE; 1.394 - load_m <= `FALSE; 1.395 - store_m <= `FALSE; 1.396 - write_enable_m <= `FALSE; 1.397 - write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.398 - condition_met_m <= `FALSE; 1.399 + m_bypass_enable_m <= #1 `FALSE; 1.400 + branch_m <= #1 `FALSE; 1.401 + branch_predict_m <= #1 `FALSE; 1.402 + branch_predict_taken_m <= #1 `FALSE; 1.403 + exception_m <= #1 `FALSE; 1.404 + load_m <= #1 `FALSE; 1.405 + store_m <= #1 `FALSE; 1.406 + write_enable_m <= #1 `FALSE; 1.407 + write_idx_m <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 1.408 + condition_met_m <= #1 `FALSE; 1.409 `ifdef CFG_DCACHE_ENABLED 1.410 - dflush_m <= `FALSE; 1.411 + dflush_m <= #1 `FALSE; 1.412 `endif 1.413 `ifdef CFG_DEBUG_ENABLED 1.414 - debug_exception_m <= `FALSE; 1.415 - non_debug_exception_m <= `FALSE; 1.416 + debug_exception_m <= #1 `FALSE; 1.417 + non_debug_exception_m <= #1 `FALSE; 1.418 `endif 1.419 - operand_w <= {`LM32_WORD_WIDTH{1'b0}}; 1.420 - w_result_sel_load_w <= `FALSE; 1.421 + operand_w <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.422 + w_result_sel_load_w <= #1 `FALSE; 1.423 `ifdef CFG_PL_MULTIPLY_ENABLED 1.424 - w_result_sel_mul_w <= `FALSE; 1.425 + w_result_sel_mul_w <= #1 `FALSE; 1.426 `endif 1.427 - write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.428 - write_enable_w <= `FALSE; 1.429 + write_idx_w <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 1.430 + write_enable_w <= #1 `FALSE; 1.431 `ifdef CFG_DEBUG_ENABLED 1.432 - debug_exception_w <= `FALSE; 1.433 - non_debug_exception_w <= `FALSE; 1.434 + debug_exception_w <= #1 `FALSE; 1.435 + non_debug_exception_w <= #1 `FALSE; 1.436 `else 1.437 - exception_w <= `FALSE; 1.438 + exception_w <= #1 `FALSE; 1.439 `endif 1.440 `ifdef CFG_BUS_ERRORS_ENABLED 1.441 - memop_pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.442 + memop_pc_w <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.443 `endif 1.444 end 1.445 else 1.446 @@ -2362,105 +2404,105 @@ 1.447 if (stall_x == `FALSE) 1.448 begin 1.449 `ifdef CFG_USER_ENABLED 1.450 - user_opcode <= user_opcode_d; 1.451 + user_opcode <= #1 user_opcode_d; 1.452 `endif 1.453 - operand_0_x <= d_result_0; 1.454 - operand_1_x <= d_result_1; 1.455 - store_operand_x <= bypass_data_1; 1.456 - branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 1.457 - x_result_sel_csr_x <= x_result_sel_csr_d; 1.458 + operand_0_x <= #1 d_result_0; 1.459 + operand_1_x <= #1 d_result_1; 1.460 + store_operand_x <= #1 bypass_data_1; 1.461 + branch_target_x <= #1 branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 1.462 + x_result_sel_csr_x <= #1 x_result_sel_csr_d; 1.463 `ifdef LM32_MC_ARITHMETIC_ENABLED 1.464 - x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d; 1.465 + x_result_sel_mc_arith_x <= #1 x_result_sel_mc_arith_d; 1.466 `endif 1.467 `ifdef LM32_NO_BARREL_SHIFT 1.468 - x_result_sel_shift_x <= x_result_sel_shift_d; 1.469 + x_result_sel_shift_x <= #1 x_result_sel_shift_d; 1.470 `endif 1.471 `ifdef CFG_SIGN_EXTEND_ENABLED 1.472 - x_result_sel_sext_x <= x_result_sel_sext_d; 1.473 + x_result_sel_sext_x <= #1 x_result_sel_sext_d; 1.474 `endif 1.475 - x_result_sel_logic_x <= x_result_sel_logic_d; 1.476 + x_result_sel_logic_x <= #1 x_result_sel_logic_d; 1.477 `ifdef CFG_USER_ENABLED 1.478 - x_result_sel_user_x <= x_result_sel_user_d; 1.479 + x_result_sel_user_x <= #1 x_result_sel_user_d; 1.480 `endif 1.481 - x_result_sel_add_x <= x_result_sel_add_d; 1.482 - m_result_sel_compare_x <= m_result_sel_compare_d; 1.483 + x_result_sel_add_x <= #1 x_result_sel_add_d; 1.484 + m_result_sel_compare_x <= #1 m_result_sel_compare_d; 1.485 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.486 - m_result_sel_shift_x <= m_result_sel_shift_d; 1.487 + m_result_sel_shift_x <= #1 m_result_sel_shift_d; 1.488 `endif 1.489 - w_result_sel_load_x <= w_result_sel_load_d; 1.490 + w_result_sel_load_x <= #1 w_result_sel_load_d; 1.491 `ifdef CFG_PL_MULTIPLY_ENABLED 1.492 - w_result_sel_mul_x <= w_result_sel_mul_d; 1.493 + w_result_sel_mul_x <= #1 w_result_sel_mul_d; 1.494 `endif 1.495 - x_bypass_enable_x <= x_bypass_enable_d; 1.496 - m_bypass_enable_x <= m_bypass_enable_d; 1.497 - load_x <= load_d; 1.498 - store_x <= store_d; 1.499 - branch_x <= branch_d; 1.500 - branch_predict_x <= branch_predict_d; 1.501 - branch_predict_taken_x <= branch_predict_taken_d; 1.502 - write_idx_x <= write_idx_d; 1.503 - csr_x <= csr_d; 1.504 - size_x <= size_d; 1.505 - sign_extend_x <= sign_extend_d; 1.506 - adder_op_x <= adder_op_d; 1.507 - adder_op_x_n <= ~adder_op_d; 1.508 - logic_op_x <= logic_op_d; 1.509 + x_bypass_enable_x <= #1 x_bypass_enable_d; 1.510 + m_bypass_enable_x <= #1 m_bypass_enable_d; 1.511 + load_x <= #1 load_d; 1.512 + store_x <= #1 store_d; 1.513 + branch_x <= #1 branch_d; 1.514 + branch_predict_x <= #1 branch_predict_d; 1.515 + branch_predict_taken_x <= #1 branch_predict_taken_d; 1.516 + write_idx_x <= #1 write_idx_d; 1.517 + csr_x <= #1 csr_d; 1.518 + size_x <= #1 size_d; 1.519 + sign_extend_x <= #1 sign_extend_d; 1.520 + adder_op_x <= #1 adder_op_d; 1.521 + adder_op_x_n <= #1 ~adder_op_d; 1.522 + logic_op_x <= #1 logic_op_d; 1.523 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.524 - direction_x <= direction_d; 1.525 + direction_x <= #1 direction_d; 1.526 `endif 1.527 `ifdef CFG_ROTATE_ENABLED 1.528 - rotate_x <= rotate_d; 1.529 + rotate_x <= #1 rotate_d; 1.530 `endif 1.531 - condition_x <= condition_d; 1.532 - csr_write_enable_x <= csr_write_enable_d; 1.533 + condition_x <= #1 condition_d; 1.534 + csr_write_enable_x <= #1 csr_write_enable_d; 1.535 `ifdef CFG_DEBUG_ENABLED 1.536 - break_x <= break_d; 1.537 + break_x <= #1 break_d; 1.538 `endif 1.539 - scall_x <= scall_d; 1.540 + scall_x <= #1 scall_d; 1.541 `ifdef CFG_BUS_ERRORS_ENABLED 1.542 - bus_error_x <= bus_error_d; 1.543 + bus_error_x <= #1 bus_error_d; 1.544 `endif 1.545 - eret_x <= eret_d; 1.546 + eret_x <= #1 eret_d; 1.547 `ifdef CFG_DEBUG_ENABLED 1.548 - bret_x <= bret_d; 1.549 + bret_x <= #1 bret_d; 1.550 `endif 1.551 - write_enable_x <= write_enable_d; 1.552 + write_enable_x <= #1 write_enable_d; 1.553 end 1.554 1.555 // X/M stage registers 1.556 1.557 if (stall_m == `FALSE) 1.558 begin 1.559 - operand_m <= x_result; 1.560 - m_result_sel_compare_m <= m_result_sel_compare_x; 1.561 + operand_m <= #1 x_result; 1.562 + m_result_sel_compare_m <= #1 m_result_sel_compare_x; 1.563 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.564 - m_result_sel_shift_m <= m_result_sel_shift_x; 1.565 + m_result_sel_shift_m <= #1 m_result_sel_shift_x; 1.566 `endif 1.567 if (exception_x == `TRUE) 1.568 begin 1.569 - w_result_sel_load_m <= `FALSE; 1.570 + w_result_sel_load_m <= #1 `FALSE; 1.571 `ifdef CFG_PL_MULTIPLY_ENABLED 1.572 - w_result_sel_mul_m <= `FALSE; 1.573 + w_result_sel_mul_m <= #1 `FALSE; 1.574 `endif 1.575 end 1.576 else 1.577 begin 1.578 - w_result_sel_load_m <= w_result_sel_load_x; 1.579 + w_result_sel_load_m <= #1 w_result_sel_load_x; 1.580 `ifdef CFG_PL_MULTIPLY_ENABLED 1.581 - w_result_sel_mul_m <= w_result_sel_mul_x; 1.582 + w_result_sel_mul_m <= #1 w_result_sel_mul_x; 1.583 `endif 1.584 end 1.585 - m_bypass_enable_m <= m_bypass_enable_x; 1.586 + m_bypass_enable_m <= #1 m_bypass_enable_x; 1.587 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.588 `endif 1.589 - load_m <= load_x; 1.590 - store_m <= store_x; 1.591 + load_m <= #1 load_x; 1.592 + store_m <= #1 store_x; 1.593 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.594 - branch_m <= branch_x && !branch_taken_x; 1.595 + branch_m <= #1 branch_x && !branch_taken_x; 1.596 `else 1.597 - branch_m <= branch_x; 1.598 - branch_predict_m <= branch_predict_x; 1.599 - branch_predict_taken_m <= branch_predict_taken_x; 1.600 + branch_m <= #1 branch_x; 1.601 + branch_predict_m <= #1 branch_predict_x; 1.602 + branch_predict_taken_m <= #1 branch_predict_taken_x; 1.603 `endif 1.604 `ifdef CFG_DEBUG_ENABLED 1.605 // Data bus errors are generated by the wishbone and are 1.606 @@ -2469,45 +2511,48 @@ 1.607 // in same cycle (causing a debug exception). Handle non 1.608 // -debug exception first! 1.609 if (non_debug_exception_x == `TRUE) 1.610 - write_idx_m <= `LM32_EA_REG; 1.611 + write_idx_m <= #1 `LM32_EA_REG; 1.612 else if (debug_exception_x == `TRUE) 1.613 - write_idx_m <= `LM32_BA_REG; 1.614 + write_idx_m <= #1 `LM32_BA_REG; 1.615 else 1.616 - write_idx_m <= write_idx_x; 1.617 + write_idx_m <= #1 write_idx_x; 1.618 `else 1.619 if (exception_x == `TRUE) 1.620 - write_idx_m <= `LM32_EA_REG; 1.621 + write_idx_m <= #1 `LM32_EA_REG; 1.622 else 1.623 - write_idx_m <= write_idx_x; 1.624 + write_idx_m <= #1 write_idx_x; 1.625 `endif 1.626 - condition_met_m <= condition_met_x; 1.627 + condition_met_m <= #1 condition_met_x; 1.628 `ifdef CFG_DEBUG_ENABLED 1.629 if (exception_x == `TRUE) 1.630 if ((dc_re == `TRUE) 1.631 + `ifdef CFG_ALTERNATE_EBA 1.632 + || (at_debug == `TRUE) 1.633 + `endif 1.634 || ((debug_exception_x == `TRUE) 1.635 && (non_debug_exception_x == `FALSE))) 1.636 - branch_target_m <= {deba, eid_x, {3{1'b0}}}; 1.637 + branch_target_m <= #1 {deba, eid_x, {3{1'b0}}}; 1.638 else 1.639 - branch_target_m <= {eba, eid_x, {3{1'b0}}}; 1.640 + branch_target_m <= #1 {eba, eid_x, {3{1'b0}}}; 1.641 else 1.642 - branch_target_m <= branch_target_x; 1.643 + branch_target_m <= #1 branch_target_x; 1.644 `else 1.645 - branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 1.646 + branch_target_m <= #1 exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 1.647 `endif 1.648 `ifdef CFG_TRACE_ENABLED 1.649 - eid_m <= eid_x; 1.650 + eid_m <= #1 eid_x; 1.651 `endif 1.652 `ifdef CFG_DCACHE_ENABLED 1.653 - dflush_m <= dflush_x; 1.654 + dflush_m <= #1 dflush_x; 1.655 `endif 1.656 - eret_m <= eret_q_x; 1.657 + eret_m <= #1 eret_q_x; 1.658 `ifdef CFG_DEBUG_ENABLED 1.659 - bret_m <= bret_q_x; 1.660 + bret_m <= #1 bret_q_x; 1.661 `endif 1.662 - write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x; 1.663 + write_enable_m <= #1 exception_x == `TRUE ? `TRUE : write_enable_x; 1.664 `ifdef CFG_DEBUG_ENABLED 1.665 - debug_exception_m <= debug_exception_x; 1.666 - non_debug_exception_m <= non_debug_exception_x; 1.667 + debug_exception_m <= #1 debug_exception_x; 1.668 + non_debug_exception_m <= #1 non_debug_exception_x; 1.669 `endif 1.670 end 1.671 1.672 @@ -2515,11 +2560,11 @@ 1.673 if (stall_m == `FALSE) 1.674 begin 1.675 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 1.676 - exception_m <= `TRUE; 1.677 + exception_m <= #1 `TRUE; 1.678 else 1.679 - exception_m <= `FALSE; 1.680 + exception_m <= #1 `FALSE; 1.681 `ifdef CFG_BUS_ERRORS_ENABLED 1.682 - data_bus_error_exception_m <= (data_bus_error_exception == `TRUE) 1.683 + data_bus_error_exception_m <= #1 (data_bus_error_exception == `TRUE) 1.684 `ifdef CFG_DEBUG_ENABLED 1.685 && (reset_exception == `FALSE) 1.686 `endif 1.687 @@ -2529,36 +2574,37 @@ 1.688 1.689 // M/W stage registers 1.690 `ifdef CFG_BUS_ERRORS_ENABLED 1.691 - operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 1.692 + operand_w <= #1 exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 1.693 `else 1.694 - operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 1.695 + operand_w <= #1 exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 1.696 `endif 1.697 - w_result_sel_load_w <= w_result_sel_load_m; 1.698 + w_result_sel_load_w <= #1 w_result_sel_load_m; 1.699 `ifdef CFG_PL_MULTIPLY_ENABLED 1.700 - w_result_sel_mul_w <= w_result_sel_mul_m; 1.701 + w_result_sel_mul_w <= #1 w_result_sel_mul_m; 1.702 `endif 1.703 - write_idx_w <= write_idx_m; 1.704 + write_idx_w <= #1 write_idx_m; 1.705 `ifdef CFG_TRACE_ENABLED 1.706 - eid_w <= eid_m; 1.707 - eret_w <= eret_m; 1.708 + eid_w <= #1 eid_m; 1.709 + eret_w <= #1 eret_m; 1.710 `ifdef CFG_DEBUG_ENABLED 1.711 - bret_w <= bret_m; 1.712 + bret_w <= #1 bret_m; 1.713 `endif 1.714 `endif 1.715 - write_enable_w <= write_enable_m; 1.716 + write_enable_w <= #1 write_enable_m; 1.717 `ifdef CFG_DEBUG_ENABLED 1.718 - debug_exception_w <= debug_exception_m; 1.719 - non_debug_exception_w <= non_debug_exception_m; 1.720 + debug_exception_w <= #1 debug_exception_m; 1.721 + non_debug_exception_w <= #1 non_debug_exception_m; 1.722 `else 1.723 - exception_w <= exception_m; 1.724 + exception_w <= #1 exception_m; 1.725 `endif 1.726 `ifdef CFG_BUS_ERRORS_ENABLED 1.727 if ( (stall_m == `FALSE) 1.728 + && (data_bus_error_exception == `FALSE) 1.729 && ( (load_q_m == `TRUE) 1.730 || (store_q_m == `TRUE) 1.731 ) 1.732 ) 1.733 - memop_pc_w <= pc_m; 1.734 + memop_pc_w <= #1 pc_m; 1.735 `endif 1.736 end 1.737 end 1.738 @@ -2570,26 +2616,26 @@ 1.739 begin 1.740 if (rst_i == `TRUE) 1.741 begin 1.742 - use_buf <= `FALSE; 1.743 - reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}}; 1.744 - reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}}; 1.745 + use_buf <= #1 `FALSE; 1.746 + reg_data_buf_0 <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.747 + reg_data_buf_1 <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.748 end 1.749 else 1.750 begin 1.751 if (stall_d == `FALSE) 1.752 - use_buf <= `FALSE; 1.753 + use_buf <= #1 `FALSE; 1.754 else if (use_buf == `FALSE) 1.755 begin 1.756 - reg_data_buf_0 <= reg_data_live_0; 1.757 - reg_data_buf_1 <= reg_data_live_1; 1.758 - use_buf <= `TRUE; 1.759 + reg_data_buf_0 <= #1 reg_data_live_0; 1.760 + reg_data_buf_1 <= #1 reg_data_live_1; 1.761 + use_buf <= #1 `TRUE; 1.762 end 1.763 if (reg_write_enable_q_w == `TRUE) 1.764 begin 1.765 if (write_idx_w == read_idx_0_d) 1.766 - reg_data_buf_0 <= w_result; 1.767 + reg_data_buf_0 <= #1 w_result; 1.768 if (write_idx_w == read_idx_1_d) 1.769 - reg_data_buf_1 <= w_result; 1.770 + reg_data_buf_1 <= #1 w_result; 1.771 end 1.772 end 1.773 end 1.774 @@ -2601,42 +2647,42 @@ 1.775 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.776 begin 1.777 if (rst_i == `TRUE) begin 1.778 - registers[0] <= {`LM32_WORD_WIDTH{1'b0}}; 1.779 - registers[1] <= {`LM32_WORD_WIDTH{1'b0}}; 1.780 - registers[2] <= {`LM32_WORD_WIDTH{1'b0}}; 1.781 - registers[3] <= {`LM32_WORD_WIDTH{1'b0}}; 1.782 - registers[4] <= {`LM32_WORD_WIDTH{1'b0}}; 1.783 - registers[5] <= {`LM32_WORD_WIDTH{1'b0}}; 1.784 - registers[6] <= {`LM32_WORD_WIDTH{1'b0}}; 1.785 - registers[7] <= {`LM32_WORD_WIDTH{1'b0}}; 1.786 - registers[8] <= {`LM32_WORD_WIDTH{1'b0}}; 1.787 - registers[9] <= {`LM32_WORD_WIDTH{1'b0}}; 1.788 - registers[10] <= {`LM32_WORD_WIDTH{1'b0}}; 1.789 - registers[11] <= {`LM32_WORD_WIDTH{1'b0}}; 1.790 - registers[12] <= {`LM32_WORD_WIDTH{1'b0}}; 1.791 - registers[13] <= {`LM32_WORD_WIDTH{1'b0}}; 1.792 - registers[14] <= {`LM32_WORD_WIDTH{1'b0}}; 1.793 - registers[15] <= {`LM32_WORD_WIDTH{1'b0}}; 1.794 - registers[16] <= {`LM32_WORD_WIDTH{1'b0}}; 1.795 - registers[17] <= {`LM32_WORD_WIDTH{1'b0}}; 1.796 - registers[18] <= {`LM32_WORD_WIDTH{1'b0}}; 1.797 - registers[19] <= {`LM32_WORD_WIDTH{1'b0}}; 1.798 - registers[20] <= {`LM32_WORD_WIDTH{1'b0}}; 1.799 - registers[21] <= {`LM32_WORD_WIDTH{1'b0}}; 1.800 - registers[22] <= {`LM32_WORD_WIDTH{1'b0}}; 1.801 - registers[23] <= {`LM32_WORD_WIDTH{1'b0}}; 1.802 - registers[24] <= {`LM32_WORD_WIDTH{1'b0}}; 1.803 - registers[25] <= {`LM32_WORD_WIDTH{1'b0}}; 1.804 - registers[26] <= {`LM32_WORD_WIDTH{1'b0}}; 1.805 - registers[27] <= {`LM32_WORD_WIDTH{1'b0}}; 1.806 - registers[28] <= {`LM32_WORD_WIDTH{1'b0}}; 1.807 - registers[29] <= {`LM32_WORD_WIDTH{1'b0}}; 1.808 - registers[30] <= {`LM32_WORD_WIDTH{1'b0}}; 1.809 - registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 1.810 + registers[0] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.811 + registers[1] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.812 + registers[2] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.813 + registers[3] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.814 + registers[4] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.815 + registers[5] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.816 + registers[6] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.817 + registers[7] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.818 + registers[8] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.819 + registers[9] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.820 + registers[10] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.821 + registers[11] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.822 + registers[12] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.823 + registers[13] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.824 + registers[14] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.825 + registers[15] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.826 + registers[16] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.827 + registers[17] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.828 + registers[18] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.829 + registers[19] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.830 + registers[20] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.831 + registers[21] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.832 + registers[22] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.833 + registers[23] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.834 + registers[24] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.835 + registers[25] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.836 + registers[26] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.837 + registers[27] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.838 + registers[28] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.839 + registers[29] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.840 + registers[30] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.841 + registers[31] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.842 end 1.843 else begin 1.844 if (reg_write_enable_q_w == `TRUE) 1.845 - registers[write_idx_w] <= w_result; 1.846 + registers[write_idx_w] <= #1 w_result; 1.847 end 1.848 end 1.849 `endif 1.850 @@ -2647,19 +2693,19 @@ 1.851 begin 1.852 if (rst_i == `TRUE) 1.853 begin 1.854 - trace_pc_valid <= `FALSE; 1.855 - trace_pc <= {`LM32_PC_WIDTH{1'b0}}; 1.856 - trace_exception <= `FALSE; 1.857 - trace_eid <= `LM32_EID_RESET; 1.858 - trace_eret <= `FALSE; 1.859 + trace_pc_valid <= #1 `FALSE; 1.860 + trace_pc <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.861 + trace_exception <= #1 `FALSE; 1.862 + trace_eid <= #1 `LM32_EID_RESET; 1.863 + trace_eret <= #1 `FALSE; 1.864 `ifdef CFG_DEBUG_ENABLED 1.865 - trace_bret <= `FALSE; 1.866 + trace_bret <= #1 `FALSE; 1.867 `endif 1.868 - pc_c <= `CFG_EBA_RESET/4; 1.869 + pc_c <= #1 `CFG_EBA_RESET/4; 1.870 end 1.871 else 1.872 begin 1.873 - trace_pc_valid <= `FALSE; 1.874 + trace_pc_valid <= #1 `FALSE; 1.875 // Has an exception occured 1.876 `ifdef CFG_DEBUG_ENABLED 1.877 if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE)) 1.878 @@ -2667,13 +2713,13 @@ 1.879 if (exception_q_w == `TRUE) 1.880 `endif 1.881 begin 1.882 - trace_exception <= `TRUE; 1.883 - trace_pc_valid <= `TRUE; 1.884 - trace_pc <= pc_w; 1.885 - trace_eid <= eid_w; 1.886 + trace_exception <= #1 `TRUE; 1.887 + trace_pc_valid <= #1 `TRUE; 1.888 + trace_pc <= #1 pc_w; 1.889 + trace_eid <= #1 eid_w; 1.890 end 1.891 else 1.892 - trace_exception <= `FALSE; 1.893 + trace_exception <= #1 `FALSE; 1.894 1.895 if ((valid_w == `TRUE) && (!kill_w)) 1.896 begin 1.897 @@ -2681,22 +2727,22 @@ 1.898 if (pc_c + 1'b1 != pc_w) 1.899 begin 1.900 // Non-sequential instruction 1.901 - trace_pc_valid <= `TRUE; 1.902 - trace_pc <= pc_w; 1.903 + trace_pc_valid <= #1 `TRUE; 1.904 + trace_pc <= #1 pc_w; 1.905 end 1.906 // Record PC so we can determine if next instruction is sequential or not 1.907 - pc_c <= pc_w; 1.908 + pc_c <= #1 pc_w; 1.909 // Indicate if it was an eret/bret instruction 1.910 - trace_eret <= eret_w; 1.911 + trace_eret <= #1 eret_w; 1.912 `ifdef CFG_DEBUG_ENABLED 1.913 - trace_bret <= bret_w; 1.914 + trace_bret <= #1 bret_w; 1.915 `endif 1.916 end 1.917 else 1.918 begin 1.919 - trace_eret <= `FALSE; 1.920 + trace_eret <= #1 `FALSE; 1.921 `ifdef CFG_DEBUG_ENABLED 1.922 - trace_bret <= `FALSE; 1.923 + trace_bret <= #1 `FALSE; 1.924 `endif 1.925 end 1.926 end