1.1 diff -r a61bb364ae1f -r b153470d41c5 lm32_dcache.v 1.2 --- a/lm32_dcache.v Sun Apr 04 20:52:32 2010 +0100 1.3 +++ b/lm32_dcache.v Sun Apr 04 22:05:07 2010 +0100 1.4 @@ -195,8 +195,9 @@ 1.5 #( 1.6 // ----- Parameters ------- 1.7 .data_width (32), 1.8 - .address_width (`LM32_DC_DMEM_ADDR_WIDTH), 1.9 + .address_width (`LM32_DC_DMEM_ADDR_WIDTH) 1.10 `ifdef PLATFORM_LATTICE 1.11 + , 1.12 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE 1.13 .RAM_IMPLEMENTATION ("EBR"), 1.14 .RAM_TYPE ("RAM_DP_TRUE") 1.15 @@ -232,15 +233,18 @@ 1.16 #( 1.17 // ----- Parameters ------- 1.18 .data_width (8), 1.19 - .address_width (`LM32_DC_DMEM_ADDR_WIDTH), 1.20 -`ifdef CFG_DCACHE_DAT_USE_DP_TRUE 1.21 + .address_width (`LM32_DC_DMEM_ADDR_WIDTH) 1.22 +`ifdef PLATFORM_LATTICE 1.23 + , 1.24 + `ifdef CFG_DCACHE_DAT_USE_DP_TRUE 1.25 .RAM_IMPLEMENTATION ("EBR"), 1.26 .RAM_TYPE ("RAM_DP_TRUE") 1.27 -`else 1.28 - `ifdef CFG_DCACHE_DAT_USE_SLICE 1.29 + `else 1.30 + `ifdef CFG_DCACHE_DAT_USE_SLICE 1.31 .RAM_IMPLEMENTATION ("SLICE") 1.32 - `else 1.33 + `else 1.34 .RAM_IMPLEMENTATION ("AUTO") 1.35 + `endif 1.36 `endif 1.37 `endif 1.38 ) way_0_data_ram 1.39 @@ -266,15 +270,18 @@ 1.40 #( 1.41 // ----- Parameters ------- 1.42 .data_width (`LM32_DC_TAGS_WIDTH), 1.43 - .address_width (`LM32_DC_TMEM_ADDR_WIDTH), 1.44 -`ifdef CFG_DCACHE_DAT_USE_DP_TRUE 1.45 + .address_width (`LM32_DC_TMEM_ADDR_WIDTH) 1.46 +`ifdef PLATFORM_LATTICE 1.47 + , 1.48 + `ifdef CFG_DCACHE_DAT_USE_DP_TRUE 1.49 .RAM_IMPLEMENTATION ("EBR"), 1.50 .RAM_TYPE ("RAM_DP_TRUE") 1.51 -`else 1.52 - `ifdef CFG_DCACHE_DAT_USE_SLICE 1.53 + `else 1.54 + `ifdef CFG_DCACHE_DAT_USE_SLICE 1.55 .RAM_IMPLEMENTATION ("SLICE") 1.56 - `else 1.57 + `else 1.58 .RAM_IMPLEMENTATION ("AUTO") 1.59 + `endif 1.60 `endif 1.61 `endif 1.62 ) way_0_tag_ram