1.1 diff -r 73de224304c1 -r d6c693415d59 lm32_cpu.v 1.2 --- a/lm32_cpu.v Sat Aug 06 00:02:46 2011 +0100 1.3 +++ b/lm32_cpu.v Sat Aug 06 01:26:56 2011 +0100 1.4 @@ -1298,15 +1298,15 @@ 1.5 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.6 if (rst_i == `TRUE) 1.7 begin 1.8 - regfile_raw_0 <= #1 1'b0; 1.9 - regfile_raw_1 <= #1 1'b0; 1.10 - w_result_d <= #1 32'b0; 1.11 + regfile_raw_0 <= 1'b0; 1.12 + regfile_raw_1 <= 1'b0; 1.13 + w_result_d <= 32'b0; 1.14 end 1.15 else 1.16 begin 1.17 - regfile_raw_0 <= #1 regfile_raw_0_nxt; 1.18 - regfile_raw_1 <= #1 regfile_raw_1_nxt; 1.19 - w_result_d <= #1 w_result; 1.20 + regfile_raw_0 <= regfile_raw_0_nxt; 1.21 + regfile_raw_1 <= regfile_raw_1_nxt; 1.22 + w_result_d <= w_result; 1.23 end 1.24 1.25 /*---------------------------------------------------------------------- 1.26 @@ -2132,14 +2132,14 @@ 1.27 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.28 begin 1.29 if (rst_i == `TRUE) 1.30 - eba <= #1 eba_reset[`LM32_PC_WIDTH+2-1:8]; 1.31 + eba <= eba_reset[`LM32_PC_WIDTH+2-1:8]; 1.32 else 1.33 begin 1.34 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE)) 1.35 - eba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.36 + eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.37 `ifdef CFG_HW_DEBUG_ENABLED 1.38 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA)) 1.39 - eba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.40 + eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.41 `endif 1.42 end 1.43 end 1.44 @@ -2149,14 +2149,14 @@ 1.45 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.46 begin 1.47 if (rst_i == `TRUE) 1.48 - deba <= #1 deba_reset[`LM32_PC_WIDTH+2-1:8]; 1.49 + deba <= deba_reset[`LM32_PC_WIDTH+2-1:8]; 1.50 else 1.51 begin 1.52 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE)) 1.53 - deba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.54 + deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.55 `ifdef CFG_HW_DEBUG_ENABLED 1.56 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA)) 1.57 - deba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.58 + deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.59 `endif 1.60 end 1.61 end 1.62 @@ -2167,9 +2167,9 @@ 1.63 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.64 begin 1.65 if (rst_i == `TRUE) 1.66 - cc <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.67 + cc <= {`LM32_WORD_WIDTH{1'b0}}; 1.68 else 1.69 - cc <= #1 cc + 1'b1; 1.70 + cc <= cc + 1'b1; 1.71 end 1.72 `endif 1.73 1.74 @@ -2178,15 +2178,15 @@ 1.75 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.76 begin 1.77 if (rst_i == `TRUE) 1.78 - data_bus_error_seen <= #1 `FALSE; 1.79 + data_bus_error_seen <= `FALSE; 1.80 else 1.81 begin 1.82 // Set flag when bus error is detected 1.83 if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE)) 1.84 - data_bus_error_seen <= #1 `TRUE; 1.85 + data_bus_error_seen <= `TRUE; 1.86 // Clear flag when exception is taken 1.87 if ((exception_m == `TRUE) && (kill_m == `FALSE)) 1.88 - data_bus_error_seen <= #1 `FALSE; 1.89 + data_bus_error_seen <= `FALSE; 1.90 end 1.91 end 1.92 `endif 1.93 @@ -2237,48 +2237,48 @@ 1.94 begin 1.95 if (rst_i == `TRUE) 1.96 begin 1.97 - valid_f <= #1 `FALSE; 1.98 - valid_d <= #1 `FALSE; 1.99 - valid_x <= #1 `FALSE; 1.100 - valid_m <= #1 `FALSE; 1.101 - valid_w <= #1 `FALSE; 1.102 + valid_f <= `FALSE; 1.103 + valid_d <= `FALSE; 1.104 + valid_x <= `FALSE; 1.105 + valid_m <= `FALSE; 1.106 + valid_w <= `FALSE; 1.107 end 1.108 else 1.109 begin 1.110 if ((kill_f == `TRUE) || (stall_a == `FALSE)) 1.111 `ifdef LM32_CACHE_ENABLED 1.112 - valid_f <= #1 valid_a; 1.113 + valid_f <= valid_a; 1.114 `else 1.115 - valid_f <= #1 `TRUE; 1.116 + valid_f <= `TRUE; 1.117 `endif 1.118 else if (stall_f == `FALSE) 1.119 - valid_f <= #1 `FALSE; 1.120 + valid_f <= `FALSE; 1.121 1.122 if (kill_d == `TRUE) 1.123 - valid_d <= #1 `FALSE; 1.124 + valid_d <= `FALSE; 1.125 else if (stall_f == `FALSE) 1.126 - valid_d <= #1 valid_f & !kill_f; 1.127 + valid_d <= valid_f & !kill_f; 1.128 else if (stall_d == `FALSE) 1.129 - valid_d <= #1 `FALSE; 1.130 + valid_d <= `FALSE; 1.131 1.132 if (stall_d == `FALSE) 1.133 - valid_x <= #1 valid_d & !kill_d; 1.134 + valid_x <= valid_d & !kill_d; 1.135 else if (kill_x == `TRUE) 1.136 - valid_x <= #1 `FALSE; 1.137 + valid_x <= `FALSE; 1.138 else if (stall_x == `FALSE) 1.139 - valid_x <= #1 `FALSE; 1.140 + valid_x <= `FALSE; 1.141 1.142 if (kill_m == `TRUE) 1.143 - valid_m <= #1 `FALSE; 1.144 + valid_m <= `FALSE; 1.145 else if (stall_x == `FALSE) 1.146 - valid_m <= #1 valid_x & !kill_x; 1.147 + valid_m <= valid_x & !kill_x; 1.148 else if (stall_m == `FALSE) 1.149 - valid_m <= #1 `FALSE; 1.150 + valid_m <= `FALSE; 1.151 1.152 if (stall_m == `FALSE) 1.153 - valid_w <= #1 valid_m & !kill_m; 1.154 + valid_w <= valid_m & !kill_m; 1.155 else 1.156 - valid_w <= #1 `FALSE; 1.157 + valid_w <= `FALSE; 1.158 end 1.159 end 1.160 1.161 @@ -2288,113 +2288,113 @@ 1.162 if (rst_i == `TRUE) 1.163 begin 1.164 `ifdef CFG_USER_ENABLED 1.165 - user_opcode <= #1 {`LM32_USER_OPCODE_WIDTH{1'b0}}; 1.166 + user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}}; 1.167 `endif 1.168 - operand_0_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.169 - operand_1_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.170 - store_operand_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.171 - branch_target_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.172 - x_result_sel_csr_x <= #1 `FALSE; 1.173 + operand_0_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.174 + operand_1_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.175 + store_operand_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.176 + branch_target_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.177 + x_result_sel_csr_x <= `FALSE; 1.178 `ifdef LM32_MC_ARITHMETIC_ENABLED 1.179 - x_result_sel_mc_arith_x <= #1 `FALSE; 1.180 + x_result_sel_mc_arith_x <= `FALSE; 1.181 `endif 1.182 `ifdef LM32_NO_BARREL_SHIFT 1.183 - x_result_sel_shift_x <= #1 `FALSE; 1.184 + x_result_sel_shift_x <= `FALSE; 1.185 `endif 1.186 `ifdef CFG_SIGN_EXTEND_ENABLED 1.187 - x_result_sel_sext_x <= #1 `FALSE; 1.188 + x_result_sel_sext_x <= `FALSE; 1.189 `endif 1.190 - x_result_sel_logic_x <= #1 `FALSE; 1.191 + x_result_sel_logic_x <= `FALSE; 1.192 `ifdef CFG_USER_ENABLED 1.193 - x_result_sel_user_x <= #1 `FALSE; 1.194 + x_result_sel_user_x <= `FALSE; 1.195 `endif 1.196 - x_result_sel_add_x <= #1 `FALSE; 1.197 - m_result_sel_compare_x <= #1 `FALSE; 1.198 + x_result_sel_add_x <= `FALSE; 1.199 + m_result_sel_compare_x <= `FALSE; 1.200 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.201 - m_result_sel_shift_x <= #1 `FALSE; 1.202 + m_result_sel_shift_x <= `FALSE; 1.203 `endif 1.204 - w_result_sel_load_x <= #1 `FALSE; 1.205 + w_result_sel_load_x <= `FALSE; 1.206 `ifdef CFG_PL_MULTIPLY_ENABLED 1.207 - w_result_sel_mul_x <= #1 `FALSE; 1.208 + w_result_sel_mul_x <= `FALSE; 1.209 `endif 1.210 - x_bypass_enable_x <= #1 `FALSE; 1.211 - m_bypass_enable_x <= #1 `FALSE; 1.212 - write_enable_x <= #1 `FALSE; 1.213 - write_idx_x <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 1.214 - csr_x <= #1 {`LM32_CSR_WIDTH{1'b0}}; 1.215 - load_x <= #1 `FALSE; 1.216 - store_x <= #1 `FALSE; 1.217 - size_x <= #1 {`LM32_SIZE_WIDTH{1'b0}}; 1.218 - sign_extend_x <= #1 `FALSE; 1.219 - adder_op_x <= #1 `FALSE; 1.220 - adder_op_x_n <= #1 `FALSE; 1.221 - logic_op_x <= #1 4'h0; 1.222 + x_bypass_enable_x <= `FALSE; 1.223 + m_bypass_enable_x <= `FALSE; 1.224 + write_enable_x <= `FALSE; 1.225 + write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.226 + csr_x <= {`LM32_CSR_WIDTH{1'b0}}; 1.227 + load_x <= `FALSE; 1.228 + store_x <= `FALSE; 1.229 + size_x <= {`LM32_SIZE_WIDTH{1'b0}}; 1.230 + sign_extend_x <= `FALSE; 1.231 + adder_op_x <= `FALSE; 1.232 + adder_op_x_n <= `FALSE; 1.233 + logic_op_x <= 4'h0; 1.234 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.235 - direction_x <= #1 `FALSE; 1.236 + direction_x <= `FALSE; 1.237 `endif 1.238 `ifdef CFG_ROTATE_ENABLED 1.239 - rotate_x <= #1 `FALSE; 1.240 + rotate_x <= `FALSE; 1.241 1.242 `endif 1.243 - branch_x <= #1 `FALSE; 1.244 - branch_predict_x <= #1 `FALSE; 1.245 - branch_predict_taken_x <= #1 `FALSE; 1.246 - condition_x <= #1 `LM32_CONDITION_U1; 1.247 + branch_x <= `FALSE; 1.248 + branch_predict_x <= `FALSE; 1.249 + branch_predict_taken_x <= `FALSE; 1.250 + condition_x <= `LM32_CONDITION_U1; 1.251 `ifdef CFG_DEBUG_ENABLED 1.252 - break_x <= #1 `FALSE; 1.253 + break_x <= `FALSE; 1.254 `endif 1.255 - scall_x <= #1 `FALSE; 1.256 - eret_x <= #1 `FALSE; 1.257 + scall_x <= `FALSE; 1.258 + eret_x <= `FALSE; 1.259 `ifdef CFG_DEBUG_ENABLED 1.260 - bret_x <= #1 `FALSE; 1.261 + bret_x <= `FALSE; 1.262 `endif 1.263 `ifdef CFG_BUS_ERRORS_ENABLED 1.264 - bus_error_x <= #1 `FALSE; 1.265 - data_bus_error_exception_m <= #1 `FALSE; 1.266 + bus_error_x <= `FALSE; 1.267 + data_bus_error_exception_m <= `FALSE; 1.268 `endif 1.269 - csr_write_enable_x <= #1 `FALSE; 1.270 - operand_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.271 - branch_target_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.272 - m_result_sel_compare_m <= #1 `FALSE; 1.273 + csr_write_enable_x <= `FALSE; 1.274 + operand_m <= {`LM32_WORD_WIDTH{1'b0}}; 1.275 + branch_target_m <= {`LM32_WORD_WIDTH{1'b0}}; 1.276 + m_result_sel_compare_m <= `FALSE; 1.277 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.278 - m_result_sel_shift_m <= #1 `FALSE; 1.279 + m_result_sel_shift_m <= `FALSE; 1.280 `endif 1.281 - w_result_sel_load_m <= #1 `FALSE; 1.282 + w_result_sel_load_m <= `FALSE; 1.283 `ifdef CFG_PL_MULTIPLY_ENABLED 1.284 - w_result_sel_mul_m <= #1 `FALSE; 1.285 + w_result_sel_mul_m <= `FALSE; 1.286 `endif 1.287 - m_bypass_enable_m <= #1 `FALSE; 1.288 - branch_m <= #1 `FALSE; 1.289 - branch_predict_m <= #1 `FALSE; 1.290 - branch_predict_taken_m <= #1 `FALSE; 1.291 - exception_m <= #1 `FALSE; 1.292 - load_m <= #1 `FALSE; 1.293 - store_m <= #1 `FALSE; 1.294 - write_enable_m <= #1 `FALSE; 1.295 - write_idx_m <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 1.296 - condition_met_m <= #1 `FALSE; 1.297 + m_bypass_enable_m <= `FALSE; 1.298 + branch_m <= `FALSE; 1.299 + branch_predict_m <= `FALSE; 1.300 + branch_predict_taken_m <= `FALSE; 1.301 + exception_m <= `FALSE; 1.302 + load_m <= `FALSE; 1.303 + store_m <= `FALSE; 1.304 + write_enable_m <= `FALSE; 1.305 + write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.306 + condition_met_m <= `FALSE; 1.307 `ifdef CFG_DCACHE_ENABLED 1.308 - dflush_m <= #1 `FALSE; 1.309 + dflush_m <= `FALSE; 1.310 `endif 1.311 `ifdef CFG_DEBUG_ENABLED 1.312 - debug_exception_m <= #1 `FALSE; 1.313 - non_debug_exception_m <= #1 `FALSE; 1.314 + debug_exception_m <= `FALSE; 1.315 + non_debug_exception_m <= `FALSE; 1.316 `endif 1.317 - operand_w <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.318 - w_result_sel_load_w <= #1 `FALSE; 1.319 + operand_w <= {`LM32_WORD_WIDTH{1'b0}}; 1.320 + w_result_sel_load_w <= `FALSE; 1.321 `ifdef CFG_PL_MULTIPLY_ENABLED 1.322 - w_result_sel_mul_w <= #1 `FALSE; 1.323 + w_result_sel_mul_w <= `FALSE; 1.324 `endif 1.325 - write_idx_w <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 1.326 - write_enable_w <= #1 `FALSE; 1.327 + write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.328 + write_enable_w <= `FALSE; 1.329 `ifdef CFG_DEBUG_ENABLED 1.330 - debug_exception_w <= #1 `FALSE; 1.331 - non_debug_exception_w <= #1 `FALSE; 1.332 + debug_exception_w <= `FALSE; 1.333 + non_debug_exception_w <= `FALSE; 1.334 `else 1.335 - exception_w <= #1 `FALSE; 1.336 + exception_w <= `FALSE; 1.337 `endif 1.338 `ifdef CFG_BUS_ERRORS_ENABLED 1.339 - memop_pc_w <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.340 + memop_pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.341 `endif 1.342 end 1.343 else 1.344 @@ -2404,105 +2404,105 @@ 1.345 if (stall_x == `FALSE) 1.346 begin 1.347 `ifdef CFG_USER_ENABLED 1.348 - user_opcode <= #1 user_opcode_d; 1.349 + user_opcode <= user_opcode_d; 1.350 `endif 1.351 - operand_0_x <= #1 d_result_0; 1.352 - operand_1_x <= #1 d_result_1; 1.353 - store_operand_x <= #1 bypass_data_1; 1.354 - branch_target_x <= #1 branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 1.355 - x_result_sel_csr_x <= #1 x_result_sel_csr_d; 1.356 + operand_0_x <= d_result_0; 1.357 + operand_1_x <= d_result_1; 1.358 + store_operand_x <= bypass_data_1; 1.359 + branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 1.360 + x_result_sel_csr_x <= x_result_sel_csr_d; 1.361 `ifdef LM32_MC_ARITHMETIC_ENABLED 1.362 - x_result_sel_mc_arith_x <= #1 x_result_sel_mc_arith_d; 1.363 + x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d; 1.364 `endif 1.365 `ifdef LM32_NO_BARREL_SHIFT 1.366 - x_result_sel_shift_x <= #1 x_result_sel_shift_d; 1.367 + x_result_sel_shift_x <= x_result_sel_shift_d; 1.368 `endif 1.369 `ifdef CFG_SIGN_EXTEND_ENABLED 1.370 - x_result_sel_sext_x <= #1 x_result_sel_sext_d; 1.371 + x_result_sel_sext_x <= x_result_sel_sext_d; 1.372 `endif 1.373 - x_result_sel_logic_x <= #1 x_result_sel_logic_d; 1.374 + x_result_sel_logic_x <= x_result_sel_logic_d; 1.375 `ifdef CFG_USER_ENABLED 1.376 - x_result_sel_user_x <= #1 x_result_sel_user_d; 1.377 + x_result_sel_user_x <= x_result_sel_user_d; 1.378 `endif 1.379 - x_result_sel_add_x <= #1 x_result_sel_add_d; 1.380 - m_result_sel_compare_x <= #1 m_result_sel_compare_d; 1.381 + x_result_sel_add_x <= x_result_sel_add_d; 1.382 + m_result_sel_compare_x <= m_result_sel_compare_d; 1.383 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.384 - m_result_sel_shift_x <= #1 m_result_sel_shift_d; 1.385 + m_result_sel_shift_x <= m_result_sel_shift_d; 1.386 `endif 1.387 - w_result_sel_load_x <= #1 w_result_sel_load_d; 1.388 + w_result_sel_load_x <= w_result_sel_load_d; 1.389 `ifdef CFG_PL_MULTIPLY_ENABLED 1.390 - w_result_sel_mul_x <= #1 w_result_sel_mul_d; 1.391 + w_result_sel_mul_x <= w_result_sel_mul_d; 1.392 `endif 1.393 - x_bypass_enable_x <= #1 x_bypass_enable_d; 1.394 - m_bypass_enable_x <= #1 m_bypass_enable_d; 1.395 - load_x <= #1 load_d; 1.396 - store_x <= #1 store_d; 1.397 - branch_x <= #1 branch_d; 1.398 - branch_predict_x <= #1 branch_predict_d; 1.399 - branch_predict_taken_x <= #1 branch_predict_taken_d; 1.400 - write_idx_x <= #1 write_idx_d; 1.401 - csr_x <= #1 csr_d; 1.402 - size_x <= #1 size_d; 1.403 - sign_extend_x <= #1 sign_extend_d; 1.404 - adder_op_x <= #1 adder_op_d; 1.405 - adder_op_x_n <= #1 ~adder_op_d; 1.406 - logic_op_x <= #1 logic_op_d; 1.407 + x_bypass_enable_x <= x_bypass_enable_d; 1.408 + m_bypass_enable_x <= m_bypass_enable_d; 1.409 + load_x <= load_d; 1.410 + store_x <= store_d; 1.411 + branch_x <= branch_d; 1.412 + branch_predict_x <= branch_predict_d; 1.413 + branch_predict_taken_x <= branch_predict_taken_d; 1.414 + write_idx_x <= write_idx_d; 1.415 + csr_x <= csr_d; 1.416 + size_x <= size_d; 1.417 + sign_extend_x <= sign_extend_d; 1.418 + adder_op_x <= adder_op_d; 1.419 + adder_op_x_n <= ~adder_op_d; 1.420 + logic_op_x <= logic_op_d; 1.421 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.422 - direction_x <= #1 direction_d; 1.423 + direction_x <= direction_d; 1.424 `endif 1.425 `ifdef CFG_ROTATE_ENABLED 1.426 - rotate_x <= #1 rotate_d; 1.427 + rotate_x <= rotate_d; 1.428 `endif 1.429 - condition_x <= #1 condition_d; 1.430 - csr_write_enable_x <= #1 csr_write_enable_d; 1.431 + condition_x <= condition_d; 1.432 + csr_write_enable_x <= csr_write_enable_d; 1.433 `ifdef CFG_DEBUG_ENABLED 1.434 - break_x <= #1 break_d; 1.435 + break_x <= break_d; 1.436 `endif 1.437 - scall_x <= #1 scall_d; 1.438 + scall_x <= scall_d; 1.439 `ifdef CFG_BUS_ERRORS_ENABLED 1.440 - bus_error_x <= #1 bus_error_d; 1.441 + bus_error_x <= bus_error_d; 1.442 `endif 1.443 - eret_x <= #1 eret_d; 1.444 + eret_x <= eret_d; 1.445 `ifdef CFG_DEBUG_ENABLED 1.446 - bret_x <= #1 bret_d; 1.447 + bret_x <= bret_d; 1.448 `endif 1.449 - write_enable_x <= #1 write_enable_d; 1.450 + write_enable_x <= write_enable_d; 1.451 end 1.452 1.453 // X/M stage registers 1.454 1.455 if (stall_m == `FALSE) 1.456 begin 1.457 - operand_m <= #1 x_result; 1.458 - m_result_sel_compare_m <= #1 m_result_sel_compare_x; 1.459 + operand_m <= x_result; 1.460 + m_result_sel_compare_m <= m_result_sel_compare_x; 1.461 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.462 - m_result_sel_shift_m <= #1 m_result_sel_shift_x; 1.463 + m_result_sel_shift_m <= m_result_sel_shift_x; 1.464 `endif 1.465 if (exception_x == `TRUE) 1.466 begin 1.467 - w_result_sel_load_m <= #1 `FALSE; 1.468 + w_result_sel_load_m <= `FALSE; 1.469 `ifdef CFG_PL_MULTIPLY_ENABLED 1.470 - w_result_sel_mul_m <= #1 `FALSE; 1.471 + w_result_sel_mul_m <= `FALSE; 1.472 `endif 1.473 end 1.474 else 1.475 begin 1.476 - w_result_sel_load_m <= #1 w_result_sel_load_x; 1.477 + w_result_sel_load_m <= w_result_sel_load_x; 1.478 `ifdef CFG_PL_MULTIPLY_ENABLED 1.479 - w_result_sel_mul_m <= #1 w_result_sel_mul_x; 1.480 + w_result_sel_mul_m <= w_result_sel_mul_x; 1.481 `endif 1.482 end 1.483 - m_bypass_enable_m <= #1 m_bypass_enable_x; 1.484 + m_bypass_enable_m <= m_bypass_enable_x; 1.485 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.486 `endif 1.487 - load_m <= #1 load_x; 1.488 - store_m <= #1 store_x; 1.489 + load_m <= load_x; 1.490 + store_m <= store_x; 1.491 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.492 - branch_m <= #1 branch_x && !branch_taken_x; 1.493 + branch_m <= branch_x && !branch_taken_x; 1.494 `else 1.495 - branch_m <= #1 branch_x; 1.496 - branch_predict_m <= #1 branch_predict_x; 1.497 - branch_predict_taken_m <= #1 branch_predict_taken_x; 1.498 + branch_m <= branch_x; 1.499 + branch_predict_m <= branch_predict_x; 1.500 + branch_predict_taken_m <= branch_predict_taken_x; 1.501 `endif 1.502 `ifdef CFG_DEBUG_ENABLED 1.503 // Data bus errors are generated by the wishbone and are 1.504 @@ -2511,18 +2511,18 @@ 1.505 // in same cycle (causing a debug exception). Handle non 1.506 // -debug exception first! 1.507 if (non_debug_exception_x == `TRUE) 1.508 - write_idx_m <= #1 `LM32_EA_REG; 1.509 + write_idx_m <= `LM32_EA_REG; 1.510 else if (debug_exception_x == `TRUE) 1.511 - write_idx_m <= #1 `LM32_BA_REG; 1.512 + write_idx_m <= `LM32_BA_REG; 1.513 else 1.514 - write_idx_m <= #1 write_idx_x; 1.515 + write_idx_m <= write_idx_x; 1.516 `else 1.517 if (exception_x == `TRUE) 1.518 - write_idx_m <= #1 `LM32_EA_REG; 1.519 + write_idx_m <= `LM32_EA_REG; 1.520 else 1.521 - write_idx_m <= #1 write_idx_x; 1.522 + write_idx_m <= write_idx_x; 1.523 `endif 1.524 - condition_met_m <= #1 condition_met_x; 1.525 + condition_met_m <= condition_met_x; 1.526 `ifdef CFG_DEBUG_ENABLED 1.527 if (exception_x == `TRUE) 1.528 if ((dc_re == `TRUE) 1.529 @@ -2531,28 +2531,28 @@ 1.530 `endif 1.531 || ((debug_exception_x == `TRUE) 1.532 && (non_debug_exception_x == `FALSE))) 1.533 - branch_target_m <= #1 {deba, eid_x, {3{1'b0}}}; 1.534 + branch_target_m <= {deba, eid_x, {3{1'b0}}}; 1.535 else 1.536 - branch_target_m <= #1 {eba, eid_x, {3{1'b0}}}; 1.537 + branch_target_m <= {eba, eid_x, {3{1'b0}}}; 1.538 else 1.539 - branch_target_m <= #1 branch_target_x; 1.540 + branch_target_m <= branch_target_x; 1.541 `else 1.542 - branch_target_m <= #1 exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 1.543 + branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 1.544 `endif 1.545 `ifdef CFG_TRACE_ENABLED 1.546 - eid_m <= #1 eid_x; 1.547 + eid_m <= eid_x; 1.548 `endif 1.549 `ifdef CFG_DCACHE_ENABLED 1.550 - dflush_m <= #1 dflush_x; 1.551 + dflush_m <= dflush_x; 1.552 `endif 1.553 - eret_m <= #1 eret_q_x; 1.554 + eret_m <= eret_q_x; 1.555 `ifdef CFG_DEBUG_ENABLED 1.556 - bret_m <= #1 bret_q_x; 1.557 + bret_m <= bret_q_x; 1.558 `endif 1.559 - write_enable_m <= #1 exception_x == `TRUE ? `TRUE : write_enable_x; 1.560 + write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x; 1.561 `ifdef CFG_DEBUG_ENABLED 1.562 - debug_exception_m <= #1 debug_exception_x; 1.563 - non_debug_exception_m <= #1 non_debug_exception_x; 1.564 + debug_exception_m <= debug_exception_x; 1.565 + non_debug_exception_m <= non_debug_exception_x; 1.566 `endif 1.567 end 1.568 1.569 @@ -2560,11 +2560,11 @@ 1.570 if (stall_m == `FALSE) 1.571 begin 1.572 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 1.573 - exception_m <= #1 `TRUE; 1.574 + exception_m <= `TRUE; 1.575 else 1.576 - exception_m <= #1 `FALSE; 1.577 + exception_m <= `FALSE; 1.578 `ifdef CFG_BUS_ERRORS_ENABLED 1.579 - data_bus_error_exception_m <= #1 (data_bus_error_exception == `TRUE) 1.580 + data_bus_error_exception_m <= (data_bus_error_exception == `TRUE) 1.581 `ifdef CFG_DEBUG_ENABLED 1.582 && (reset_exception == `FALSE) 1.583 `endif 1.584 @@ -2574,28 +2574,28 @@ 1.585 1.586 // M/W stage registers 1.587 `ifdef CFG_BUS_ERRORS_ENABLED 1.588 - operand_w <= #1 exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 1.589 + operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 1.590 `else 1.591 - operand_w <= #1 exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 1.592 + operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 1.593 `endif 1.594 - w_result_sel_load_w <= #1 w_result_sel_load_m; 1.595 + w_result_sel_load_w <= w_result_sel_load_m; 1.596 `ifdef CFG_PL_MULTIPLY_ENABLED 1.597 - w_result_sel_mul_w <= #1 w_result_sel_mul_m; 1.598 + w_result_sel_mul_w <= w_result_sel_mul_m; 1.599 `endif 1.600 - write_idx_w <= #1 write_idx_m; 1.601 + write_idx_w <= write_idx_m; 1.602 `ifdef CFG_TRACE_ENABLED 1.603 - eid_w <= #1 eid_m; 1.604 - eret_w <= #1 eret_m; 1.605 + eid_w <= eid_m; 1.606 + eret_w <= eret_m; 1.607 `ifdef CFG_DEBUG_ENABLED 1.608 - bret_w <= #1 bret_m; 1.609 + bret_w <= bret_m; 1.610 `endif 1.611 `endif 1.612 - write_enable_w <= #1 write_enable_m; 1.613 + write_enable_w <= write_enable_m; 1.614 `ifdef CFG_DEBUG_ENABLED 1.615 - debug_exception_w <= #1 debug_exception_m; 1.616 - non_debug_exception_w <= #1 non_debug_exception_m; 1.617 + debug_exception_w <= debug_exception_m; 1.618 + non_debug_exception_w <= non_debug_exception_m; 1.619 `else 1.620 - exception_w <= #1 exception_m; 1.621 + exception_w <= exception_m; 1.622 `endif 1.623 `ifdef CFG_BUS_ERRORS_ENABLED 1.624 if ( (stall_m == `FALSE) 1.625 @@ -2604,7 +2604,7 @@ 1.626 || (store_q_m == `TRUE) 1.627 ) 1.628 ) 1.629 - memop_pc_w <= #1 pc_m; 1.630 + memop_pc_w <= pc_m; 1.631 `endif 1.632 end 1.633 end 1.634 @@ -2616,26 +2616,26 @@ 1.635 begin 1.636 if (rst_i == `TRUE) 1.637 begin 1.638 - use_buf <= #1 `FALSE; 1.639 - reg_data_buf_0 <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.640 - reg_data_buf_1 <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.641 + use_buf <= `FALSE; 1.642 + reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}}; 1.643 + reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}}; 1.644 end 1.645 else 1.646 begin 1.647 if (stall_d == `FALSE) 1.648 - use_buf <= #1 `FALSE; 1.649 + use_buf <= `FALSE; 1.650 else if (use_buf == `FALSE) 1.651 begin 1.652 - reg_data_buf_0 <= #1 reg_data_live_0; 1.653 - reg_data_buf_1 <= #1 reg_data_live_1; 1.654 - use_buf <= #1 `TRUE; 1.655 + reg_data_buf_0 <= reg_data_live_0; 1.656 + reg_data_buf_1 <= reg_data_live_1; 1.657 + use_buf <= `TRUE; 1.658 end 1.659 if (reg_write_enable_q_w == `TRUE) 1.660 begin 1.661 if (write_idx_w == read_idx_0_d) 1.662 - reg_data_buf_0 <= #1 w_result; 1.663 + reg_data_buf_0 <= w_result; 1.664 if (write_idx_w == read_idx_1_d) 1.665 - reg_data_buf_1 <= #1 w_result; 1.666 + reg_data_buf_1 <= w_result; 1.667 end 1.668 end 1.669 end 1.670 @@ -2647,42 +2647,42 @@ 1.671 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.672 begin 1.673 if (rst_i == `TRUE) begin 1.674 - registers[0] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.675 - registers[1] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.676 - registers[2] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.677 - registers[3] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.678 - registers[4] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.679 - registers[5] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.680 - registers[6] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.681 - registers[7] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.682 - registers[8] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.683 - registers[9] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.684 - registers[10] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.685 - registers[11] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.686 - registers[12] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.687 - registers[13] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.688 - registers[14] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.689 - registers[15] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.690 - registers[16] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.691 - registers[17] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.692 - registers[18] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.693 - registers[19] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.694 - registers[20] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.695 - registers[21] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.696 - registers[22] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.697 - registers[23] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.698 - registers[24] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.699 - registers[25] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.700 - registers[26] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.701 - registers[27] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.702 - registers[28] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.703 - registers[29] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.704 - registers[30] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.705 - registers[31] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.706 + registers[0] <= {`LM32_WORD_WIDTH{1'b0}}; 1.707 + registers[1] <= {`LM32_WORD_WIDTH{1'b0}}; 1.708 + registers[2] <= {`LM32_WORD_WIDTH{1'b0}}; 1.709 + registers[3] <= {`LM32_WORD_WIDTH{1'b0}}; 1.710 + registers[4] <= {`LM32_WORD_WIDTH{1'b0}}; 1.711 + registers[5] <= {`LM32_WORD_WIDTH{1'b0}}; 1.712 + registers[6] <= {`LM32_WORD_WIDTH{1'b0}}; 1.713 + registers[7] <= {`LM32_WORD_WIDTH{1'b0}}; 1.714 + registers[8] <= {`LM32_WORD_WIDTH{1'b0}}; 1.715 + registers[9] <= {`LM32_WORD_WIDTH{1'b0}}; 1.716 + registers[10] <= {`LM32_WORD_WIDTH{1'b0}}; 1.717 + registers[11] <= {`LM32_WORD_WIDTH{1'b0}}; 1.718 + registers[12] <= {`LM32_WORD_WIDTH{1'b0}}; 1.719 + registers[13] <= {`LM32_WORD_WIDTH{1'b0}}; 1.720 + registers[14] <= {`LM32_WORD_WIDTH{1'b0}}; 1.721 + registers[15] <= {`LM32_WORD_WIDTH{1'b0}}; 1.722 + registers[16] <= {`LM32_WORD_WIDTH{1'b0}}; 1.723 + registers[17] <= {`LM32_WORD_WIDTH{1'b0}}; 1.724 + registers[18] <= {`LM32_WORD_WIDTH{1'b0}}; 1.725 + registers[19] <= {`LM32_WORD_WIDTH{1'b0}}; 1.726 + registers[20] <= {`LM32_WORD_WIDTH{1'b0}}; 1.727 + registers[21] <= {`LM32_WORD_WIDTH{1'b0}}; 1.728 + registers[22] <= {`LM32_WORD_WIDTH{1'b0}}; 1.729 + registers[23] <= {`LM32_WORD_WIDTH{1'b0}}; 1.730 + registers[24] <= {`LM32_WORD_WIDTH{1'b0}}; 1.731 + registers[25] <= {`LM32_WORD_WIDTH{1'b0}}; 1.732 + registers[26] <= {`LM32_WORD_WIDTH{1'b0}}; 1.733 + registers[27] <= {`LM32_WORD_WIDTH{1'b0}}; 1.734 + registers[28] <= {`LM32_WORD_WIDTH{1'b0}}; 1.735 + registers[29] <= {`LM32_WORD_WIDTH{1'b0}}; 1.736 + registers[30] <= {`LM32_WORD_WIDTH{1'b0}}; 1.737 + registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 1.738 end 1.739 else begin 1.740 if (reg_write_enable_q_w == `TRUE) 1.741 - registers[write_idx_w] <= #1 w_result; 1.742 + registers[write_idx_w] <= w_result; 1.743 end 1.744 end 1.745 `endif 1.746 @@ -2693,19 +2693,19 @@ 1.747 begin 1.748 if (rst_i == `TRUE) 1.749 begin 1.750 - trace_pc_valid <= #1 `FALSE; 1.751 - trace_pc <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.752 - trace_exception <= #1 `FALSE; 1.753 - trace_eid <= #1 `LM32_EID_RESET; 1.754 - trace_eret <= #1 `FALSE; 1.755 + trace_pc_valid <= `FALSE; 1.756 + trace_pc <= {`LM32_PC_WIDTH{1'b0}}; 1.757 + trace_exception <= `FALSE; 1.758 + trace_eid <= `LM32_EID_RESET; 1.759 + trace_eret <= `FALSE; 1.760 `ifdef CFG_DEBUG_ENABLED 1.761 - trace_bret <= #1 `FALSE; 1.762 + trace_bret <= `FALSE; 1.763 `endif 1.764 - pc_c <= #1 `CFG_EBA_RESET/4; 1.765 + pc_c <= `CFG_EBA_RESET/4; 1.766 end 1.767 else 1.768 begin 1.769 - trace_pc_valid <= #1 `FALSE; 1.770 + trace_pc_valid <= `FALSE; 1.771 // Has an exception occured 1.772 `ifdef CFG_DEBUG_ENABLED 1.773 if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE)) 1.774 @@ -2713,13 +2713,13 @@ 1.775 if (exception_q_w == `TRUE) 1.776 `endif 1.777 begin 1.778 - trace_exception <= #1 `TRUE; 1.779 - trace_pc_valid <= #1 `TRUE; 1.780 - trace_pc <= #1 pc_w; 1.781 - trace_eid <= #1 eid_w; 1.782 + trace_exception <= `TRUE; 1.783 + trace_pc_valid <= `TRUE; 1.784 + trace_pc <= pc_w; 1.785 + trace_eid <= eid_w; 1.786 end 1.787 else 1.788 - trace_exception <= #1 `FALSE; 1.789 + trace_exception <= `FALSE; 1.790 1.791 if ((valid_w == `TRUE) && (!kill_w)) 1.792 begin 1.793 @@ -2727,22 +2727,22 @@ 1.794 if (pc_c + 1'b1 != pc_w) 1.795 begin 1.796 // Non-sequential instruction 1.797 - trace_pc_valid <= #1 `TRUE; 1.798 - trace_pc <= #1 pc_w; 1.799 + trace_pc_valid <= `TRUE; 1.800 + trace_pc <= pc_w; 1.801 end 1.802 // Record PC so we can determine if next instruction is sequential or not 1.803 - pc_c <= #1 pc_w; 1.804 + pc_c <= pc_w; 1.805 // Indicate if it was an eret/bret instruction 1.806 - trace_eret <= #1 eret_w; 1.807 + trace_eret <= eret_w; 1.808 `ifdef CFG_DEBUG_ENABLED 1.809 - trace_bret <= #1 bret_w; 1.810 + trace_bret <= bret_w; 1.811 `endif 1.812 end 1.813 else 1.814 begin 1.815 - trace_eret <= #1 `FALSE; 1.816 + trace_eret <= `FALSE; 1.817 `ifdef CFG_DEBUG_ENABLED 1.818 - trace_bret <= #1 `FALSE; 1.819 + trace_bret <= `FALSE; 1.820 `endif 1.821 end 1.822 end