1.1 diff -r 73de224304c1 -r d6c693415d59 lm32_icache.v 1.2 --- a/lm32_icache.v Sat Aug 06 00:02:46 2011 +0100 1.3 +++ b/lm32_icache.v Sat Aug 06 01:26:56 2011 +0100 1.4 @@ -380,11 +380,11 @@ 1.5 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.6 begin 1.7 if (rst_i == `TRUE) 1.8 - refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1}; 1.9 + refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 1.10 else 1.11 begin 1.12 if (miss == `TRUE) 1.13 - refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]}; 1.14 + refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 1.15 end 1.16 end 1.17 end 1.18 @@ -394,9 +394,9 @@ 1.19 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.20 begin 1.21 if (rst_i == `TRUE) 1.22 - refilling <= #1 `FALSE; 1.23 + refilling <= `FALSE; 1.24 else 1.25 - refilling <= #1 refill; 1.26 + refilling <= refill; 1.27 end 1.28 1.29 // Instruction cache control FSM 1.30 @@ -404,10 +404,10 @@ 1.31 begin 1.32 if (rst_i == `TRUE) 1.33 begin 1.34 - state <= #1 `LM32_IC_STATE_FLUSH_INIT; 1.35 - flush_set <= #1 {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 1.36 - refill_address <= #1 {`LM32_PC_WIDTH{1'bx}}; 1.37 - restart_request <= #1 `FALSE; 1.38 + state <= `LM32_IC_STATE_FLUSH_INIT; 1.39 + flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 1.40 + refill_address <= {`LM32_PC_WIDTH{1'bx}}; 1.41 + restart_request <= `FALSE; 1.42 end 1.43 else 1.44 begin 1.45 @@ -417,8 +417,8 @@ 1.46 `LM32_IC_STATE_FLUSH_INIT: 1.47 begin 1.48 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 1.49 - state <= #1 `LM32_IC_STATE_CHECK; 1.50 - flush_set <= #1 flush_set - 1'b1; 1.51 + state <= `LM32_IC_STATE_CHECK; 1.52 + flush_set <= flush_set - 1'b1; 1.53 end 1.54 1.55 // Flush the cache in response to an write to the ICC CSR 1.56 @@ -427,28 +427,28 @@ 1.57 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 1.58 `ifdef CFG_IROM_ENABLED 1.59 if (select_f) 1.60 - state <= #1 `LM32_IC_STATE_REFILL; 1.61 + state <= `LM32_IC_STATE_REFILL; 1.62 else 1.63 `endif 1.64 - state <= #1 `LM32_IC_STATE_CHECK; 1.65 + state <= `LM32_IC_STATE_CHECK; 1.66 1.67 - flush_set <= #1 flush_set - 1'b1; 1.68 + flush_set <= flush_set - 1'b1; 1.69 end 1.70 1.71 // Check for cache misses 1.72 `LM32_IC_STATE_CHECK: 1.73 begin 1.74 if (stall_a == `FALSE) 1.75 - restart_request <= #1 `FALSE; 1.76 + restart_request <= `FALSE; 1.77 if (iflush == `TRUE) 1.78 begin 1.79 - refill_address <= #1 address_f; 1.80 - state <= #1 `LM32_IC_STATE_FLUSH; 1.81 + refill_address <= address_f; 1.82 + state <= `LM32_IC_STATE_FLUSH; 1.83 end 1.84 else if (miss == `TRUE) 1.85 begin 1.86 - refill_address <= #1 address_f; 1.87 - state <= #1 `LM32_IC_STATE_REFILL; 1.88 + refill_address <= address_f; 1.89 + state <= `LM32_IC_STATE_REFILL; 1.90 end 1.91 end 1.92 1.93 @@ -459,8 +459,8 @@ 1.94 begin 1.95 if (last_refill == `TRUE) 1.96 begin 1.97 - restart_request <= #1 `TRUE; 1.98 - state <= #1 `LM32_IC_STATE_CHECK; 1.99 + restart_request <= `TRUE; 1.100 + state <= `LM32_IC_STATE_CHECK; 1.101 end 1.102 end 1.103 end 1.104 @@ -476,7 +476,7 @@ 1.105 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.106 begin 1.107 if (rst_i == `TRUE) 1.108 - refill_offset <= #1 {addr_offset_width{1'b0}}; 1.109 + refill_offset <= {addr_offset_width{1'b0}}; 1.110 else 1.111 begin 1.112 case (state) 1.113 @@ -485,16 +485,16 @@ 1.114 `LM32_IC_STATE_CHECK: 1.115 begin 1.116 if (iflush == `TRUE) 1.117 - refill_offset <= #1 {addr_offset_width{1'b0}}; 1.118 + refill_offset <= {addr_offset_width{1'b0}}; 1.119 else if (miss == `TRUE) 1.120 - refill_offset <= #1 {addr_offset_width{1'b0}}; 1.121 + refill_offset <= {addr_offset_width{1'b0}}; 1.122 end 1.123 1.124 // Refill a cache line 1.125 `LM32_IC_STATE_REFILL: 1.126 begin 1.127 if (refill_ready == `TRUE) 1.128 - refill_offset <= #1 refill_offset + 1'b1; 1.129 + refill_offset <= refill_offset + 1'b1; 1.130 end 1.131 1.132 endcase