IPCores/lm32_cpu / file diff

     1.1 diff -r 73de224304c1 -r d6c693415d59 lm32_monitor.v
     1.2 --- a/lm32_monitor.v	Sat Aug 06 00:02:46 2011 +0100
     1.3 +++ b/lm32_monitor.v	Sat Aug 06 01:26:56 2011 +0100
     1.4 @@ -144,10 +144,10 @@
     1.5  begin
     1.6      if (rst_i == `TRUE)
     1.7      begin
     1.8 -        write_enable <= #1 `FALSE;
     1.9 -        MON_ACK_O <= #1 `FALSE;
    1.10 -        MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}};
    1.11 -        state <= #1 2'b00;
    1.12 +        write_enable <= `FALSE;
    1.13 +        MON_ACK_O <= `FALSE;
    1.14 +        MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
    1.15 +        state <= 2'b00;
    1.16      end
    1.17      else
    1.18      begin
    1.19 @@ -155,33 +155,33 @@
    1.20          2'b01:
    1.21          begin
    1.22              // Output read data to Wishbone
    1.23 -            MON_ACK_O <= #1 `TRUE;
    1.24 -            MON_DAT_O <= #1 data;
    1.25 +            MON_ACK_O <= `TRUE;
    1.26 +            MON_DAT_O <= data;
    1.27              // Sub-word writes are performed using read-modify-write  
    1.28              // as the Lattice EBRs don't support byte enables
    1.29              if (MON_WE_I == `TRUE)
    1.30 -                write_enable <= #1 `TRUE;
    1.31 -            write_data[7:0] <= #1 MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
    1.32 -            write_data[15:8] <= #1 MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
    1.33 -            write_data[23:16] <= #1 MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
    1.34 -            write_data[31:24] <= #1 MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
    1.35 -            state <= #1 2'b10;
    1.36 +                write_enable <= `TRUE;
    1.37 +            write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
    1.38 +            write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
    1.39 +            write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
    1.40 +            write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
    1.41 +            state <= 2'b10;
    1.42          end
    1.43          2'b10:
    1.44          begin
    1.45              // Wishbone access occurs in this cycle
    1.46 -            write_enable <= #1 `FALSE;
    1.47 -            MON_ACK_O <= #1 `FALSE;
    1.48 -            MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}};
    1.49 -            state <= #1 2'b00;
    1.50 +            write_enable <= `FALSE;
    1.51 +            MON_ACK_O <= `FALSE;
    1.52 +            MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
    1.53 +            state <= 2'b00;
    1.54          end
    1.55          default:
    1.56          begin
    1.57 -           write_enable <= #1 `FALSE;
    1.58 -           MON_ACK_O <= #1 `FALSE;
    1.59 +           write_enable <= `FALSE;
    1.60 +           MON_ACK_O <= `FALSE;
    1.61              // Wait for a Wishbone access
    1.62              if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
    1.63 -                state <= #1 2'b01;
    1.64 +                state <= 2'b01;
    1.65          end
    1.66          endcase        
    1.67      end