Fri, 13 Aug 2010 01:15:02 +0100
[MERGE] Merge in changes from Lattice LM32 v3.5
| lm32_addsub.v | file | annotate | diff | revisions | |
| lm32_dcache.v | file | annotate | diff | revisions | |
| lm32_icache.v | file | annotate | diff | revisions | |
| lm32_include.v | file | annotate | diff | revisions | |
| lm32_ram.v | file | annotate | diff | revisions |
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2.1 diff -r 0a26167af7e1 -r 0eb235b23d55 document/ds_icon.jpg 2.2 Binary file document/ds_icon.jpg has changed
3.1 diff -r 0a26167af7e1 -r 0eb235b23d55 document/ds_icon_ast.jpg 3.2 Binary file document/ds_icon_ast.jpg has changed
4.1 diff -r 0a26167af7e1 -r 0eb235b23d55 document/dsb_icon.jpg 4.2 Binary file document/dsb_icon.jpg has changed
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padding-left:10px; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-bottom-width:1px; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; } 7.56 +img_whs32 { border:none; width:14px; height:16px; float:none; border-style:none; } 7.57 +--> 7.58 +</style><script type="text/javascript" language="JavaScript"> 7.59 +<!-- 7.60 +function ehlp_showtip(current,e,text) 7.61 +{ 7.62 + if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) 7.63 + { 7.64 + document.tooltip.document.write("<layer bgColor='yellow' style='border:1px solid black;font-size:12px;'>"+ text + "</layer>"); 7.65 + document.tooltip.document.close(); 7.66 + document.tooltip.left=e.pageX+5; 7.67 + document.tooltip.top=e.pageY+5; 7.68 + document.tooltip.visibility="show"; 7.69 + } 7.70 +} 7.71 +function ehlp_hidetip() 7.72 +{ 7.73 + document.tooltip.visibility="hidden"; 7.74 +} 7.75 +//--> 7.76 +</script> 7.77 +<script type="text/javascript" language="JavaScript" title="WebHelpInlineScript"> 7.78 +<!-- 7.79 +function reDo() { 7.80 + if (innerWidth != origWidth || innerHeight != origHeight) 7.81 + location.reload(); 7.82 +} 7.83 +if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) { 7.84 + origWidth = innerWidth; 7.85 + origHeight = innerHeight; 7.86 + onresize = reDo; 7.87 +} 7.88 +onerror = null; 7.89 +//--> 7.90 +</script> 7.91 +<style type="text/css"> 7.92 +<!-- 7.93 +div.WebHelpPopupMenu { position:absolute; left:0px; top:0px; z-index:4; visibility:hidden; } 7.94 +p.WebHelpNavBar { text-align:right; } 7.95 +--> 7.96 +</style><script type="text/javascript" language="javascript1.2" src="whmsg.js"></script> 7.97 +<script type="text/javascript" language="javascript" src="whver.js"></script> 7.98 +<script type="text/javascript" language="javascript1.2" src="whproxy.js"></script> 7.99 +<script type="text/javascript" language="javascript1.2" src="whutils.js"></script> 7.100 +<script type="text/javascript" language="javascript1.2" src="whtopic.js"></script> 7.101 +<script type="text/javascript" language="javascript1.2"> 7.102 +<!-- 7.103 +if (window.gbWhTopic) 7.104 +{ 7.105 + if (window.setRelStartPage) 7.106 + { 7.107 + addTocInfo("LM32"); 7.108 + 7.109 + } 7.110 + 7.111 + 7.112 + if (window.setRelStartPage) 7.113 + { 7.114 + setRelStartPage("MSB_Peripherals.htm"); 7.115 + 7.116 + autoSync(0); 7.117 + sendSyncInfo(); 7.118 + sendAveInfoOut(); 7.119 + } 7.120 + 7.121 +} 7.122 +else 7.123 + if (window.gbIE4) 7.124 + document.location.reload(); 7.125 +//--> 7.126 +</script> 7.127 +</head> 7.128 +<body><script type="text/javascript" language="javascript1.2"> 7.129 +<!-- 7.130 +if (window.writeIntopicBar) 7.131 + writeIntopicBar(4); 7.132 +//--> 7.133 +</script> 7.134 +<h1>LatticeMico32 Processor <a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1> 7.135 + 7.136 +<p>The LatticeMico32 processor is a high-performance 32-bit microprocessor 7.137 + optimized for Lattice Semiconductor field-programmable gate arrays. </p> 7.138 + 7.139 +<p class="whs2"><span style="font-style: italic;"><I>*If the 7.140 + processor manual fails to open, see the note at the bottom of this page.</I></span></p> 7.141 + 7.142 +<h2>Revision History</h2> 7.143 + 7.144 +<table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3"> 7.145 +<script language='JavaScript'><!-- 7.146 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' width='738' height='84' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>"); 7.147 +//--></script> 7.148 +<col class="whs4"> 7.149 +<col class="whs5"> 7.150 + 7.151 +<tr valign="top" class="whs6"> 7.152 +<td bgcolor="#DEE8F4" width="93px" class="whs7"> 7.153 +<p class=Table 7.154 + style="font-weight: bold;">Version</td> 7.155 +<td bgcolor="#DEE8F4" width="598px" class="whs8"> 7.156 +<p class=Table 7.157 + style="font-weight: bold;">Description</td></tr> 7.158 + 7.159 +<tr valign="top" class="whs6"> 7.160 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 7.161 +<p class=Table 7.162 + style="font-weight: normal;">3.5</td> 7.163 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 7.164 +<p class=whs10 7.165 + style="margin-left: 0px;">Support added to allow Inline Memories to 7.166 + be generated as non-power-of-two, as long as they are a multiple of 1024 7.167 + bytes</td></tr> 7.168 + 7.169 +<tr valign="top" class="whs6"> 7.170 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 7.171 +<p class=Table 7.172 + style="font-weight: normal;">3.3</td> 7.173 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 7.174 +<p class=whs10 7.175 + style="margin-left: 0px;">Added Inline Memory to support on-chip memory 7.176 + connected through a local bus.</td></tr> 7.177 + 7.178 +<tr valign="top" class="whs6"> 7.179 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 7.180 +<p class=Table 7.181 + style="font-weight: normal;">3.2</td> 7.182 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 7.183 +<p class=whs10 7.184 + style="margin-left: 0px;">Added Memory Type to instruction cache and 7.185 + data cache.</td></tr> 7.186 + 7.187 +<tr valign="top" class="whs6"> 7.188 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 7.189 +<p class=Table 7.190 + style="font-weight: normal;">3.1</td> 7.191 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 7.192 +<p class="whs11">Added static predictor to improve the behavior 7.193 + of branches.</p> 7.194 +<p class="whs11">Added support for optionally mapping the register 7.195 + file to EBRs (on-chip memory).</p> 7.196 +<p class="whs11">Added support for selecting between distributed 7.197 + RAM and EBRs (pseudo-dual port or true-dual port) for instruction and 7.198 + data caches.</td></tr> 7.199 + 7.200 +<tr valign="top" class="whs6"> 7.201 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 7.202 +<p class=Table 7.203 + style="font-weight: normal;"><span style="font-weight: normal;">3.0 7.204 + </span></td> 7.205 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 7.206 +<p class="whs11">Fixed incorrect handling of data cache miss 7.207 + in the presence of an instruction cache miss.</td></tr> 7.208 + 7.209 +<tr valign="top" class="whs6"> 7.210 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 7.211 +<p class="whs11">1.0</td> 7.212 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 7.213 +<p class="whs11">Initial version.</td></tr> 7.214 +<script language='JavaScript'><!-- 7.215 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>"); 7.216 +//--></script> 7.217 +</table> 7.218 + 7.219 + 7.220 + 7.221 +<h2>Dialog Box Parameters – 7.222 + General Tab</h2> 7.223 + 7.224 +<table x-use-null-cells cellspacing="0" class="whs12"> 7.225 +<col class="whs13"> 7.226 +<col class="whs14"> 7.227 + 7.228 +<tr valign="top" class="whs15"> 7.229 +<td bgcolor="#DEE8F4" width="167px" class="whs16"> 7.230 +<p class=Table 7.231 + style="font-weight: bold;">Parameter</td> 7.232 +<td bgcolor="#DEE8F4" width="524px" class="whs17"> 7.233 +<p class=Table 7.234 + style="font-weight: bold;">Description</td></tr> 7.235 + 7.236 +<tr valign="top" class="whs15"> 7.237 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.238 +<p class=Table 7.239 + style="font-weight: normal;">Instance Name</td> 7.240 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 7.241 +<p class=Table 7.242 + style="margin-left: 14px;">Specifies the name of the LatticeMico32 7.243 + processor. Alphanumeric values and underscores are supported. The default 7.244 + is LM32.</td></tr> 7.245 + 7.246 +<tr valign="top" class="whs15"> 7.247 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 7.248 +<p class=Table 7.249 + style="font-weight: bold;">Settings</td> 7.250 +</tr> 7.251 + 7.252 +<tr valign="top" class="whs15"> 7.253 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.254 +<p class=Table>Use EBRs for Register File</td> 7.255 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.256 +<p class=Table>Uses embedded block RAMS for the register file.</td></tr> 7.257 + 7.258 +<tr valign="top" class="whs15"> 7.259 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.260 +<p class=Table>Enable Divide</td> 7.261 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.262 +<p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, 7.263 + modu</span>).</td></tr> 7.264 + 7.265 +<tr valign="top" class="whs15"> 7.266 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.267 +<p class=Table>Enable Sign Extend</td> 7.268 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.269 +<p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, 7.270 + sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr> 7.271 + 7.272 +<tr valign="top" class="whs15"> 7.273 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.274 +<p class=Table>Location of Exception Handlers</td> 7.275 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.276 +<p class=Table>Specifies the default value for the vector table. This can 7.277 + be changed by updating the EBA control register or status register.</p> 7.278 +<p class=Table>This address must be aligned to a 256-byte boundary, since 7.279 + the hardware ignores the least-significant byte. Unpredictable behavior 7.280 + occurs when the exception base address and the exception vectors are not 7.281 + aligned on a 256-byte boundary.</td></tr> 7.282 + 7.283 +<tr valign="top" class="whs15"> 7.284 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 7.285 +<p class=Table 7.286 + style="font-weight: bold;">Multiplier Settings</td> 7.287 +</tr> 7.288 + 7.289 +<tr valign="top" class="whs15"> 7.290 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.291 +<p class=Table>Enable Multiplier</td> 7.292 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.293 +<p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, 7.294 + muli)</span>.</td></tr> 7.295 + 7.296 +<tr valign="top" class="whs15"> 7.297 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.298 +<p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td> 7.299 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.300 +<p class=Table>Enables the multiplier using the DSP block, if available.</td></tr> 7.301 + 7.302 +<tr valign="top" class="whs15"> 7.303 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.304 +<p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td> 7.305 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.306 +<p class=Table>Enables the multiplier using LUTs.</td></tr> 7.307 + 7.308 +<tr valign="top" class="whs15"> 7.309 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 7.310 +<p class=Table 7.311 + style="font-weight: bold;">Instruction Cache</td> 7.312 +</tr> 7.313 + 7.314 +<tr valign="top" class="whs15"> 7.315 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.316 +<p class=Table>Instruction Cache Enabled</td> 7.317 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 7.318 +<p class=Table 7.319 + style="margin-left: 14px;">Determines whether an instruction cache 7.320 + is implemented.</td></tr> 7.321 + 7.322 +<tr valign="top" class="whs15"> 7.323 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.324 +<p class=Table>Number of Sets</td> 7.325 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 7.326 +<p class=Table 7.327 + style="margin-left: 14px;">Specifies the number of sets in the instruction 7.328 + cache. Supported values are 128, 256, 512, 1024.</td></tr> 7.329 + 7.330 +<tr valign="top" class="whs15"> 7.331 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.332 +<p class=Table>Set Associativity</td> 7.333 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 7.334 +<p class=Table 7.335 + style="margin-left: 14px;">Specifies the associativity of the instruction 7.336 + cache. Supported values are 1, 2.</td></tr> 7.337 + 7.338 +<tr valign="top" class="whs15"> 7.339 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.340 +<p class=Table>Bytes/Cache Line</td> 7.341 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 7.342 +<p class=Table 7.343 + style="margin-left: 15px;">Specifies the number of bytes per instruction 7.344 + cache line. Supported values are 4, 8, 16.</td></tr> 7.345 + 7.346 +<tr valign="top" class="whs15"> 7.347 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.348 +<p class=Table>Memory Type</td> 7.349 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 7.350 +<p class=Table 7.351 + style="margin-left: 15px;">Determines the FPGA resource to be used 7.352 + to implement the instruction cache. The decision can be left to the synthesis 7.353 + tool (Auto), or you can select from the following options:</p> 7.354 +<ul type="disc" class="whs22"> 7.355 + 7.356 + <li class=kadov-p-CBullet><p class=Bullet>Auto – 7.357 + Leaves the implementation of the instruction cache to the synthesis tool.</p></li> 7.358 + 7.359 + <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM – 7.360 + Implements the instruction cache as distributed RAM.</p></li> 7.361 + 7.362 + <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR – 7.363 + Implements the instruction cache as dual-port EBR (two read/write ports).</p></li> 7.364 + 7.365 + <li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR – Implements 7.366 + the instruction cache as pseudo-dual-port EBR (one read port and one write 7.367 + port). </p></li> 7.368 +</ul></td></tr> 7.369 + 7.370 +<tr valign="top" class="whs15"> 7.371 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 7.372 +<p class=Table 7.373 + style="font-weight: bold;">Debug Setting</td> 7.374 +</tr> 7.375 + 7.376 +<tr valign="top" class="whs15"> 7.377 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.378 +<p class=Table>Enable Debug Interface</td> 7.379 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.380 +<p class=Table>Includes the debugger stub in the CPU, which is required 7.381 + for debugging.</td></tr> 7.382 + 7.383 +<tr valign="top" class="whs15"> 7.384 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.385 +<p class=Table># of H/W Watchpoint Registers</td> 7.386 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.387 +<p class=Table 7.388 + style="font-weight: normal;">Specifies the number of hardware watchpoint 7.389 + registers to be used in the debugging process.</td></tr> 7.390 + 7.391 +<tr valign="top" class="whs15"> 7.392 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.393 +<p class=Table>Enable Debugging Code in Flash or ROM</td> 7.394 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.395 +<p class=Table 7.396 + style="font-weight: normal;">Enables you to set hardware breakpoints 7.397 + in read-only memory.</td></tr> 7.398 + 7.399 +<tr valign="top" class="whs15"> 7.400 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.401 +<p class=Table># of H/W Breakpoint Registers</td> 7.402 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.403 +<p class=Table>Specifies the number of hardware breakpoint registers to 7.404 + be used in the debugging process.</td></tr> 7.405 + 7.406 +<tr valign="top" class="whs15"> 7.407 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.408 +<p class=Table>Enable PC Trace</td> 7.409 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.410 +<p class=Table>Enables the Program Counter Trace feature, which enables 7.411 + you to run the program trace during debug to find items in your C or C++ 7.412 + Code during debug, such as breakpoints and exceptions. Refer to <span 7.413 + style="font-weight: bold;"><B>Help > Help Contents > Lattice Software 7.414 + Project Environment > Concepts > Program Counter Trace</B></span> for 7.415 + more information on Program Counter Trace.</td></tr> 7.416 + 7.417 +<tr valign="top" class="whs15"> 7.418 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.419 +<p class=Table>Trace Depth</td> 7.420 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.421 +<p class=Table>Enables you to specify the depth of the Program Counter 7.422 + Trace buffer. Refer to <span style="font-weight: bold;"><B>Help > Help 7.423 + Contents > Lattice Software Project Environment > 7.424 + Concepts > Program Counter Trace</B></span> for more information on Program 7.425 + Counter Trace.</td></tr> 7.426 + 7.427 +<tr valign="top" class="whs15"> 7.428 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 7.429 +<p class=Table 7.430 + style="font-weight: bold;">Shifter Settings</td> 7.431 +</tr> 7.432 + 7.433 +<tr valign="top" class="whs15"> 7.434 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.435 +<p class=Table>Enable Shifter</td> 7.436 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 7.437 +<p>Enables the multi-bit shift instructions (sr, sri, sru, srui, sl, sli). 7.438 + </td></tr> 7.439 + 7.440 +<tr valign="top" class="whs15"> 7.441 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.442 +<p class=Table>Enable Piplined Barrel Shifter</td> 7.443 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 7.444 +<p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 7.445 + to perform a shift operation in three cycles.</td></tr> 7.446 + 7.447 +<tr valign="top" class="whs15"> 7.448 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.449 +<p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td> 7.450 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 7.451 +<p>Enables multi-cycle shift operation for the barrel shifter. The barrel 7.452 + shifter is implemented to shift one bit per cycle and take thirty-two 7.453 + cycles to complete.</td></tr> 7.454 + 7.455 +<tr valign="top" class="whs15"> 7.456 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 7.457 +<p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td> 7.458 +</tr> 7.459 + 7.460 +<tr valign="top" class="whs15"> 7.461 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.462 +<p class=Table>Data Cache Enabled</td> 7.463 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.464 +<p class=Table>Determines whether a data cache is implemented.</td></tr> 7.465 + 7.466 +<tr valign="top" class="whs15"> 7.467 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.468 +<p class=Table>Number of Sets</td> 7.469 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.470 +<p class=Table>Specifies the number of sets in the data cache. Supported 7.471 + values are 128, 256, 512, 1024.</td></tr> 7.472 + 7.473 +<tr valign="top" class="whs15"> 7.474 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.475 +<p class=Table>Set Associativity</td> 7.476 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.477 +<p class=Table>Specifies the associativity of the data cache. Supported 7.478 + values are 1, 2.</td></tr> 7.479 + 7.480 +<tr valign="top" class="whs15"> 7.481 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 7.482 +<p class=Table>Bytes/Cache Line</td> 7.483 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 7.484 +<p class=Table>Specifies the number of bytes per data cache line. Supported 7.485 + values are 4, 8, 16.</td></tr> 7.486 + 7.487 +<tr valign="top" class="whs15"> 7.488 +<td colspan="1" rowspan="1" width="167px" class="whs23"> 7.489 +<p class=Table>Memory Type</td> 7.490 +<td colspan="1" rowspan="1" width="524px" class="whs24"> 7.491 +<p class=Table>Determines the FPGA resource to be used to implement the 7.492 + data cache. The decision can be left to the synthesis tool (Auto), or 7.493 + you can select from the following options:</p> 7.494 +<ul> 7.495 + 7.496 + <li class=kadov-p-CBullet><p class=Bullet>Auto – 7.497 + Leaves the implementation of the data cache to the synthesis tool.</p></li> 7.498 + 7.499 + <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM – 7.500 + Implements the data cache as distributed RAM.</p></li> 7.501 + 7.502 + <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR – 7.503 + Implements the data cache as dual-port EBR (two read/write ports).</p></li> 7.504 +</ul></td></tr> 7.505 +</table> 7.506 + 7.507 +<p> </p> 7.508 + 7.509 +<h2>Dialog Box Parameters – 7.510 + Inline Memory Tab</h2> 7.511 + 7.512 +<table x-use-null-cells cellspacing="0" class="whs12"> 7.513 +<col class="whs13"> 7.514 +<col class="whs14"> 7.515 + 7.516 +<tr valign="top" class="whs15"> 7.517 +<td bgcolor="#DEE8F4" width="167px" class="whs25"> 7.518 +<p class=Table 7.519 + style="font-weight: bold;">Parameter</td> 7.520 +<td bgcolor="#DEE8F4" width="524px" class="whs26"> 7.521 +<p class=Table 7.522 + style="font-weight: bold;">Description</td></tr> 7.523 + 7.524 +<tr valign="top" class="whs15"> 7.525 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 7.526 +<p class=Table 7.527 + style="font-weight: bold;">Instruction Inline Memory</td> 7.528 +</tr> 7.529 + 7.530 +<tr valign="top" class="whs15"> 7.531 +<td width="167px" class="whs28"> 7.532 +<p class=Table>Enable</td> 7.533 +<td width="524px" class="whs29"> 7.534 +<p class=Table>Enables the instruction inline memory</td></tr> 7.535 + 7.536 +<tr valign="top" class="whs15"> 7.537 +<td width="167px" class="whs28"> 7.538 +<p class=Table>Instance Name</td> 7.539 +<td width="524px" class="whs29"> 7.540 +<p class=Table>Specifics the name of the instruction inline memory. Alphanumeric 7.541 + values and underscores are supported. The default is Instruction_IM.</td></tr> 7.542 + 7.543 +<tr valign="top" class="whs15"> 7.544 +<td width="167px" class="whs28"> 7.545 +<p class=Table>Base Address</td> 7.546 +<td width="524px" class="whs29"> 7.547 +<p class=Table>Specifies the base address for the instruction inline memory. 7.548 + The default is 0x10000000.</td></tr> 7.549 + 7.550 +<tr valign="top" class="whs15"> 7.551 +<td width="167px" class="whs28"> 7.552 +<p class=Table>Size of Memory in Bytes</td> 7.553 +<td width="524px" class="whs29"> 7.554 +<p class=Table>Specifies the size of the instruction inline memory.</td></tr> 7.555 + 7.556 +<tr valign="top" class="whs15"> 7.557 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 7.558 +<p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td> 7.559 +</tr> 7.560 + 7.561 +<tr valign="top" class="whs15"> 7.562 +<td width="167px" class="whs28"> 7.563 +<p class=Table>Initialization File Name</td> 7.564 +<td width="524px" class="whs29"> 7.565 +<p class=Table>Specifies the name of the memory initialization file for 7.566 + instruction inline memory.</td></tr> 7.567 + 7.568 +<tr valign="top" class="whs15"> 7.569 +<td width="167px" class="whs28"> 7.570 +<p class=Table>File Format</td> 7.571 +<td width="524px" class="whs29"> 7.572 +<p class=Table>Specifies the format of the memory initialization file: 7.573 + hex or binary.</td></tr> 7.574 + 7.575 +<tr valign="top" class="whs15"> 7.576 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 7.577 +<p class=Table 7.578 + style="font-weight: bold;">Data Inline Memory</td> 7.579 +</tr> 7.580 + 7.581 +<tr valign="top" class="whs15"> 7.582 +<td width="167px" class="whs28"> 7.583 +<p class=Table>Enabled</td> 7.584 +<td width="524px" class="whs29"> 7.585 +<p class=Table>Enables the data inline memory.</td></tr> 7.586 + 7.587 +<tr valign="top" class="whs15"> 7.588 +<td width="167px" class="whs28"> 7.589 +<p class=Table>Instance Name</td> 7.590 +<td width="524px" class="whs29"> 7.591 +<p class=Table>Specifies the name of the data inline memory. Alphanumeric 7.592 + values and underscores are supported. The default is Data_IM.</td></tr> 7.593 + 7.594 +<tr valign="top" class="whs15"> 7.595 +<td width="167px" class="whs28"> 7.596 +<p class=Table>Base Address</td> 7.597 +<td width="524px" class="whs29"> 7.598 +<p class=Table>Specifies the base address for the data inline memory. The 7.599 + default is 0x20000000.</td></tr> 7.600 + 7.601 +<tr valign="top" class="whs15"> 7.602 +<td width="167px" class="whs28"> 7.603 +<p class=Table>Size of Memory in Bytes</td> 7.604 +<td width="524px" class="whs29"> 7.605 +<p class=Table>Specifies the size of the data inline memory.</td></tr> 7.606 + 7.607 +<tr valign="top" class="whs15"> 7.608 +<td colspan="2" rowspan="1" width="691px" class="whs27"> 7.609 +<p class=Table 7.610 + style="font-weight: bold;">Memory File</td> 7.611 +</tr> 7.612 + 7.613 +<tr valign="top" class="whs15"> 7.614 +<td colspan="1" rowspan="1" width="167px" class="whs28"> 7.615 +<p class=Table>Initialization File Name</td> 7.616 +<td colspan="1" rowspan="1" width="524px" class="whs29"> 7.617 +<p class=Table>Specifies the name of the memory initialization file for 7.618 + data inline memory.</td></tr> 7.619 + 7.620 +<tr valign="top" class="whs15"> 7.621 +<td colspan="1" rowspan="1" width="167px" class="whs30"> 7.622 +<p class=Table>File Format</td> 7.623 +<td colspan="1" rowspan="1" width="524px" class="whs31"> 7.624 +<p class=Table>Specifies the format of the memory initialization file: 7.625 + hex or binary.</td></tr> 7.626 +</table> 7.627 + 7.628 +<p> </p> 7.629 + 7.630 +<p>For the revision history of the component RTL files, refer to the header 7.631 + of each component Verilog source file. </p> 7.632 + 7.633 +<p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual 7.634 + fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, 7.635 + and then click the note button.</p> 7.636 + 7.637 +<script type="text/javascript" language="JavaScript"> 7.638 +<!-- 7.639 + if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) 7.640 + document.write("<div id='tooltip' class='WebHelpPopupMenu'></div>"); 7.641 +//--> 7.642 +</script><script type="text/javascript" language="javascript1.2"> 7.643 +<!-- 7.644 +if (window.writeIntopicBar) 7.645 + writeIntopicBar(0); 7.646 +//--> 7.647 +</script> 7.648 +</body> 7.649 +</html>
8.1 diff -r 0a26167af7e1 -r 0eb235b23d55 document/lm32_archman.pdf 8.2 Binary file document/lm32_archman.pdf has changed
9.1 diff -r 0a26167af7e1 -r 0eb235b23d55 document/qm_icon.jpg 9.2 Binary file document/qm_icon.jpg has changed
10.1 diff -r 0a26167af7e1 -r 0eb235b23d55 er1.v
11.1 diff -r 0a26167af7e1 -r 0eb235b23d55 jtag_cores.v
12.1 diff -r 0a26167af7e1 -r 0eb235b23d55 jtag_lm32.v
13.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_adder.v
14.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_addsub.v
15.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_cpu.v 15.2 --- a/lm32_cpu.v Tue Apr 06 18:27:55 2010 +0100 15.3 +++ b/lm32_cpu.v Fri Aug 13 01:15:02 2010 +0100 15.4 @@ -536,7 +536,6 @@ 15.5 `endif 15.6 wire direction_d; // Which direction to shift in 15.7 reg direction_x; 15.8 -reg direction_m; 15.9 wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter 15.10 `endif 15.11 `ifdef CFG_MC_BARREL_SHIFT_ENABLED 15.12 @@ -789,7 +788,6 @@ 15.13 .i_dat_i (I_DAT_I), 15.14 .i_ack_i (I_ACK_I), 15.15 .i_err_i (I_ERR_I), 15.16 - .i_rty_i (I_RTY_I), 15.17 `endif 15.18 `ifdef CFG_HW_DEBUG_ENABLED 15.19 .jtag_read_enable (jtag_read_enable), 15.20 @@ -932,7 +930,6 @@ 15.21 .stall_a (stall_a), 15.22 .stall_x (stall_x), 15.23 .stall_m (stall_m), 15.24 - .kill_x (kill_x), 15.25 .kill_m (kill_m), 15.26 .exception_m (exception_m), 15.27 .store_operand_x (store_operand_x), 15.28 @@ -957,7 +954,6 @@ 15.29 .d_dat_i (D_DAT_I), 15.30 .d_ack_i (D_ACK_I), 15.31 .d_err_i (D_ERR_I), 15.32 - .d_rty_i (D_RTY_I), 15.33 // ----- Outputs ------- 15.34 // To pipeline 15.35 `ifdef CFG_DCACHE_ENABLED 15.36 @@ -2264,8 +2260,8 @@ 15.37 `endif 15.38 `ifdef CFG_SIGN_EXTEND_ENABLED 15.39 x_result_sel_sext_x <= `FALSE; 15.40 -`endif 15.41 - x_result_sel_logic_x <= `FALSE; 15.42 +`endif 15.43 + x_result_sel_logic_x <= `FALSE; 15.44 `ifdef CFG_USER_ENABLED 15.45 x_result_sel_user_x <= `FALSE; 15.46 `endif 15.47 @@ -2331,9 +2327,6 @@ 15.48 exception_m <= `FALSE; 15.49 load_m <= `FALSE; 15.50 store_m <= `FALSE; 15.51 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 15.52 - direction_m <= `FALSE; 15.53 -`endif 15.54 write_enable_m <= `FALSE; 15.55 write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}}; 15.56 condition_met_m <= `FALSE; 15.57 @@ -2384,7 +2377,7 @@ 15.58 `ifdef CFG_SIGN_EXTEND_ENABLED 15.59 x_result_sel_sext_x <= x_result_sel_sext_d; 15.60 `endif 15.61 - x_result_sel_logic_x <= x_result_sel_logic_d; 15.62 + x_result_sel_logic_x <= x_result_sel_logic_d; 15.63 `ifdef CFG_USER_ENABLED 15.64 x_result_sel_user_x <= x_result_sel_user_d; 15.65 `endif 15.66 @@ -2458,7 +2451,6 @@ 15.67 end 15.68 m_bypass_enable_m <= m_bypass_enable_x; 15.69 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 15.70 - direction_m <= direction_x; 15.71 `endif 15.72 load_m <= load_x; 15.73 store_m <= store_x;
16.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_dcache.v
17.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_debug.v
18.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_decoder.v
19.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_functions.v
20.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_icache.v
21.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_include.v
22.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_instruction_unit.v 22.2 --- a/lm32_instruction_unit.v Tue Apr 06 18:27:55 2010 +0100 22.3 +++ b/lm32_instruction_unit.v Fri Aug 13 01:15:02 2010 +0100 22.4 @@ -91,7 +91,6 @@ 22.5 i_dat_i, 22.6 i_ack_i, 22.7 i_err_i, 22.8 - i_rty_i, 22.9 `endif 22.10 `ifdef CFG_HW_DEBUG_ENABLED 22.11 jtag_read_enable, 22.12 @@ -202,7 +201,6 @@ 22.13 input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data 22.14 input i_ack_i; // Instruction Wishbone interface acknowledgement 22.15 input i_err_i; // Instruction Wishbone interface error 22.16 -input i_rty_i; // Instruction Wishbone interface retry 22.17 `endif 22.18 22.19 `ifdef CFG_HW_DEBUG_ENABLED
23.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_interrupt.v
24.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_jtag.v
25.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_load_store_unit.v 25.2 --- a/lm32_load_store_unit.v Tue Apr 06 18:27:55 2010 +0100 25.3 +++ b/lm32_load_store_unit.v Fri Aug 13 01:15:02 2010 +0100 25.4 @@ -53,7 +53,6 @@ 25.5 stall_a, 25.6 stall_x, 25.7 stall_m, 25.8 - kill_x, 25.9 kill_m, 25.10 exception_m, 25.11 store_operand_x, 25.12 @@ -132,7 +131,6 @@ 25.13 input stall_a; // A stage stall 25.14 input stall_x; // X stage stall 25.15 input stall_m; // M stage stall 25.16 -input kill_x; // Kill instruction in X stage 25.17 input kill_m; // Kill instruction in M stage 25.18 input exception_m; // An exception occured in the M stage 25.19
26.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_logic_op.v
27.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_mc_arithmetic.v
28.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_monitor.v 28.2 --- a/lm32_monitor.v Tue Apr 06 18:27:55 2010 +0100 28.3 +++ b/lm32_monitor.v Fri Aug 13 01:15:02 2010 +0100 28.4 @@ -43,9 +43,6 @@ 28.5 MON_SEL_I, 28.6 MON_STB_I, 28.7 MON_WE_I, 28.8 - MON_LOCK_I, 28.9 - MON_CTI_I, 28.10 - MON_BTE_I, 28.11 // ----- Outputs ------- 28.12 MON_ACK_O, 28.13 MON_RTY_O, 28.14 @@ -59,15 +56,12 @@ 28.15 28.16 input clk_i; // Wishbone clock 28.17 input rst_i; // Wishbone reset 28.18 -input [`LM32_WORD_RNG] MON_ADR_I; // Wishbone address 28.19 +input [10:2] MON_ADR_I; // Wishbone address 28.20 input MON_STB_I; // Wishbone strobe 28.21 input MON_CYC_I; // Wishbone cycle 28.22 input [`LM32_WORD_RNG] MON_DAT_I; // Wishbone write data 28.23 input [`LM32_BYTE_SELECT_RNG] MON_SEL_I; // Wishbone byte select 28.24 input MON_WE_I; // Wishbone write enable 28.25 -input MON_LOCK_I; // Wishbone locked transfer 28.26 -input [`LM32_CTYPE_RNG] MON_CTI_I; // Wishbone cycle type 28.27 -input [`LM32_BTYPE_RNG] MON_BTE_I; // Wishbone burst type 28.28 28.29 ///////////////////////////////////////////////////// 28.30 // Outputs
29.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_monitor_ram.v
30.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_multiplier.v
31.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_ram.v
32.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_shifter.v
33.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_top.v 33.2 --- a/lm32_top.v Tue Apr 06 18:27:55 2010 +0100 33.3 +++ b/lm32_top.v Fri Aug 13 01:15:02 2010 +0100 33.4 @@ -356,15 +356,12 @@ 33.5 // ----- Inputs ------- 33.6 .clk_i (clk_i), 33.7 .rst_i (rst_i), 33.8 - .MON_ADR_I (DEBUG_ADR_I), 33.9 + .MON_ADR_I (DEBUG_ADR_I[10:2]), 33.10 .MON_STB_I (DEBUG_STB_I & ~DEBUG_ADR_I[13]), 33.11 .MON_CYC_I (DEBUG_CYC_I & ~DEBUG_ADR_I[13]), 33.12 .MON_WE_I (DEBUG_WE_I), 33.13 .MON_SEL_I (DEBUG_SEL_I), 33.14 .MON_DAT_I (DEBUG_DAT_I), 33.15 - .MON_CTI_I (DEBUG_CTI_I), 33.16 - .MON_BTE_I (DEBUG_BTE_I), 33.17 - .MON_LOCK_I (DEBUG_LOCK_I), 33.18 // ----- Outputs ------ 33.19 .MON_RTY_O (DEBUG_RTY_O), 33.20 .MON_ERR_O (DEBUG_ERR_O),
34.1 diff -r 0a26167af7e1 -r 0eb235b23d55 lm32_trace.v
35.1 diff -r 0a26167af7e1 -r 0eb235b23d55 spiprog.v
36.1 diff -r 0a26167af7e1 -r 0eb235b23d55 typea.v
37.1 diff -r 0a26167af7e1 -r 0eb235b23d55 typeb.v