IPCores/lm32_dma / changelog

Update to LM32 DMA v3.3 default tip

• Sat, 06 Aug 2011 01:48:48 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Sat, 06 Aug 2011 01:48:48 +0100] rev 1
• Update to LM32 DMA v3.3
  
  +// Version : 3.2
  +// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and
  +// : Read/Write Ports can be independently configured.
  +// : 2. Support for "retry" on receipt of a WISHBONE RTY. This
  +// : retry results in the current burst or classic cycle
  +// : being issued again after a retry timeout.
  +// : 3. Support for "error" on receipt of a WISHBONE ERR. This
  +// : results in the current dma transfer being terminated
  +// : and the error is updated within the STATUS CSR.
  +// : 4. Support for burst size of 64.
  +// :
  +// Version : 3.3
  +// : Support for MachXO2 added. The MachXO2 only has a FIFO
  +// : with separate read/write clocks.

Initial commit, DMAC version 3.1

• Fri, 13 Aug 2010 10:43:05 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Fri, 13 Aug 2010 10:43:05 +0100] rev 0
• Initial commit, DMAC version 3.1