1.1 --- a/rtl/verilog/slave_reg.v Fri Aug 13 10:43:05 2010 +0100 1.2 +++ b/rtl/verilog/slave_reg.v Sat Aug 06 01:48:48 2011 +0100 1.3 @@ -1,234 +1,475 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 +// ================================================================== 1.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.15 +// ------------------------------------------------------------------ 1.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.17 +// ALL RIGHTS RESERVED 1.18 +// ------------------------------------------------------------------ 1.19 +// 1.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.21 +// 1.22 +// Permission: 1.23 +// 1.24 +// Lattice Semiconductor grants permission to use this code 1.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.26 +// Open Source License Agreement. 1.27 +// 1.28 +// Disclaimer: 1.29 // 1.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.33 -// U.S.A email: techsupport@latticesemi.com 1.34 -// =============================================================================/ 1.35 +// Lattice Semiconductor provides no warranty regarding the use or 1.36 +// functionality of this code. It is the user's responsibility to 1.37 +// verify the user’s design for consistency and functionality through 1.38 +// the use of formal verification methods. 1.39 +// 1.40 +// -------------------------------------------------------------------- 1.41 +// 1.42 +// Lattice Semiconductor Corporation 1.43 +// 5555 NE Moore Court 1.44 +// Hillsboro, OR 97214 1.45 +// U.S.A 1.46 +// 1.47 +// TEL: 1-800-Lattice (USA and Canada) 1.48 +// 503-286-8001 (other locations) 1.49 +// 1.50 +// web: http://www.latticesemi.com/ 1.51 +// email: techsupport@latticesemi.com 1.52 +// 1.53 +// -------------------------------------------------------------------- 1.54 // FILE DETAILS 1.55 // Project : LM32 DMA Component 1.56 // File : slave_reg.v 1.57 // Title : DMA Slave controller 1.58 // Dependencies : None 1.59 +// : 1.60 // Version : 7.0 1.61 // : Initial Release 1.62 +// : 1.63 // Version : 7.0SP2, 3.0 1.64 -// 1. Read and Write channel of DMA controller are working in parallel, 1.65 -// due to that now as soon as FIFO is not empty write channel of the DMA 1.66 -// controller start writing data to the slave. 1.67 -// 2. Burst Size supported by DMA controller is increased to support bigger 1.68 -// burst (from current value of 4 and 8 to 16 and 32). Now 4 different type 1.69 -// of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 1.70 -// For this Burst Size field of the control register is increased to 2 bits. 1.71 -// 3. Glitch is removed on the S_ACK_O signal. 1.72 +// : 1. Read and Write channel of DMA controller are working in 1.73 +// : parallel, due to that now as soon as FIFO is not empty 1.74 +// : write channel of the DMA controller start writing data 1.75 +// : to the slave. 1.76 +// : 2. Burst Size supported by DMA controller is increased to 1.77 +// : support bigger burst (from current value of 4 and 8 to 1.78 +// : 16 and 32). Now 4 different type of burst sizes are 1.79 +// : supported by the DMA controller 4, 8, 16 and 32. For 1.80 +// : this Burst Size field of the control register is 1.81 +// : increased to 2 bits. 1.82 +// : 3. Glitch is removed on the S_ACK_O signal. 1.83 +// : 1.84 // Version : 3.1 1.85 -// : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec 1.86 -// : which defines alignement of bytes in sub-word transfers. 1.87 +// : 1. Make DMA Engine compliant to Rule 3.100 of Wishbone Spec 1.88 +// : which defines alignement of bytes in sub-word transfers. 1.89 +// : 2. Removed glitch that did not pause the burst write when 1.90 +// : the read burst was paused by the "read slave". 1.91 +// : 1.92 +// Version : 3.2 1.93 +// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and 1.94 +// : Read/Write Ports can be independently configured. 1.95 +// : 2. Support for burst size of 64. 1.96 +// : 1.97 +// Version : 3.3 1.98 +// : 1. Interrupt can be release by writing 0 to IE bit in the 1.99 +// : status register. 1.100 // ============================================================================= 1.101 1.102 `ifndef SLAVE_REG_FILE 1.103 `define SLAVE_REG_FILE 1.104 `include "system_conf.v" 1.105 module SLAVE_REG 1.106 - #(parameter LENGTH_WIDTH = 16, 1.107 + #(parameter S_WB_DAT_WIDTH = 32, 1.108 + parameter S_WB_ADR_WIDTH = 32, 1.109 + parameter MA_WB_DAT_WIDTH = 32, 1.110 + parameter MA_WB_ADR_WIDTH = 32, 1.111 + parameter RETRY_TIMEOUT = 16, 1.112 parameter FIFO_IMPLEMENTATION = "EBR") 1.113 - ( 1.114 - //slave port 1.115 - S_ADR_I, //32bits 1.116 - S_DAT_I, //32bits 1.117 - S_WE_I, 1.118 - S_STB_I, 1.119 - S_CYC_I, 1.120 - S_CTI_I, 1.121 - S_DAT_O, //32bits 1.122 - S_ACK_O, 1.123 - S_INT_O, 1.124 - //Master Address 1.125 -// MA_SEL_O, 1.126 -// MB_SEL_O, 1.127 - M_SEL_O, 1.128 - //internal signals 1.129 - reg_start, 1.130 - reg_status, 1.131 - reg_interrupt, 1.132 - reg_busy, 1.133 - data_length, 1.134 - reg_cntlg, 1.135 - reg_bt2,reg_bt1,reg_bt0, 1.136 - incr_unit, 1.137 - reg_s_con, 1.138 - reg_d_con, 1.139 - reg_00_data, 1.140 - reg_04_data, 1.141 - //system clock and reset 1.142 - CLK_I, 1.143 - RST_I 1.144 - ); 1.145 - 1.146 - input [31:0] S_ADR_I; 1.147 - input [31:0] S_DAT_I; //32bits 1.148 - input S_WE_I; 1.149 - input S_STB_I; 1.150 - input S_CYC_I; 1.151 - input [2:0] S_CTI_I; 1.152 - output [31:0] S_DAT_O; //32bits 1.153 - output S_ACK_O; 1.154 - output S_INT_O; //interrupt signal 1.155 - //Master Address 1.156 - output [3:0] M_SEL_O; 1.157 -// output [3:0] MA_SEL_O; 1.158 -// output [3:0] MB_SEL_O; 1.159 - //internal signals 1.160 - output reg_start; 1.161 - input reg_status; 1.162 - input reg_interrupt; 1.163 - input reg_busy; 1.164 - output [LENGTH_WIDTH-1:0] data_length; 1.165 - input reg_cntlg; 1.166 - output reg_bt2,reg_bt1,reg_bt0; 1.167 - output [2:0] incr_unit; 1.168 - output reg_s_con; 1.169 - output reg_d_con; 1.170 - output [31:0] reg_00_data; 1.171 - output [31:0] reg_04_data; 1.172 - 1.173 - //system clock and reset 1.174 - input CLK_I; 1.175 - input RST_I; 1.176 - 1.177 - parameter UDLY = 1; 1.178 - 1.179 - reg [31:0] reg_00_data; 1.180 - reg [31:0] reg_04_data; 1.181 - reg [LENGTH_WIDTH-1:0] reg_08_data; 1.182 - reg [6:0] reg_0c_data; 1.183 - 1.184 - reg [3:0] M_SEL_O; 1.185 -// wire [3:0] MA_SEL_O = M_SEL_O; 1.186 -// wire [3:0] MB_SEL_O = M_SEL_O; 1.187 - wire [LENGTH_WIDTH-1:0] data_length = reg_08_data; 1.188 - 1.189 - wire reg_bt2, reg_bt1, reg_bt0, reg_incw, reg_inchw, reg_d_con, reg_s_con; 1.190 - assign {reg_bt2,reg_bt1,reg_bt0,reg_incw,reg_inchw,reg_d_con,reg_s_con} = reg_0c_data; 1.191 - wire [2:0] incr_unit = reg_incw ? 4 : reg_inchw ? 2 : 1; 1.192 - 1.193 - wire [8:0] burst_incr_unit = reg_bt2 ? (reg_bt1 ? (reg_bt0 ? incr_unit<<5 : incr_unit<<4) : (reg_bt0 ? incr_unit<<3 : incr_unit<<2)) : incr_unit; 1.194 - reg reg_ie; 1.195 - wire [2:0] read_10_data = {reg_status,reg_ie,reg_busy}; 1.196 - 1.197 - wire reg_wr_rd = S_CYC_I && S_STB_I; 1.198 - 1.199 - wire master_idle = !reg_busy; 1.200 - reg s_ack_o_pre; 1.201 - wire S_ACK_O = s_ack_o_pre && S_CYC_I && S_STB_I; 1.202 + ( 1.203 + input CLK_I, 1.204 + input RST_I, 1.205 + 1.206 + // Slave port 1.207 + input [S_WB_ADR_WIDTH-1:0] S_ADR_I, 1.208 + input [S_WB_DAT_WIDTH-1:0] S_DAT_I, 1.209 + input [S_WB_DAT_WIDTH/8-1:0] S_SEL_I, 1.210 + input S_WE_I, 1.211 + input S_STB_I, 1.212 + input S_CYC_I, 1.213 + input [2:0] S_CTI_I, 1.214 + output [S_WB_DAT_WIDTH-1:0] S_DAT_O, 1.215 + output reg S_ACK_O, 1.216 + output reg S_INT_O, 1.217 + 1.218 + output reg reg_start, 1.219 + input reg_status, 1.220 + input reg_interrupt, 1.221 + input reg_busy, 1.222 + output reg reg_bt3, reg_bt2, reg_bt1, reg_bt0, 1.223 + output reg reg_s_con, reg_d_con, 1.224 + output reg reg_incw, reg_inchw, 1.225 + output reg [7:0] reg_rdelay, 1.226 + output reg [31:0] reg_00_data, 1.227 + output reg [31:0] reg_04_data, 1.228 + output reg [31:0] reg_08_data 1.229 + ); 1.230 + 1.231 + parameter UDLY = 1; 1.232 + 1.233 + reg [31:0] reg_00_data_nxt, reg_04_data_nxt, reg_08_data_nxt; 1.234 + reg [7:0] reg_0c_data, reg_0c_data_nxt; 1.235 + 1.236 + always @(/*AUTOSENSE*/reg_0c_data) 1.237 + begin 1.238 + //reg_rdelay = reg_0c_data[23:16]; 1.239 + reg_rdelay = RETRY_TIMEOUT; 1.240 + reg_bt3 = reg_0c_data[7]; 1.241 + reg_bt2 = reg_0c_data[6]; 1.242 + reg_bt1 = reg_0c_data[5]; 1.243 + reg_bt0 = reg_0c_data[4]; 1.244 + reg_incw = reg_0c_data[3]; 1.245 + reg_inchw = reg_0c_data[2]; 1.246 + reg_d_con = reg_0c_data[1]; 1.247 + reg_s_con = reg_0c_data[0]; 1.248 + end 1.249 + 1.250 + reg [2:0] read_10_data; 1.251 + reg reg_ie; 1.252 + always @(/*AUTOSENSE*/reg_busy or reg_ie or reg_status) 1.253 + begin 1.254 + read_10_data[2] = reg_status; 1.255 + read_10_data[1] = reg_ie; 1.256 + read_10_data[0] = reg_busy; 1.257 + end 1.258 + 1.259 + wire master_idle, reg_wr_rd, reg_wr, reg_rd; 1.260 + assign master_idle = ~reg_busy; 1.261 + assign reg_wr_rd = S_CYC_I & S_STB_I; 1.262 + assign reg_wr = reg_wr_rd & master_idle & S_WE_I & S_ACK_O; 1.263 + assign reg_rd = reg_wr_rd & ~S_WE_I & S_ACK_O; 1.264 + 1.265 + reg s_ack_o_pre, s_ack_o_pre_nxt; 1.266 + always @(/*AUTOSENSE*/S_CYC_I or S_STB_I or S_WE_I or master_idle 1.267 + or reg_wr_rd or s_ack_o_pre) 1.268 + begin 1.269 + if ((s_ack_o_pre == 1'b0) 1.270 + && ((master_idle && reg_wr_rd) 1.271 + || ((master_idle == 1'b0) && reg_wr_rd && (S_WE_I == 1'b0)))) 1.272 + s_ack_o_pre_nxt = 1'b1; 1.273 + else 1.274 + s_ack_o_pre_nxt = 1'b0; 1.275 + 1.276 + S_ACK_O = s_ack_o_pre && S_CYC_I && S_STB_I; 1.277 + end 1.278 1.279 always @(posedge CLK_I or posedge RST_I) 1.280 - if(RST_I) 1.281 - s_ack_o_pre <= #UDLY 1'b0; 1.282 - else if(((master_idle && reg_wr_rd) || (!master_idle && reg_wr_rd && !S_WE_I)) && (!s_ack_o_pre)) 1.283 - s_ack_o_pre <= #UDLY 1'b1; 1.284 - else 1.285 - s_ack_o_pre <= #UDLY 1'b0; 1.286 - 1.287 - 1.288 - //register write and read 1.289 - wire reg_wr = reg_wr_rd && S_WE_I && master_idle && S_ACK_O; 1.290 - wire reg_rd = reg_wr_rd && !S_WE_I && S_ACK_O; 1.291 - 1.292 - wire dw00_cs = (!(|S_ADR_I[5:2])); 1.293 - wire dw04_cs = (S_ADR_I[5:2] == 4'h1); 1.294 - wire dw08_cs = (S_ADR_I[5:2] == 4'h2); 1.295 - wire dw0c_cs = (S_ADR_I[5:2] == 4'h3); 1.296 - wire dw10_cs = (S_ADR_I[5:2] == 4'h4); 1.297 + if (RST_I) 1.298 + s_ack_o_pre <= #UDLY 1'b0; 1.299 + else 1.300 + s_ack_o_pre <= #UDLY s_ack_o_pre_nxt; 1.301 + 1.302 + wire dw00_cs, dw04_cs, dw08_cs, dw0c_cs, dw10_cs; 1.303 + assign dw00_cs = (S_ADR_I[5:2] == 4'h0); 1.304 + assign dw04_cs = (S_ADR_I[5:2] == 4'h1); 1.305 + assign dw08_cs = (S_ADR_I[5:2] == 4'h2); 1.306 + assign dw0c_cs = (S_ADR_I[5:2] == 4'h3); 1.307 + assign dw10_cs = (S_ADR_I[5:2] == 4'h4); 1.308 + 1.309 + wire [31:0] S_DAT_O_int = (dw00_cs 1.310 + ? reg_00_data 1.311 + : (dw04_cs 1.312 + ? reg_04_data 1.313 + : (dw08_cs 1.314 + ? reg_08_data 1.315 + : (dw0c_cs 1.316 + ? {4{reg_0c_data}} 1.317 + : (dw10_cs 1.318 + ? {4{5'h0,read_10_data}} 1.319 + : 32'h0))))); 1.320 + generate 1.321 + if (S_WB_DAT_WIDTH == 8) begin 1.322 + 1.323 + assign S_DAT_O = ((S_ADR_I[1:0] == 2'b00) 1.324 + ? S_DAT_O_int[31:24] 1.325 + : ((S_ADR_I[1:0] == 2'b01) 1.326 + ? S_DAT_O_int[23:16] 1.327 + : ((S_ADR_I[1:0] == 2'b10) 1.328 + ? S_DAT_O_int[15:8] 1.329 + : S_DAT_O_int[7:0]))); 1.330 + 1.331 + end 1.332 + else begin 1.333 + 1.334 + assign S_DAT_O = S_DAT_O_int; 1.335 + 1.336 + end 1.337 + endgenerate 1.338 + 1.339 + 1.340 + 1.341 + // Interrupt 1.342 + generate 1.343 + if (S_WB_DAT_WIDTH == 8) begin 1.344 + 1.345 + always @(posedge CLK_I or posedge RST_I) 1.346 + begin 1.347 + if(RST_I) 1.348 + S_INT_O <= #UDLY 1'b0; 1.349 + else if(reg_interrupt && reg_ie) 1.350 + S_INT_O <= #UDLY 1'b1; 1.351 + else if(dw10_cs && (reg_rd || (reg_wr && (S_DAT_I[1] == 1'b0)))) 1.352 + S_INT_O <= #UDLY 1'b0; 1.353 + end 1.354 + 1.355 + end 1.356 + else begin 1.357 + 1.358 + always @(posedge CLK_I or posedge RST_I) 1.359 + begin 1.360 + if(RST_I) 1.361 + S_INT_O <= #UDLY 1'b0; 1.362 + else if(reg_interrupt && reg_ie) 1.363 + S_INT_O <= #UDLY 1'b1; 1.364 + else if(dw10_cs && (reg_rd || (reg_wr && (S_DAT_I[25] == 1'b0)))) 1.365 + S_INT_O <= #UDLY 1'b0; 1.366 + end 1.367 + 1.368 + end 1.369 + endgenerate 1.370 + 1.371 + // reg_00 1.372 + generate 1.373 + if (S_WB_DAT_WIDTH == 8) begin 1.374 1.375 - //S_DAT_O 1.376 - wire [31:0] S_DAT_O = dw00_cs ? reg_00_data : 1.377 - dw04_cs ? reg_04_data : 1.378 - dw08_cs ? reg_08_data : 1.379 - dw0c_cs ? {24'h0,1'h0,reg_0c_data} : 1.380 - dw10_cs ? {24'h0,5'h0,read_10_data} : 32'h0; 1.381 + always @(/*AUTOSENSE*/S_ADR_I or S_DAT_I or dw00_cs 1.382 + or reg_00_data or reg_wr) 1.383 + begin 1.384 + if (dw00_cs && reg_wr) begin 1.385 + casez (S_ADR_I[1:0]) 1.386 + 2'b00: reg_00_data_nxt = { S_DAT_I[7:0], reg_00_data[23: 0]}; 1.387 + 2'b01: reg_00_data_nxt = {reg_00_data[31:24], S_DAT_I[7:0], reg_00_data[15: 0]}; 1.388 + 2'b10: reg_00_data_nxt = {reg_00_data[31:16], S_DAT_I[7:0], reg_00_data[ 7: 0]}; 1.389 + 2'b11: reg_00_data_nxt = {reg_00_data[31: 8], S_DAT_I[7:0] }; 1.390 + 1.391 + default: 1.392 + reg_00_data_nxt = reg_00_data; 1.393 + endcase 1.394 + end 1.395 + else 1.396 + reg_00_data_nxt = reg_00_data; 1.397 + end 1.398 + 1.399 + end 1.400 + else begin 1.401 + 1.402 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw00_cs 1.403 + or reg_00_data or reg_wr) 1.404 + begin 1.405 + if (dw00_cs && reg_wr) begin 1.406 + casez (S_SEL_I) 1.407 + 4'b1000: reg_00_data_nxt = { S_DAT_I[31:24], reg_00_data[23:0]}; 1.408 + 4'b0100: reg_00_data_nxt = {reg_00_data[31:24], S_DAT_I[23:16], reg_00_data[15:0]}; 1.409 + 4'b0010: reg_00_data_nxt = {reg_00_data[31:16], S_DAT_I[15: 8], reg_00_data[ 7:0]}; 1.410 + 4'b0001: reg_00_data_nxt = {reg_00_data[31: 8], S_DAT_I[ 7: 0] }; 1.411 + 4'b1111: reg_00_data_nxt = S_DAT_I[31: 0] ; 1.412 + 1.413 + default: 1.414 + reg_00_data_nxt = reg_00_data; 1.415 + endcase 1.416 + end 1.417 + else 1.418 + reg_00_data_nxt = reg_00_data; 1.419 + end 1.420 + 1.421 + end 1.422 + endgenerate 1.423 + 1.424 + always @(posedge CLK_I or posedge RST_I) 1.425 + if (RST_I) 1.426 + reg_00_data <= #UDLY 32'b0; 1.427 + else 1.428 + reg_00_data <= #UDLY reg_00_data_nxt; 1.429 + 1.430 + 1.431 + 1.432 + // reg_04 1.433 + generate 1.434 + if (S_WB_DAT_WIDTH == 8) begin 1.435 1.436 - always @(posedge CLK_I or posedge RST_I) 1.437 - if(RST_I) 1.438 - M_SEL_O <= #UDLY 4'h0; 1.439 - else if(data_length < incr_unit) 1.440 - case(data_length[2:0]) 1.441 - 1: M_SEL_O <= #UDLY 4'h8; 1.442 - 2: M_SEL_O <= #UDLY 4'hc; 1.443 - 3: M_SEL_O <= #UDLY 4'he; 1.444 - default:M_SEL_O <= #UDLY 4'hf; 1.445 - endcase 1.446 - else 1.447 - case(incr_unit) 1.448 - 1: M_SEL_O <= #UDLY 4'h8; 1.449 - 2: M_SEL_O <= #UDLY 4'hc; 1.450 - 4: M_SEL_O <= #UDLY 4'hf; 1.451 - default:M_SEL_O <= #UDLY 4'hf; 1.452 - endcase 1.453 - //interrupt 1.454 - reg S_INT_O; 1.455 + always @(/*AUTOSENSE*/S_ADR_I or S_DAT_I or dw04_cs 1.456 + or reg_04_data or reg_wr) 1.457 + begin 1.458 + if (dw04_cs && reg_wr) begin 1.459 + casez (S_ADR_I[1:0]) 1.460 + 2'b00: reg_04_data_nxt = { S_DAT_I[7:0], reg_04_data[23: 0]}; 1.461 + 2'b01: reg_04_data_nxt = {reg_04_data[31:24], S_DAT_I[7:0], reg_04_data[15: 0]}; 1.462 + 2'b10: reg_04_data_nxt = {reg_04_data[31:16], S_DAT_I[7:0], reg_04_data[ 7: 0]}; 1.463 + 2'b11: reg_04_data_nxt = {reg_04_data[31: 8], S_DAT_I[7:0] }; 1.464 + 1.465 + default: 1.466 + reg_04_data_nxt = reg_04_data; 1.467 + endcase 1.468 + end 1.469 + else 1.470 + reg_04_data_nxt = reg_04_data; 1.471 + end 1.472 + 1.473 + end 1.474 + else begin 1.475 + 1.476 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw04_cs 1.477 + or reg_04_data or reg_wr) 1.478 + begin 1.479 + if (dw04_cs && reg_wr) begin 1.480 + casez (S_SEL_I) 1.481 + 4'b1000: reg_04_data_nxt = { S_DAT_I[31:24], reg_04_data[23:0]}; 1.482 + 4'b0100: reg_04_data_nxt = {reg_04_data[31:24], S_DAT_I[23:16], reg_04_data[15:0]}; 1.483 + 4'b0010: reg_04_data_nxt = {reg_04_data[31:16], S_DAT_I[15: 8], reg_04_data[ 7:0]}; 1.484 + 4'b0001: reg_04_data_nxt = {reg_04_data[31: 8], S_DAT_I[ 7: 0] }; 1.485 + 4'b1111: reg_04_data_nxt = { S_DAT_I[31: 0] }; 1.486 + 1.487 + default: 1.488 + reg_04_data_nxt = reg_04_data; 1.489 + endcase 1.490 + end 1.491 + else 1.492 + reg_04_data_nxt = reg_04_data; 1.493 + end 1.494 + 1.495 + end 1.496 + endgenerate 1.497 + 1.498 always @(posedge CLK_I or posedge RST_I) 1.499 - if(RST_I) 1.500 - S_INT_O <= #UDLY 1'b0; 1.501 - else if(reg_interrupt && reg_ie) 1.502 - S_INT_O <= #UDLY 1'b1; 1.503 - else if(dw10_cs && reg_rd) 1.504 - S_INT_O <= #UDLY 1'b0; 1.505 + if (RST_I) 1.506 + reg_04_data <= #UDLY 32'b0; 1.507 + else 1.508 + reg_04_data <= #UDLY reg_04_data_nxt; 1.509 + 1.510 + 1.511 + 1.512 + // reg_08 1.513 + generate 1.514 + if (S_WB_DAT_WIDTH == 8) begin 1.515 1.516 - //reg_00 1.517 - always @(posedge CLK_I or posedge RST_I) 1.518 - if(RST_I) 1.519 - reg_00_data <= #UDLY 32'h0; 1.520 - else if(dw00_cs && reg_wr) 1.521 - reg_00_data <= #UDLY S_DAT_I; 1.522 - 1.523 - //reg_04 1.524 - always @(posedge CLK_I or posedge RST_I) 1.525 - if(RST_I) 1.526 - reg_04_data <= #UDLY 32'h0; 1.527 - else if(dw04_cs && reg_wr) 1.528 - reg_04_data <= #UDLY S_DAT_I; 1.529 - 1.530 - //reg_08 1.531 + always @(/*AUTOSENSE*/S_ADR_I or S_DAT_I or dw08_cs 1.532 + or reg_08_data or reg_wr) 1.533 + if (dw08_cs && reg_wr) begin 1.534 + casez (S_ADR_I[1:0]) 1.535 + 2'b00: reg_08_data_nxt = { S_DAT_I[7:0], reg_08_data[23: 0]}; 1.536 + 2'b01: reg_08_data_nxt = {reg_08_data[31:24], S_DAT_I[7:0], reg_08_data[15: 0]}; 1.537 + 2'b10: reg_08_data_nxt = {reg_08_data[31:16], S_DAT_I[7:0], reg_08_data[ 7: 0]}; 1.538 + 2'b11: reg_08_data_nxt = {reg_08_data[31: 8], S_DAT_I[7:0] }; 1.539 + 1.540 + default: 1.541 + reg_08_data_nxt = reg_08_data; 1.542 + endcase 1.543 + end 1.544 + 1.545 + end 1.546 + else begin 1.547 + 1.548 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw08_cs 1.549 + or reg_08_data or reg_wr) 1.550 + if (dw08_cs && reg_wr) begin 1.551 + casez (S_SEL_I) 1.552 + 4'b1000: reg_08_data_nxt = { S_DAT_I[31:24], reg_08_data[23:0]}; 1.553 + 4'b0100: reg_08_data_nxt = {reg_08_data[31:24], S_DAT_I[23:16], reg_08_data[15:0]}; 1.554 + 4'b0010: reg_08_data_nxt = {reg_08_data[31:16], S_DAT_I[15: 8], reg_08_data[ 7:0]}; 1.555 + 4'b0001: reg_08_data_nxt = {reg_08_data[31: 8], S_DAT_I[ 7: 0] }; 1.556 + 4'b1111: reg_08_data_nxt = { S_DAT_I[31: 0] }; 1.557 + 1.558 + default: 1.559 + reg_08_data_nxt = reg_08_data; 1.560 + endcase 1.561 + end 1.562 + 1.563 + end 1.564 + endgenerate 1.565 + 1.566 always @(posedge CLK_I or posedge RST_I) 1.567 - if(RST_I) 1.568 - reg_08_data <= #UDLY 32'h0; 1.569 - else if(reg_cntlg) 1.570 - reg_08_data <= #UDLY (reg_08_data < burst_incr_unit) ? 'h0 : (reg_08_data - burst_incr_unit); 1.571 - else if(dw08_cs && reg_wr) 1.572 - reg_08_data <= #UDLY S_DAT_I; 1.573 - 1.574 - //reg_0c 1.575 + if (RST_I) 1.576 + reg_08_data <= #UDLY 0; 1.577 + else 1.578 + reg_08_data <= #UDLY reg_08_data_nxt[31:0]; 1.579 + 1.580 + 1.581 + 1.582 + // reg_0c 1.583 + generate 1.584 + if (S_WB_DAT_WIDTH == 8) begin 1.585 + 1.586 + always @(/*AUTOSENSE*/S_DAT_I or dw0c_cs or reg_0c_data 1.587 + or reg_wr) 1.588 + if (dw0c_cs && reg_wr) 1.589 + reg_0c_data_nxt = S_DAT_I[7:0]; 1.590 + else 1.591 + reg_0c_data_nxt = reg_0c_data; 1.592 + 1.593 + end 1.594 + else begin 1.595 + 1.596 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw0c_cs 1.597 + or reg_0c_data or reg_wr) 1.598 + if (dw0c_cs && reg_wr) 1.599 + reg_0c_data_nxt = S_DAT_I[31:24]; 1.600 + else 1.601 + reg_0c_data_nxt = reg_0c_data; 1.602 + 1.603 + end 1.604 + endgenerate 1.605 + 1.606 always @(posedge CLK_I or posedge RST_I) 1.607 - if(RST_I) 1.608 - reg_0c_data <= #UDLY 7'h0; 1.609 - else if(dw0c_cs && reg_wr) 1.610 - reg_0c_data <= #UDLY S_DAT_I[6:0]; 1.611 - 1.612 - //reg_10 1.613 - reg reg_start; 1.614 + if (RST_I) 1.615 + reg_0c_data <= #UDLY 8'b0; 1.616 + else 1.617 + reg_0c_data <= #UDLY reg_0c_data_nxt; 1.618 + 1.619 + 1.620 + 1.621 + // reg_10 1.622 + reg reg_ie_nxt, reg_start_nxt; 1.623 + generate 1.624 + if (S_WB_DAT_WIDTH == 8) begin 1.625 + 1.626 + always @(/*AUTOSENSE*/S_DAT_I or dw10_cs or reg_ie or reg_wr) 1.627 + if (dw10_cs && reg_wr) 1.628 + begin 1.629 + reg_ie_nxt = S_DAT_I[1]; 1.630 + reg_start_nxt = S_DAT_I[3]; 1.631 + end 1.632 + else 1.633 + begin 1.634 + reg_ie_nxt = reg_ie; 1.635 + reg_start_nxt = 1'b0; 1.636 + end 1.637 + 1.638 + end 1.639 + else begin 1.640 + 1.641 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw10_cs or reg_ie 1.642 + or reg_wr) 1.643 + if (dw10_cs && reg_wr) 1.644 + begin 1.645 + reg_ie_nxt = S_DAT_I[25]; 1.646 + reg_start_nxt = S_DAT_I[27]; 1.647 + end 1.648 + else 1.649 + begin 1.650 + reg_ie_nxt = reg_ie; 1.651 + reg_start_nxt = 1'b0; 1.652 + end 1.653 + 1.654 + end 1.655 + endgenerate 1.656 + 1.657 always @(posedge CLK_I or posedge RST_I) 1.658 - if(RST_I) 1.659 + if (RST_I) 1.660 begin 1.661 - reg_ie <= #UDLY 1'b0; 1.662 - reg_start <= #UDLY 1'b0; 1.663 - end 1.664 - else if(dw10_cs && reg_wr) 1.665 + reg_ie <= #UDLY 1'b0; 1.666 + reg_start <= #UDLY 1'b0; 1.667 + end 1.668 + else 1.669 begin 1.670 - reg_ie <= #UDLY S_DAT_I[1]; 1.671 - reg_start <= #UDLY S_DAT_I[3]; 1.672 + reg_ie <= #UDLY reg_ie_nxt; 1.673 + reg_start <= #UDLY reg_start_nxt; 1.674 end 1.675 - else 1.676 - begin 1.677 - reg_start <= #UDLY 1'b0; 1.678 - end 1.679 + 1.680 endmodule // SLAVE_REG 1.681 `endif // SLAVE_REG_FILE