IPCores/lm32_gpio / annotate

drivers/device/MicoGPIO.h@267b5a25932f (annotated)

drivers/device/MicoGPIO.h

Fri, 13 Aug 2010 10:41:29 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 13 Aug 2010 10:41:29 +0100
changeset 0
267b5a25932f
permissions
-rw-r--r--

Initial commit, GPIO v3.1

philpem@0 1 /****************************************************************************
philpem@0 2 **
philpem@0 3 ** Name: MicoGPIO.h
philpem@0 4 **
philpem@0 5 ** Description:
philpem@0 6 ** Declares GPIO register structure and
philpem@0 7 ** macros/functions for manipulating GPIO
philpem@0 8 **
philpem@0 9 ** $Revision: $
philpem@0 10 **
philpem@0 11 ** Disclaimer:
philpem@0 12 **
philpem@0 13 ** This source code is intended as a design reference which
philpem@0 14 ** illustrates how these types of functions can be implemented. It
philpem@0 15 ** is the user's responsibility to verify their design for
philpem@0 16 ** consistency and functionality through the use of formal
philpem@0 17 ** verification methods. Lattice Semiconductor provides no warranty
philpem@0 18 ** regarding the use or functionality of this code.
philpem@0 19 **
philpem@0 20 ** --------------------------------------------------------------------
philpem@0 21 **
philpem@0 22 ** Lattice Semiconductor Corporation
philpem@0 23 ** 5555 NE Moore Court
philpem@0 24 ** Hillsboro, OR 97214
philpem@0 25 ** U.S.A
philpem@0 26 **
philpem@0 27 ** TEL: 1-800-Lattice (USA and Canada)
philpem@0 28 ** (503)268-8001 (other locations)
philpem@0 29 **
philpem@0 30 ** web: http://www.latticesemi.com
philpem@0 31 ** email: techsupport@latticesemi.com
philpem@0 32 **
philpem@0 33 ** --------------------------------------------------------------------------
philpem@0 34 **
philpem@0 35 ** Change History (Latest changes on top)
philpem@0 36 **
philpem@0 37 ** Ver Date Description
philpem@0 38 ** --------------------------------------------------------------------------
philpem@0 39 **
philpem@0 40 ** 3.1 Oct-23-2008 Updated macros to provide for
philpem@0 41 ** reading of the interrupt-mask register
philpem@0 42 ** and writing to the edge-capture register
philpem@0 43 ** Updated comments in the GPIO register
philpem@0 44 ** structure definition
philpem@0 45 ** 3.0 Mar-25-2008 Added Header
philpem@0 46 **
philpem@0 47 **
philpem@0 48 **---------------------------------------------------------------------------
philpem@0 49 *****************************************************************************/
philpem@0 50
philpem@0 51 #ifndef MICO32_MICOGPIO_HEADER_FILE
philpem@0 52 #define MICO32_MICOGPIO_HEADER_FILE
philpem@0 53
philpem@0 54 #include "MicoTypes.h"
philpem@0 55 #include "DDStructs.h"
philpem@0 56
philpem@0 57 /****************************************************************************
philpem@0 58 * Mico-GPIO driver does not provide any specific user-routine other than *
philpem@0 59 * linking it to GPIO services for lookup capability. *
philpem@0 60 *--------------------------------------------------------------------------*
philpem@0 61 * Mico GPIOs must be located in a non-cached region to use this driver *
philpem@0 62 ****************************************************************************/
philpem@0 63
philpem@0 64
philpem@0 65 #ifdef __cplusplus
philpem@0 66 extern "C"
philpem@0 67 {
philpem@0 68 #endif /* __cplusplus */
philpem@0 69
philpem@0 70 /*
philpem@0 71 *****************************************
philpem@0 72 *****************************************
philpem@0 73 GPIO REGISTER MAPPING
philpem@0 74 *****************************************
philpem@0 75 *****************************************
philpem@0 76 */
philpem@0 77 typedef struct st_MicoGPIO_t{
philpem@0 78 volatile unsigned int data; /* R/W:
philpem@0 79 R for in-only GPIO,
philpem@0 80 W for out-only GPIO,
philpem@0 81 R/W for tristates */
philpem@0 82 volatile unsigned int tristate; /* R/W:
philpem@0 83 tristate enable reg for
philpem@0 84 tristate GPIOs */
philpem@0 85 volatile unsigned int irqMask; /* R/W:
philpem@0 86 irq mask for interrupt-
philpem@0 87 enabled GPIOs */
philpem@0 88 volatile unsigned int edgeCapture; /* R/W:
philpem@0 89 applicable to GPIOs with
philpem@0 90 edge-capture ability */
philpem@0 91 }MicoGPIO_t;
philpem@0 92
philpem@0 93
philpem@0 94
philpem@0 95 /*
philpem@0 96 ********************************************
philpem@0 97 ********************************************
philpem@0 98 MACROS FOR ACCESSING GPIO REGISTERS
philpem@0 99 ********************************************
philpem@0 100 NOTE: FOR THE MACROS, THE FOLLOWING RULES
philpem@0 101 APPLY:
philpem@0 102 X is pointer to a valid MicoGPIOCtx_t structure
philpem@0 103 Y is unsigned int variable
philpem@0 104 */
philpem@0 105
philpem@0 106
philpem@0 107 /* reads data register */
philpem@0 108 #define MICO_GPIO_READ_DATA(X,Y) \
philpem@0 109 (Y)=((volatile MicoGPIO_t *)((X)->base))->data
philpem@0 110
philpem@0 111
philpem@0 112 /* writes data-register */
philpem@0 113 #define MICO_GPIO_WRITE_DATA(X,Y) \
philpem@0 114 ((volatile MicoGPIO_t *)((X)->base))->data=(Y)
philpem@0 115
philpem@0 116
philpem@0 117 /* reads tristate register */
philpem@0 118 #define MICO_GPIO_READ_TRISTATE(X,Y) \
philpem@0 119 (Y) = ((volatile MicoGPIO_t *)((X)->base))->tristate
philpem@0 120
philpem@0 121
philpem@0 122 /* writes tristate register */
philpem@0 123 #define MICO_GPIO_WRITE_TRISTATE(X,Y) \
philpem@0 124 ((volatile MicoGPIO_t *)((X)->base))->tristate = (Y)
philpem@0 125
philpem@0 126
philpem@0 127 /* reads irq-mask register */
philpem@0 128 #define MICO_GPIO_READ_IRQ_MASK(X,Y) \
philpem@0 129 (Y) = ((volatile MicoGPIO_t *)((X)->base))->irqMask
philpem@0 130
philpem@0 131
philpem@0 132 /* writes irq-mask register */
philpem@0 133 #define MICO_GPIO_WRITE_IRQ_MASK(X,Y) \
philpem@0 134 ((volatile MicoGPIO_t *)((X)->base))->irqMask = (Y)
philpem@0 135
philpem@0 136
philpem@0 137 /* reads edge-capture register */
philpem@0 138 #define MICO_GPIO_READ_EDGE_CAPTURE(X,Y) \
philpem@0 139 (Y) = ((volatile MicoGPIO_t *)((X)->base))->edgeCapture
philpem@0 140
philpem@0 141
philpem@0 142 /* writes edge-capture register */
philpem@0 143 #define MICO_GPIO_WRITE_EDGE_CAPTURE(X,Y) \
philpem@0 144 ((volatile MicoGPIO_t *)((X)->base))->edgeCapture = (Y)
philpem@0 145
philpem@0 146
philpem@0 147 /******************************************************************************
philpem@0 148 * functions *
philpem@0 149 ******************************************************************************/
philpem@0 150
philpem@0 151 /* initializes Mico32 GPIO peripheral */
philpem@0 152 void MicoGPIOInit( MicoGPIOCtx_t *ctx );
philpem@0 153
philpem@0 154
philpem@0 155 #ifdef __cplusplus
philpem@0 156 };
philpem@0 157 #endif /* __cplusplus */
philpem@0 158
philpem@0 159
philpem@0 160 #endif /*MICO32_MICOGPIO_HEADER_FILE */
philpem@0 161