Sat, 06 Aug 2011 01:43:24 +0100
Update to latest Lattice code dump (LM32 V3.8, GPIO V3.2)
Version : 3.2
Mod. Data : Jun 6, 2010
Changes Made : 1. Provide capability to read/write bytes (when GPIO larger than 8 bits wide)
2. Provide capability to use a 32-bit or 8-bit data bus on the WISHBONE slave port
3. Perform a big-endian to little-endian conversion in hardware
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 // ------------------------------------------------------------------
4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5 // ALL RIGHTS RESERVED
6 // ------------------------------------------------------------------
7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 //
10 // Permission:
11 //
12 // Lattice Semiconductor grants permission to use this code
13 // pursuant to the terms of the Lattice Semiconductor Corporation
14 // Open Source License Agreement.
15 //
16 // Disclaimer:
17 //
18 // Lattice Semiconductor provides no warranty regarding the use or
19 // functionality of this code. It is the user's responsibility to
20 // verify the user’s design for consistency and functionality through
21 // the use of formal verification methods.
22 //
23 // --------------------------------------------------------------------
24 //
25 // Lattice Semiconductor Corporation
26 // 5555 NE Moore Court
27 // Hillsboro, OR 97214
28 // U.S.A
29 //
30 // TEL: 1-800-Lattice (USA and Canada)
31 // 503-286-8001 (other locations)
32 //
33 // web: http://www.latticesemi.com/
34 // email: techsupport@latticesemi.com
35 //
36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // FILE DETAILS
39 // Project : GPIO for LM32
40 // File : tpio.v
41 // Title : Tri State IO control
42 // Dependencies : system_conf.v
43 // Description : Implements the logic to interface tri-state IO with
44 // Wishbone bus.
45 // =============================================================================
46 // REVISION HISTORY
47 // Version : 7.0
48 // Mod. Date : Jun 27, 2005
49 // Changes Made : Initial Creation
50 //
51 // Version : 7.0SP2, 3.0
52 // Mod. Date : 20 Nov. 2007
53 // Changes Made : Code clean up and add the BB for the inout port.
54 //
55 // Version : 3.1
56 // Mod. Date : 11 Oct. 2008
57 // Changes Made : Update the Edge Capture Register clean method
58 // Make IRQ Mask register readable
59 // =============================================================================
60 `ifndef TPIO_V
61 `define TPIO_V
62 `timescale 1ns/100 ps
63 `include "system_conf.v"
64 module TRI_PIO #(parameter DATA_WIDTH = 16,
65 parameter IRQ_MODE = 1,
66 parameter LEVEL = 0,
67 parameter EDGE = 1,
68 parameter POSE_EDGE_IRQ = 1,
69 parameter NEGE_EDGE_IRQ = 0,
70 parameter EITHER_EDGE_IRQ = 0)
71 (RST_I,
72 CLK_I,
73 DAT_I,
74 DAT_O,
75 PIO_IO,
76 IRQ_O,
77 PIO_TRI_WR_EN,
78 PIO_TRI_RE_EN,
79 PIO_DATA_RE_EN,
80 PIO_DATA_WR_EN,
81 IRQ_MASK_RE_EN,
82 IRQ_MASK_WR_EN,
83 EDGE_CAP_WR_EN);
85 parameter UDLY = 1;//user delay
87 input RST_I;
88 input CLK_I;
89 input DAT_I;
90 input PIO_TRI_RE_EN;
91 input PIO_TRI_WR_EN;
92 input PIO_DATA_RE_EN;
93 input PIO_DATA_WR_EN;
94 output DAT_O;
95 input IRQ_MASK_RE_EN;
96 input IRQ_MASK_WR_EN;
97 input EDGE_CAP_WR_EN;
98 output IRQ_O;
99 inout PIO_IO;
101 wire PIO_IO_I;
102 wire DAT_O;
103 wire IRQ_O;
104 reg PIO_DATA_O;
105 reg PIO_DATA_I;
106 reg PIO_TRI;
107 reg IRQ_MASK;
108 reg IRQ_TEMP;
109 reg EDGE_CAPTURE;
110 reg PIO_DATA_DLY;
112 always @(posedge CLK_I or posedge RST_I)
113 if (RST_I)
114 PIO_TRI <= #UDLY 0;
115 else if (PIO_TRI_WR_EN)
116 PIO_TRI <= #UDLY DAT_I;
118 always @(posedge CLK_I or posedge RST_I)
119 if (RST_I)
120 PIO_DATA_O <= #UDLY 0;
121 else if (PIO_DATA_WR_EN)
122 PIO_DATA_O <= #UDLY DAT_I;
124 always @(posedge CLK_I or posedge RST_I)
125 if (RST_I)
126 PIO_DATA_I <= #UDLY 0;
127 else if (PIO_DATA_RE_EN)
128 PIO_DATA_I <= #UDLY PIO_IO_I;
130 BB tpio_inst(.I(PIO_DATA_O), .T(~PIO_TRI), .O(PIO_IO_I), .B(PIO_IO));
131 assign DAT_O = PIO_TRI_RE_EN ? PIO_TRI :
132 IRQ_MASK_RE_EN ? IRQ_MASK : PIO_DATA_I;
134 //IRQ_MODE
136 generate
137 if (IRQ_MODE == 1) begin
138 //CONFIG THE IRQ_MASK REG.
139 always @(posedge CLK_I or posedge RST_I)
140 if (RST_I)
141 IRQ_MASK <= #UDLY 0;
142 else if (IRQ_MASK_WR_EN)
143 IRQ_MASK <= #UDLY DAT_I;
144 end
145 endgenerate
147 generate
148 if (IRQ_MODE == 1 && LEVEL == 1) begin
149 always @(posedge CLK_I or posedge RST_I)
150 if (RST_I)
151 IRQ_TEMP <= #UDLY 0;
152 else
153 IRQ_TEMP <= #UDLY PIO_IO_I & IRQ_MASK & ~PIO_TRI;//bit-and
154 assign IRQ_O = IRQ_TEMP;
155 end
156 else if (IRQ_MODE == 1 && EDGE == 1) begin
157 always @(posedge CLK_I or posedge RST_I)
158 if (RST_I)
159 PIO_DATA_DLY <= #UDLY 0;
160 else
161 PIO_DATA_DLY <= PIO_IO_I;
163 always @(posedge CLK_I or posedge RST_I)
164 if (RST_I)
165 EDGE_CAPTURE <= #UDLY 0;
166 else if ((PIO_IO_I & ~PIO_DATA_DLY & ~PIO_TRI) && POSE_EDGE_IRQ == 1)
167 EDGE_CAPTURE <= #UDLY PIO_IO_I & ~PIO_DATA_DLY;
168 else if ((~PIO_IO_I & PIO_DATA_DLY & ~PIO_TRI) && NEGE_EDGE_IRQ == 1)
169 EDGE_CAPTURE <= #UDLY ~PIO_IO_I & PIO_DATA_DLY;
170 else if ((PIO_IO_I & ~PIO_DATA_DLY & ~PIO_TRI) && EITHER_EDGE_IRQ == 1)
171 EDGE_CAPTURE <= #UDLY PIO_IO_I & ~PIO_DATA_DLY;
172 else if ((~PIO_IO_I & PIO_DATA_DLY & ~PIO_TRI) && EITHER_EDGE_IRQ == 1)
173 EDGE_CAPTURE <= #UDLY ~PIO_IO_I & PIO_DATA_DLY;
174 else if ( (~IRQ_MASK) & DAT_I & IRQ_MASK_WR_EN )
175 // interrupt mask's being set, so clear edge-capture
176 EDGE_CAPTURE <= #UDLY 0;
177 else if ( EDGE_CAP_WR_EN )
178 // user's writing to the edge-register, so update edge-capture
179 // register
180 EDGE_CAPTURE <= #UDLY EDGE_CAPTURE & DAT_I;
182 assign IRQ_O = |(EDGE_CAPTURE & IRQ_MASK);
183 end
184 else // IRQ_MODE ==0
185 assign IRQ_O = 0;
186 endgenerate
187 endmodule
188 `endif // TPIO_V