     1.1 diff -r 96badb38531d -r dd6f40c05963 wb_sdram.v
     1.2 --- a/wb_sdram.v	Tue Aug 10 17:36:00 2010 +0100
     1.3 +++ b/wb_sdram.v	Tue Aug 10 17:42:18 2010 +0100
     1.4 @@ -144,9 +144,10 @@
     1.5  localparam	ST_Test_Activate_Wait		= 32'd501;
     1.6  localparam	ST_Test_Read					= 32'd502;
     1.7  localparam	ST_Test_Read_Wait				= 32'd503;
     1.8 -localparam	ST_Test_Write					= 32'd504;
     1.9 -localparam	ST_Test_Precharge_All		= 32'd505;
    1.10 -localparam	ST_Test_Precharge_All_Wait	= 32'd506;
    1.11 +localparam	ST_Test_Read_Finish			= 32'd504;
    1.12 +localparam	ST_Test_Write					= 32'd505;
    1.13 +localparam	ST_Test_Precharge_All		= 32'd506;
    1.14 +localparam	ST_Test_Precharge_All_Wait	= 32'd507;
    1.15   
    1.16  reg [31:0] state;
    1.17  always @(posedge wb_clk_i) begin
    1.18 @@ -351,7 +352,7 @@
    1.19  					sdram_mode <= M_Read;
    1.20  					sdram_addr <= column_addr;
    1.21  					sdram_dqm <= 4'b0000;		// Allow data through (DQM = OE# = 1 to mask off, 0 to allow)
    1.22 -					timer <= 32'd3 - 32'd1;		// wait CAS# Latency (2 clock cycles)	---> TIMER HERE
    1.23 +					timer <= 32'd2 - 32'd1;		// wait CAS# Latency (2 clock cycles)	---> TIMER HERE
    1.24  					state <= ST_Test_Read_Wait;
    1.25  				end
    1.26  				
    1.27 @@ -360,10 +361,17 @@
    1.28  					sdram_mode <= M_Nop;
    1.29  					sdram_dqm <= 4'b1111;		// Disable SDRAM output buffers
    1.30  					if (timer == 32'd0) begin
    1.31 -						state <= ST_Test_Write;
    1.32 +						state <= ST_Test_Read_Finish;
    1.33  						// TODO: capture data locally
    1.34  					end
    1.35  				end
    1.36 +
    1.37 +			ST_Test_Read_Finish: begin
    1.38 +					// Additional NOP after read to avoid bus contention if next transaction is a write
    1.39 +					sdram_mode <= M_Nop;
    1.40 +					sdram_dqm <= 4'b1111;	// Disable SDRAM output buffers
    1.41 +					state <= ST_Test_Write;
    1.42 +				end
    1.43  			
    1.44  			ST_Test_Write: begin
    1.45  					// Write to SDRAM