Wed, 18 Aug 2010 14:17:42 +0100
comment cleanup
| wb_sdram.v | file | annotate | diff | revisions |
1.1 diff -r 275105a6a36b -r d39b0f302ca3 wb_sdram.v 1.2 --- a/wb_sdram.v Wed Aug 18 14:14:38 2010 +0100 1.3 +++ b/wb_sdram.v Wed Aug 18 14:17:42 2010 +0100 1.4 @@ -1,6 +1,10 @@ 1.5 /**************************************************************************** 1.6 + * WISHBONE SDRAM CONTROLLER MODULE / IP CORE 1.7 + * (C) 2010 Philip Pemberton. All Rights Reserved. 1.8 * 1.9 - * 1.10 + * This IP core provides a WISHBONE-compliant interface for most standard 1.11 + * SDR SDRAM ICs (e.g. the ISSI part on the Enterpoint Drigmorn2 and 1.12 + * Craignell2 boards). 1.13 ****************************************************************************/ 1.14 1.15 module wb_sdram #( 1.16 @@ -11,8 +15,8 @@ 1.17 parameter ROWADDR_BITS = 12, // Number of SDRAM Row Address bits 1.18 1.19 // Timer parameters 1.20 - parameter CAS_LATENCY = 3'd2, // CAS latency -- either 2 or 3 1.21 - parameter CLOCK_RATE = 25_000_000, // System clock frequency in Hz 1.22 + parameter CAS_LATENCY = 3'd2, // CAS latency -- either 2 or 3 1.23 + parameter CLOCK_RATE = 25_000_000, // System clock frequency in Hz 1.24 1.25 // SDRAM timings in nanoseconds 1.26 // Precharge to refresh/row activate command (same bank) -- Trp