1.1 diff -r da3d10af0711 -r 21521e62007f src/memory.c 1.2 --- a/src/memory.c Sat Nov 17 22:15:23 2012 +0000 1.3 +++ b/src/memory.c Sat Nov 17 22:26:53 2012 +0000 1.4 @@ -472,7 +472,9 @@ 1.5 handled = true; 1.6 break; 1.7 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2 1.8 - /*TODO: implement P5.1 second hard drive select*/ 1.9 + // MCR2 - UNIX PC Rev. P5.1 HDD head select b3 and potential HDD#2 select 1.10 + wd2010_write_reg(&state.hdc_ctx, UNIXPC_REG_MCR2, data); 1.11 + handled = true; 1.12 break; 1.13 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits 1.14 break; 1.15 @@ -546,8 +548,14 @@ 1.16 // I/O register space, zone A 1.17 switch (address & 0x0F0000) { 1.18 case 0x010000: // General Status Register 1.19 - ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); 1.20 - return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat; 1.21 + /* ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); */ 1.22 + if (bits == 32) { 1.23 + return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat; 1.24 + } else if (bits == 16) { 1.25 + return (uint16_t)state.genstat; 1.26 + } else { 1.27 + return (uint8_t)(state.genstat & 0xff); 1.28 + } 1.29 break; 1.30 case 0x030000: // Bus Status Register 0 1.31 ENFORCE_SIZE_R(bits, address, 16, "BSR0");