1.1 diff -r 976dfa068839 -r 2ef98ea1e944 src/main.c 1.2 --- a/src/main.c Mon Dec 06 08:27:05 2010 +0000 1.3 +++ b/src/main.c Mon Dec 06 08:27:21 2010 +0000 1.4 @@ -196,12 +196,13 @@ 1.5 * The 3B1 CPU runs at 10MHz, with DMA running at 1MHz and video refreshing at 1.6 * around 60Hz (???), with a 60Hz periodic interrupt. 1.7 */ 1.8 - const uint32_t TIMESLOT_FREQUENCY = 240; // Hz 1.9 + const uint32_t TIMESLOT_FREQUENCY = 1000;//240; // Hz 1.10 const uint32_t MILLISECS_PER_TIMESLOT = 1e3 / TIMESLOT_FREQUENCY; 1.11 const uint32_t CLOCKS_PER_60HZ = (10e6 / 60); 1.12 uint32_t next_timeslot = SDL_GetTicks() + MILLISECS_PER_TIMESLOT; 1.13 uint32_t clock_cycles = 0; 1.14 bool exitEmu = false; 1.15 + bool lastirq_fdc = false; 1.16 for (;;) { 1.17 // Run the CPU for however many cycles we need to. CPU core clock is 1.18 // 10MHz, and we're running at 240Hz/timeslot. Thus: 10e6/240 or 1.19 @@ -209,12 +210,10 @@ 1.20 clock_cycles += m68k_execute(10e6/TIMESLOT_FREQUENCY); 1.21 1.22 // Run the DMA engine 1.23 - // 1.24 - if (state.dmaen) { //((state.dma_count < 0x3fff) && state.dmaen) { 1.25 + if (state.dmaen) { 1.26 printf("DMA: copy addr=%08X count=%08X idmarw=%d dmarw=%d\n", state.dma_address, state.dma_count, state.idmarw, state.dma_reading); 1.27 if (state.dmaenb) { 1.28 state.dmaenb = false; 1.29 -// state.dma_address++; 1.30 state.dma_count++; 1.31 } 1.32 // DMA ready to go -- so do it. 1.33 @@ -227,7 +226,7 @@ 1.34 1.35 // Evidently we have more words to copy. Copy them. 1.36 if (!wd2797_get_drq(&state.fdc_ctx)) { 1.37 - printf("\tDMABAIL: no data! dmac=%04X dmaa=%04X\n", state.dma_count, state.dma_address); 1.38 +// printf("\tDMABAIL: no data! dmac=%04X dmaa=%04X\n", state.dma_count, state.dma_address); 1.39 // Bail out, no data available. Try again later. 1.40 // TODO: handle HDD controller too 1.41 break; 1.42 @@ -258,15 +257,20 @@ 1.43 1.44 // Turn off DMA engine if we finished this cycle 1.45 if (state.dma_count >= 0x4000) { 1.46 - printf("\tDMATRAN: transfer complete! dmaa=%06X, dmac=%04X\n", state.dma_address, state.dma_count); 1.47 +// printf("\tDMATRAN: transfer complete! dmaa=%06X, dmac=%04X\n", state.dma_address, state.dma_count); 1.48 state.dma_count = 0; 1.49 state.dmaen = false; 1.50 } 1.51 } 1.52 1.53 // Any interrupts? 1.54 - if (wd2797_get_irq(&state.fdc_ctx)) { 1.55 - m68k_set_irq(2); 1.56 + if (!lastirq_fdc) { 1.57 + if (wd2797_get_irq(&state.fdc_ctx)) { 1.58 + lastirq_fdc = true; 1.59 + m68k_set_irq(2); 1.60 + } else { 1.61 + lastirq_fdc = false; 1.62 + } 1.63 } else { 1.64 m68k_set_irq(0); 1.65 }