add Error Enable bit to gcr write handler

     1.1 diff -r e20f02519835 -r 4e1c29899aca src/memory.c
     1.2 --- a/src/memory.c	Fri Mar 04 00:41:52 2011 +0000
     1.3 +++ b/src/memory.c	Fri Mar 04 00:44:06 2011 +0000
     1.4 @@ -393,6 +393,10 @@
     1.5  					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
     1.6  						switch (address & 0x077000) {
     1.7  							case 0x040000:		// [ef][4c][08]xxx ==> EE
     1.8 +								// Error Enable. If =0, Level7 intrs and bus errors are masked.
     1.9 +								ENFORCE_SIZE_W(bits, address, 16, "EE");
    1.10 +								state.ee = ((data & 0x8000) == 0x8000);
    1.11 +								handled = true;
    1.12  								break;
    1.13  							case 0x041000:		// [ef][4c][19]xxx ==> PIE
    1.14  								ENFORCE_SIZE_W(bits, address, 16, "PIE");