1.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_monitor.v 1.2 --- a/lm32_monitor.v Sun Mar 06 21:14:43 2011 +0000 1.3 +++ b/lm32_monitor.v Sat Aug 06 00:02:46 2011 +0100 1.4 @@ -1,18 +1,39 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 +// ================================================================== 1.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.16 +// ------------------------------------------------------------------ 1.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.18 +// ALL RIGHTS RESERVED 1.19 +// ------------------------------------------------------------------ 1.20 +// 1.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.22 +// 1.23 +// Permission: 1.24 +// 1.25 +// Lattice Semiconductor grants permission to use this code 1.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.27 +// Open Source License Agreement. 1.28 +// 1.29 +// Disclaimer: 1.30 // 1.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.34 -// U.S.A email: techsupport@latticesemi.com 1.35 -// =============================================================================/ 1.36 +// Lattice Semiconductor provides no warranty regarding the use or 1.37 +// functionality of this code. It is the user's responsibility to 1.38 +// verify the user’s design for consistency and functionality through 1.39 +// the use of formal verification methods. 1.40 +// 1.41 +// -------------------------------------------------------------------- 1.42 +// 1.43 +// Lattice Semiconductor Corporation 1.44 +// 5555 NE Moore Court 1.45 +// Hillsboro, OR 97214 1.46 +// U.S.A 1.47 +// 1.48 +// TEL: 1-800-Lattice (USA and Canada) 1.49 +// 503-286-8001 (other locations) 1.50 +// 1.51 +// web: http://www.latticesemi.com/ 1.52 +// email: techsupport@latticesemi.com 1.53 +// 1.54 +// -------------------------------------------------------------------- 1.55 // FILE DETAILS 1.56 // Project : LatticeMico32 1.57 // File : lm32_monitor.v 1.58 @@ -123,10 +144,10 @@ 1.59 begin 1.60 if (rst_i == `TRUE) 1.61 begin 1.62 - write_enable <= `FALSE; 1.63 - MON_ACK_O <= `FALSE; 1.64 - MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 1.65 - state <= 2'b00; 1.66 + write_enable <= #1 `FALSE; 1.67 + MON_ACK_O <= #1 `FALSE; 1.68 + MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}}; 1.69 + state <= #1 2'b00; 1.70 end 1.71 else 1.72 begin 1.73 @@ -134,33 +155,33 @@ 1.74 2'b01: 1.75 begin 1.76 // Output read data to Wishbone 1.77 - MON_ACK_O <= `TRUE; 1.78 - MON_DAT_O <= data; 1.79 + MON_ACK_O <= #1 `TRUE; 1.80 + MON_DAT_O <= #1 data; 1.81 // Sub-word writes are performed using read-modify-write 1.82 // as the Lattice EBRs don't support byte enables 1.83 if (MON_WE_I == `TRUE) 1.84 - write_enable <= `TRUE; 1.85 - write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0]; 1.86 - write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8]; 1.87 - write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16]; 1.88 - write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24]; 1.89 - state <= 2'b10; 1.90 + write_enable <= #1 `TRUE; 1.91 + write_data[7:0] <= #1 MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0]; 1.92 + write_data[15:8] <= #1 MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8]; 1.93 + write_data[23:16] <= #1 MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16]; 1.94 + write_data[31:24] <= #1 MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24]; 1.95 + state <= #1 2'b10; 1.96 end 1.97 2'b10: 1.98 begin 1.99 // Wishbone access occurs in this cycle 1.100 - write_enable <= `FALSE; 1.101 - MON_ACK_O <= `FALSE; 1.102 - MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 1.103 - state <= 2'b00; 1.104 + write_enable <= #1 `FALSE; 1.105 + MON_ACK_O <= #1 `FALSE; 1.106 + MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}}; 1.107 + state <= #1 2'b00; 1.108 end 1.109 default: 1.110 begin 1.111 - write_enable <= `FALSE; 1.112 - MON_ACK_O <= `FALSE; 1.113 + write_enable <= #1 `FALSE; 1.114 + MON_ACK_O <= #1 `FALSE; 1.115 // Wait for a Wishbone access 1.116 if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE)) 1.117 - state <= 2'b01; 1.118 + state <= #1 2'b01; 1.119 end 1.120 endcase 1.121 end