1.1 diff -r 252df75c8f67 -r c336e674a37e lm32_icache.v 1.2 --- a/lm32_icache.v Sun Mar 06 21:17:31 2011 +0000 1.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 1.4 @@ -1,494 +0,0 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 -// 1.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 -// U.S.A email: techsupport@latticesemi.com 1.19 -// =============================================================================/ 1.20 -// FILE DETAILS 1.21 -// Project : LatticeMico32 1.22 -// File : lm32_icache.v 1.23 -// Title : Instruction cache 1.24 -// Dependencies : lm32_include.v 1.25 -// 1.26 -// Version 3.5 1.27 -// 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory 1.28 -// cause segmentation fault due to incorrect fetches. 1.29 -// 1.30 -// Version 3.1 1.31 -// 1. Feature: Support for user-selected resource usage when implementing 1.32 -// cache memory. Additional parameters must be defined when invoking module 1.33 -// lm32_ram. Instruction cache miss mechanism is dependent on branch 1.34 -// prediction being performed in D stage of pipeline. 1.35 -// 1.36 -// Version 7.0SP2, 3.0 1.37 -// No change 1.38 -// ============================================================================= 1.39 - 1.40 -`include "lm32_include.v" 1.41 - 1.42 -`ifdef CFG_ICACHE_ENABLED 1.43 - 1.44 -`define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb 1.45 -`define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb 1.46 -`define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb 1.47 -`define LM32_IC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb 1.48 - 1.49 -`define LM32_IC_TMEM_ADDR_WIDTH addr_set_width 1.50 -`define LM32_IC_TMEM_ADDR_RNG (`LM32_IC_TMEM_ADDR_WIDTH-1):0 1.51 -`define LM32_IC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width) 1.52 -`define LM32_IC_DMEM_ADDR_RNG (`LM32_IC_DMEM_ADDR_WIDTH-1):0 1.53 - 1.54 -`define LM32_IC_TAGS_WIDTH (addr_tag_width+1) 1.55 -`define LM32_IC_TAGS_RNG (`LM32_IC_TAGS_WIDTH-1):0 1.56 -`define LM32_IC_TAGS_TAG_RNG (`LM32_IC_TAGS_WIDTH-1):1 1.57 -`define LM32_IC_TAGS_VALID_RNG 0 1.58 - 1.59 -`define LM32_IC_STATE_RNG 3:0 1.60 -`define LM32_IC_STATE_FLUSH_INIT 4'b0001 1.61 -`define LM32_IC_STATE_FLUSH 4'b0010 1.62 -`define LM32_IC_STATE_CHECK 4'b0100 1.63 -`define LM32_IC_STATE_REFILL 4'b1000 1.64 - 1.65 -///////////////////////////////////////////////////// 1.66 -// Module interface 1.67 -///////////////////////////////////////////////////// 1.68 - 1.69 -module lm32_icache ( 1.70 - // ----- Inputs ----- 1.71 - clk_i, 1.72 - rst_i, 1.73 - stall_a, 1.74 - stall_f, 1.75 - address_a, 1.76 - address_f, 1.77 - read_enable_f, 1.78 - refill_ready, 1.79 - refill_data, 1.80 - iflush, 1.81 -`ifdef CFG_IROM_ENABLED 1.82 - select_f, 1.83 -`endif 1.84 - valid_d, 1.85 - branch_predict_taken_d, 1.86 - // ----- Outputs ----- 1.87 - stall_request, 1.88 - restart_request, 1.89 - refill_request, 1.90 - refill_address, 1.91 - refilling, 1.92 - inst 1.93 - ); 1.94 - 1.95 -///////////////////////////////////////////////////// 1.96 -// Parameters 1.97 -///////////////////////////////////////////////////// 1.98 - 1.99 -parameter associativity = 1; // Associativity of the cache (Number of ways) 1.100 -parameter sets = 512; // Number of sets 1.101 -parameter bytes_per_line = 16; // Number of bytes per cache line 1.102 -parameter base_address = 0; // Base address of cachable memory 1.103 -parameter limit = 0; // Limit (highest address) of cachable memory 1.104 - 1.105 -localparam addr_offset_width = clogb2(bytes_per_line)-1-2; 1.106 -localparam addr_set_width = clogb2(sets)-1; 1.107 -localparam addr_offset_lsb = 2; 1.108 -localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 1.109 -localparam addr_set_lsb = (addr_offset_msb+1); 1.110 -localparam addr_set_msb = (addr_set_lsb+addr_set_width-1); 1.111 -localparam addr_tag_lsb = (addr_set_msb+1); 1.112 -localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1; 1.113 -localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1); 1.114 - 1.115 -///////////////////////////////////////////////////// 1.116 -// Inputs 1.117 -///////////////////////////////////////////////////// 1.118 - 1.119 -input clk_i; // Clock 1.120 -input rst_i; // Reset 1.121 - 1.122 -input stall_a; // Stall instruction in A stage 1.123 -input stall_f; // Stall instruction in F stage 1.124 - 1.125 -input valid_d; // Valid instruction in D stage 1.126 -input branch_predict_taken_d; // Instruction in D stage is a branch and is predicted taken 1.127 - 1.128 -input [`LM32_PC_RNG] address_a; // Address of instruction in A stage 1.129 -input [`LM32_PC_RNG] address_f; // Address of instruction in F stage 1.130 -input read_enable_f; // Indicates if cache access is valid 1.131 - 1.132 -input refill_ready; // Next word of refill data is ready 1.133 -input [`LM32_INSTRUCTION_RNG] refill_data; // Data to refill the cache with 1.134 - 1.135 -input iflush; // Flush the cache 1.136 -`ifdef CFG_IROM_ENABLED 1.137 -input select_f; // Instruction in F stage is mapped through instruction cache 1.138 -`endif 1.139 - 1.140 -///////////////////////////////////////////////////// 1.141 -// Outputs 1.142 -///////////////////////////////////////////////////// 1.143 - 1.144 -output stall_request; // Request to stall the pipeline 1.145 -wire stall_request; 1.146 -output restart_request; // Request to restart instruction that caused the cache miss 1.147 -reg restart_request; 1.148 -output refill_request; // Request to refill a cache line 1.149 -wire refill_request; 1.150 -output [`LM32_PC_RNG] refill_address; // Base address of cache refill 1.151 -reg [`LM32_PC_RNG] refill_address; 1.152 -output refilling; // Indicates the instruction cache is currently refilling 1.153 -reg refilling; 1.154 -output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache 1.155 -wire [`LM32_INSTRUCTION_RNG] inst; 1.156 - 1.157 -///////////////////////////////////////////////////// 1.158 -// Internal nets and registers 1.159 -///////////////////////////////////////////////////// 1.160 - 1.161 -wire enable; 1.162 -wire [0:associativity-1] way_mem_we; 1.163 -wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1]; 1.164 -wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1]; 1.165 -wire [0:associativity-1] way_valid; 1.166 -wire [0:associativity-1] way_match; 1.167 -wire miss; 1.168 - 1.169 -wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address; 1.170 -wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address; 1.171 -wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address; 1.172 -wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address; 1.173 -wire [`LM32_IC_TAGS_RNG] tmem_write_data; 1.174 - 1.175 -reg [`LM32_IC_STATE_RNG] state; 1.176 -wire flushing; 1.177 -wire check; 1.178 -wire refill; 1.179 - 1.180 -reg [associativity-1:0] refill_way_select; 1.181 -reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset; 1.182 -wire last_refill; 1.183 -reg [`LM32_IC_TMEM_ADDR_RNG] flush_set; 1.184 - 1.185 -genvar i; 1.186 - 1.187 -///////////////////////////////////////////////////// 1.188 -// Functions 1.189 -///////////////////////////////////////////////////// 1.190 - 1.191 -`include "lm32_functions.v" 1.192 - 1.193 -///////////////////////////////////////////////////// 1.194 -// Instantiations 1.195 -///////////////////////////////////////////////////// 1.196 - 1.197 - generate 1.198 - for (i = 0; i < associativity; i = i + 1) 1.199 - begin : memories 1.200 - 1.201 - lm32_ram 1.202 - #( 1.203 - // ----- Parameters ------- 1.204 - .data_width (32), 1.205 - .address_width (`LM32_IC_DMEM_ADDR_WIDTH) 1.206 -`ifdef PLATFORM_LATTICE 1.207 - , 1.208 - `ifdef CFG_ICACHE_DAT_USE_DP_TRUE 1.209 - .RAM_IMPLEMENTATION ("EBR"), 1.210 - .RAM_TYPE ("RAM_DP_TRUE") 1.211 - `else 1.212 - `ifdef CFG_ICACHE_DAT_USE_DP 1.213 - .RAM_IMPLEMENTATION ("EBR"), 1.214 - .RAM_TYPE ("RAM_DP") 1.215 - `else 1.216 - `ifdef CFG_ICACHE_DAT_USE_SLICE 1.217 - .RAM_IMPLEMENTATION ("SLICE") 1.218 - `else 1.219 - .RAM_IMPLEMENTATION ("AUTO") 1.220 - `endif 1.221 - `endif 1.222 - `endif 1.223 -`endif 1.224 - ) 1.225 - way_0_data_ram 1.226 - ( 1.227 - // ----- Inputs ------- 1.228 - .read_clk (clk_i), 1.229 - .write_clk (clk_i), 1.230 - .reset (rst_i), 1.231 - .read_address (dmem_read_address), 1.232 - .enable_read (enable), 1.233 - .write_address (dmem_write_address), 1.234 - .enable_write (`TRUE), 1.235 - .write_enable (way_mem_we[i]), 1.236 - .write_data (refill_data), 1.237 - // ----- Outputs ------- 1.238 - .read_data (way_data[i]) 1.239 - ); 1.240 - 1.241 - lm32_ram 1.242 - #( 1.243 - // ----- Parameters ------- 1.244 - .data_width (`LM32_IC_TAGS_WIDTH), 1.245 - .address_width (`LM32_IC_TMEM_ADDR_WIDTH) 1.246 -`ifdef PLATFORM_LATTICE 1.247 - , 1.248 - `ifdef CFG_ICACHE_DAT_USE_DP_TRUE 1.249 - .RAM_IMPLEMENTATION ("EBR"), 1.250 - .RAM_TYPE ("RAM_DP_TRUE") 1.251 - `else 1.252 - `ifdef CFG_ICACHE_DAT_USE_DP 1.253 - .RAM_IMPLEMENTATION ("EBR"), 1.254 - .RAM_TYPE ("RAM_DP") 1.255 - `else 1.256 - `ifdef CFG_ICACHE_DAT_USE_SLICE 1.257 - .RAM_IMPLEMENTATION ("SLICE") 1.258 - `else 1.259 - .RAM_IMPLEMENTATION ("AUTO") 1.260 - `endif 1.261 - `endif 1.262 - `endif 1.263 -`endif 1.264 - ) 1.265 - way_0_tag_ram 1.266 - ( 1.267 - // ----- Inputs ------- 1.268 - .read_clk (clk_i), 1.269 - .write_clk (clk_i), 1.270 - .reset (rst_i), 1.271 - .read_address (tmem_read_address), 1.272 - .enable_read (enable), 1.273 - .write_address (tmem_write_address), 1.274 - .enable_write (`TRUE), 1.275 - .write_enable (way_mem_we[i] | flushing), 1.276 - .write_data (tmem_write_data), 1.277 - // ----- Outputs ------- 1.278 - .read_data ({way_tag[i], way_valid[i]}) 1.279 - ); 1.280 - 1.281 - end 1.282 -endgenerate 1.283 - 1.284 -///////////////////////////////////////////////////// 1.285 -// Combinational logic 1.286 -///////////////////////////////////////////////////// 1.287 - 1.288 -// Compute which ways in the cache match the address address being read 1.289 -generate 1.290 - for (i = 0; i < associativity; i = i + 1) 1.291 - begin : match 1.292 -assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE}); 1.293 - end 1.294 -endgenerate 1.295 - 1.296 -// Select data from way that matched the address being read 1.297 -generate 1.298 - if (associativity == 1) 1.299 - begin : inst_1 1.300 -assign inst = way_match[0] ? way_data[0] : 32'b0; 1.301 - end 1.302 - else if (associativity == 2) 1.303 - begin : inst_2 1.304 -assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0); 1.305 - end 1.306 -endgenerate 1.307 - 1.308 -// Compute address to use to index into the data memories 1.309 -generate 1.310 - if (bytes_per_line > 4) 1.311 -assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset}; 1.312 - else 1.313 -assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG]; 1.314 -endgenerate 1.315 - 1.316 -assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG]; 1.317 - 1.318 -// Compute address to use to index into the tag memories 1.319 -assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG]; 1.320 -assign tmem_write_address = flushing 1.321 - ? flush_set 1.322 - : refill_address[`LM32_IC_ADDR_SET_RNG]; 1.323 - 1.324 -// Compute signal to indicate when we are on the last refill accesses 1.325 -generate 1.326 - if (bytes_per_line > 4) 1.327 -assign last_refill = refill_offset == {addr_offset_width{1'b1}}; 1.328 - else 1.329 -assign last_refill = `TRUE; 1.330 -endgenerate 1.331 - 1.332 -// Compute data and tag memory access enable 1.333 -assign enable = (stall_a == `FALSE); 1.334 - 1.335 -// Compute data and tag memory write enables 1.336 -generate 1.337 - if (associativity == 1) 1.338 - begin : we_1 1.339 -assign way_mem_we[0] = (refill_ready == `TRUE); 1.340 - end 1.341 - else 1.342 - begin : we_2 1.343 -assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE); 1.344 -assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE); 1.345 - end 1.346 -endgenerate 1.347 - 1.348 -// On the last refill cycle set the valid bit, for all other writes it should be cleared 1.349 -assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing; 1.350 -assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG]; 1.351 - 1.352 -// Signals that indicate which state we are in 1.353 -assign flushing = |state[1:0]; 1.354 -assign check = state[2]; 1.355 -assign refill = state[3]; 1.356 - 1.357 -assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d); 1.358 -assign stall_request = (check == `FALSE); 1.359 -assign refill_request = (refill == `TRUE); 1.360 - 1.361 -///////////////////////////////////////////////////// 1.362 -// Sequential logic 1.363 -///////////////////////////////////////////////////// 1.364 - 1.365 -// Record way selected for replacement on a cache miss 1.366 -generate 1.367 - if (associativity >= 2) 1.368 - begin : way_select 1.369 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.370 -begin 1.371 - if (rst_i == `TRUE) 1.372 - refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 1.373 - else 1.374 - begin 1.375 - if (miss == `TRUE) 1.376 - refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 1.377 - end 1.378 -end 1.379 - end 1.380 -endgenerate 1.381 - 1.382 -// Record whether we are refilling 1.383 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.384 -begin 1.385 - if (rst_i == `TRUE) 1.386 - refilling <= `FALSE; 1.387 - else 1.388 - refilling <= refill; 1.389 -end 1.390 - 1.391 -// Instruction cache control FSM 1.392 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.393 -begin 1.394 - if (rst_i == `TRUE) 1.395 - begin 1.396 - state <= `LM32_IC_STATE_FLUSH_INIT; 1.397 - flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 1.398 - refill_address <= {`LM32_PC_WIDTH{1'bx}}; 1.399 - restart_request <= `FALSE; 1.400 - end 1.401 - else 1.402 - begin 1.403 - case (state) 1.404 - 1.405 - // Flush the cache for the first time after reset 1.406 - `LM32_IC_STATE_FLUSH_INIT: 1.407 - begin 1.408 - if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 1.409 - state <= `LM32_IC_STATE_CHECK; 1.410 - flush_set <= flush_set - 1'b1; 1.411 - end 1.412 - 1.413 - // Flush the cache in response to an write to the ICC CSR 1.414 - `LM32_IC_STATE_FLUSH: 1.415 - begin 1.416 - if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 1.417 -`ifdef CFG_IROM_ENABLED 1.418 - if (select_f) 1.419 - state <= `LM32_IC_STATE_REFILL; 1.420 - else 1.421 -`endif 1.422 - state <= `LM32_IC_STATE_CHECK; 1.423 - 1.424 - flush_set <= flush_set - 1'b1; 1.425 - end 1.426 - 1.427 - // Check for cache misses 1.428 - `LM32_IC_STATE_CHECK: 1.429 - begin 1.430 - if (stall_a == `FALSE) 1.431 - restart_request <= `FALSE; 1.432 - if (iflush == `TRUE) 1.433 - begin 1.434 - refill_address <= address_f; 1.435 - state <= `LM32_IC_STATE_FLUSH; 1.436 - end 1.437 - else if (miss == `TRUE) 1.438 - begin 1.439 - refill_address <= address_f; 1.440 - state <= `LM32_IC_STATE_REFILL; 1.441 - end 1.442 - end 1.443 - 1.444 - // Refill a cache line 1.445 - `LM32_IC_STATE_REFILL: 1.446 - begin 1.447 - if (refill_ready == `TRUE) 1.448 - begin 1.449 - if (last_refill == `TRUE) 1.450 - begin 1.451 - restart_request <= `TRUE; 1.452 - state <= `LM32_IC_STATE_CHECK; 1.453 - end 1.454 - end 1.455 - end 1.456 - 1.457 - endcase 1.458 - end 1.459 -end 1.460 - 1.461 -generate 1.462 - if (bytes_per_line > 4) 1.463 - begin 1.464 -// Refill offset 1.465 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.466 -begin 1.467 - if (rst_i == `TRUE) 1.468 - refill_offset <= {addr_offset_width{1'b0}}; 1.469 - else 1.470 - begin 1.471 - case (state) 1.472 - 1.473 - // Check for cache misses 1.474 - `LM32_IC_STATE_CHECK: 1.475 - begin 1.476 - if (iflush == `TRUE) 1.477 - refill_offset <= {addr_offset_width{1'b0}}; 1.478 - else if (miss == `TRUE) 1.479 - refill_offset <= {addr_offset_width{1'b0}}; 1.480 - end 1.481 - 1.482 - // Refill a cache line 1.483 - `LM32_IC_STATE_REFILL: 1.484 - begin 1.485 - if (refill_ready == `TRUE) 1.486 - refill_offset <= refill_offset + 1'b1; 1.487 - end 1.488 - 1.489 - endcase 1.490 - end 1.491 -end 1.492 - end 1.493 -endgenerate 1.494 - 1.495 -endmodule 1.496 - 1.497 -`endif 1.498 -