1.1 diff -r 252df75c8f67 -r c336e674a37e lm32_include.v 1.2 --- a/lm32_include.v Sun Mar 06 21:17:31 2011 +0000 1.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 1.4 @@ -1,368 +0,0 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 -// 1.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 -// U.S.A email: techsupport@latticesemi.com 1.19 -// =============================================================================/ 1.20 -// FILE DETAILS 1.21 -// Project : LatticeMico32 1.22 -// File : lm32_include.v 1.23 -// Title : CPU global macros 1.24 -// Version : 6.1.17 1.25 -// : Initial Release 1.26 -// Version : 7.0SP2, 3.0 1.27 -// : No Change 1.28 -// Version : 3.1 1.29 -// : No Change 1.30 -// Version : 3.2 1.31 -// : No Change 1.32 -// Version : 3.3 1.33 -// : Support for extended configuration register 1.34 -// ============================================================================= 1.35 - 1.36 -`ifdef LM32_INCLUDE_V 1.37 -`else 1.38 -`define LM32_INCLUDE_V 1.39 - 1.40 -// 1.41 -// Common configuration options 1.42 -// 1.43 - 1.44 -`define CFG_EBA_RESET 32'h00000000 1.45 -`define CFG_DEBA_RESET 32'h10000000 1.46 - 1.47 -`define CFG_PL_MULTIPLY_ENABLED 1.48 -`define CFG_PL_BARREL_SHIFT_ENABLED 1.49 -`define CFG_SIGN_EXTEND_ENABLED 1.50 -`define CFG_MC_DIVIDE_ENABLED 1.51 -`define CFG_EBR_POSEDGE_REGISTER_FILE 1.52 - 1.53 -// [found by Milkymist dev'rs] 1.54 -// Bug in Xst: 1.55 -// CFG_ICACHE_ASSOCIATIVITY=2 => works in most cases (random crash on complex software) 1.56 -// CFG_ICACHE_ASSOCIATIVITY=1 => disaster, CPU will not work at all 1.57 -// Works 100% OK with expensive synthesizers. 1.58 -`define CFG_ICACHE_ENABLED 1.59 -`define CFG_ICACHE_ASSOCIATIVITY 1 1.60 -`define CFG_ICACHE_SETS 256 1.61 -`define CFG_ICACHE_BYTES_PER_LINE 16 1.62 -`define CFG_ICACHE_BASE_ADDRESS 32'h0 1.63 -`define CFG_ICACHE_LIMIT 32'h7FFF_FFFF 1.64 - 1.65 -`define CFG_DCACHE_ENABLED 1.66 -`define CFG_DCACHE_ASSOCIATIVITY 1 1.67 -`define CFG_DCACHE_SETS 256 1.68 -`define CFG_DCACHE_BYTES_PER_LINE 16 1.69 -`define CFG_DCACHE_BASE_ADDRESS 32'h0 1.70 -`define CFG_DCACHE_LIMIT 32'h0FFF_FFFF 1.71 - 1.72 -// Enable Debugging 1.73 -//`define CFG_JTAG_ENABLED 1.74 -//`define CFG_JTAG_UART_ENABLED 1.75 -//`define CFG_DEBUG_ENABLED 1.76 -//`define CFG_HW_DEBUG_ENABLED 1.77 -//`define CFG_ROM_DEBUG_ENABLED 1.78 -//`define CFG_BREAKPOINTS 32'h0 1.79 -//`define CFG_WATCHPOINTS 32'h0 1.80 - 1.81 -// 1.82 -// End of common configuration options 1.83 -// 1.84 - 1.85 -`ifdef TRUE 1.86 -`else 1.87 -`define TRUE 1'b1 1.88 -`define FALSE 1'b0 1.89 -`define TRUE_N 1'b0 1.90 -`define FALSE_N 1'b1 1.91 -`endif 1.92 - 1.93 -// Wishbone configuration 1.94 -`define CFG_IWB_ENABLED 1.95 -`define CFG_DWB_ENABLED 1.96 - 1.97 -// Data-path width 1.98 -`define LM32_WORD_WIDTH 32 1.99 -`define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0 1.100 -`define LM32_SHIFT_WIDTH 5 1.101 -`define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0 1.102 -`define LM32_BYTE_SELECT_WIDTH 4 1.103 -`define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0 1.104 - 1.105 -// Register file size 1.106 -`define LM32_REGISTERS 32 1.107 -`define LM32_REG_IDX_WIDTH 5 1.108 -`define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0 1.109 - 1.110 -// Standard register numbers 1.111 -`define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29 1.112 -`define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30 1.113 -`define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31 1.114 - 1.115 -// Range of Program Counter. Two LSBs are always 0. 1.116 -// `ifdef CFG_ICACHE_ENABLED 1.117 -// `define LM32_PC_WIDTH (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2) 1.118 -// `else 1.119 -// `ifdef CFG_IWB_ENABLED 1.120 -`define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2) 1.121 -// `else 1.122 -// `define LM32_PC_WIDTH `LM32_IROM_ADDRESS_WIDTH 1.123 -// `endif 1.124 -// `endif 1.125 -`define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2 1.126 - 1.127 -// Range of an instruction 1.128 -`define LM32_INSTRUCTION_WIDTH 32 1.129 -`define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0 1.130 - 1.131 -// Adder operation 1.132 -`define LM32_ADDER_OP_ADD 1'b0 1.133 -`define LM32_ADDER_OP_SUBTRACT 1'b1 1.134 - 1.135 -// Shift direction 1.136 -`define LM32_SHIFT_OP_RIGHT 1'b0 1.137 -`define LM32_SHIFT_OP_LEFT 1'b1 1.138 - 1.139 -// Bus errors 1.140 -//`define CFG_BUS_ERRORS_ENABLED 1.141 - 1.142 -// Derive macro that indicates whether we have single-stepping or not 1.143 -`ifdef CFG_ROM_DEBUG_ENABLED 1.144 -`define LM32_SINGLE_STEP_ENABLED 1.145 -`else 1.146 -`ifdef CFG_HW_DEBUG_ENABLED 1.147 -`define LM32_SINGLE_STEP_ENABLED 1.148 -`endif 1.149 -`endif 1.150 - 1.151 -// Derive macro that indicates whether JTAG interface is required 1.152 -`ifdef CFG_JTAG_UART_ENABLED 1.153 -`define LM32_JTAG_ENABLED 1.154 -`else 1.155 -`ifdef CFG_DEBUG_ENABLED 1.156 -`define LM32_JTAG_ENABLED 1.157 -`else 1.158 -`endif 1.159 -`endif 1.160 - 1.161 -// Derive macro that indicates whether we have a barrel-shifter or not 1.162 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.163 -`define LM32_BARREL_SHIFT_ENABLED 1.164 -`else // CFG_PL_BARREL_SHIFT_ENABLED 1.165 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.166 -`define LM32_BARREL_SHIFT_ENABLED 1.167 -`else 1.168 -`define LM32_NO_BARREL_SHIFT 1.169 -`endif 1.170 -`endif // CFG_PL_BARREL_SHIFT_ENABLED 1.171 - 1.172 -// Derive macro that indicates whether we have a multiplier or not 1.173 -`ifdef CFG_PL_MULTIPLY_ENABLED 1.174 -`define LM32_MULTIPLY_ENABLED 1.175 -`else 1.176 -`ifdef CFG_MC_MULTIPLY_ENABLED 1.177 -`define LM32_MULTIPLY_ENABLED 1.178 -`endif 1.179 -`endif 1.180 - 1.181 -// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required 1.182 -`ifdef CFG_MC_DIVIDE_ENABLED 1.183 -`define LM32_MC_ARITHMETIC_ENABLED 1.184 -`endif 1.185 -`ifdef CFG_MC_MULTIPLY_ENABLED 1.186 -`define LM32_MC_ARITHMETIC_ENABLED 1.187 -`endif 1.188 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.189 -`define LM32_MC_ARITHMETIC_ENABLED 1.190 -`endif 1.191 - 1.192 -// Derive macro that indicates if we are using an EBR register file 1.193 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.194 -`define LM32_EBR_REGISTER_FILE 1.195 -`endif 1.196 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 1.197 -`define LM32_EBR_REGISTER_FILE 1.198 -`endif 1.199 - 1.200 -// Revision number 1.201 -`define LM32_REVISION 6'h02 1.202 - 1.203 -// Logical operations - Function encoded directly in instruction 1.204 -`define LM32_LOGIC_OP_RNG 3:0 1.205 - 1.206 -// Conditions for conditional branches 1.207 -`define LM32_CONDITION_WIDTH 3 1.208 -`define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0 1.209 -`define LM32_CONDITION_E 3'b001 1.210 -`define LM32_CONDITION_G 3'b010 1.211 -`define LM32_CONDITION_GE 3'b011 1.212 -`define LM32_CONDITION_GEU 3'b100 1.213 -`define LM32_CONDITION_GU 3'b101 1.214 -`define LM32_CONDITION_NE 3'b111 1.215 -`define LM32_CONDITION_U1 3'b000 1.216 -`define LM32_CONDITION_U2 3'b110 1.217 - 1.218 -// Size of load or store instruction - Encoding corresponds to opcode 1.219 -`define LM32_SIZE_WIDTH 2 1.220 -`define LM32_SIZE_RNG 1:0 1.221 -`define LM32_SIZE_BYTE 2'b00 1.222 -`define LM32_SIZE_HWORD 2'b11 1.223 -`define LM32_SIZE_WORD 2'b10 1.224 -`define LM32_ADDRESS_LSBS_WIDTH 2 1.225 - 1.226 -// Width and range of a CSR index 1.227 -`ifdef CFG_DEBUG_ENABLED 1.228 -`define LM32_CSR_WIDTH 5 1.229 -`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 1.230 -`else 1.231 -`ifdef CFG_JTAG_ENABLED 1.232 -`define LM32_CSR_WIDTH 4 1.233 -`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 1.234 -`else 1.235 -`define LM32_CSR_WIDTH 3 1.236 -`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 1.237 -`endif 1.238 -`endif 1.239 - 1.240 -// CSR indices 1.241 -`define LM32_CSR_IE `LM32_CSR_WIDTH'h0 1.242 -`define LM32_CSR_IM `LM32_CSR_WIDTH'h1 1.243 -`define LM32_CSR_IP `LM32_CSR_WIDTH'h2 1.244 -`define LM32_CSR_ICC `LM32_CSR_WIDTH'h3 1.245 -`define LM32_CSR_DCC `LM32_CSR_WIDTH'h4 1.246 -`define LM32_CSR_CC `LM32_CSR_WIDTH'h5 1.247 -`define LM32_CSR_CFG `LM32_CSR_WIDTH'h6 1.248 -`define LM32_CSR_EBA `LM32_CSR_WIDTH'h7 1.249 -`ifdef CFG_DEBUG_ENABLED 1.250 -`define LM32_CSR_DC `LM32_CSR_WIDTH'h8 1.251 -`define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9 1.252 -`endif 1.253 -`define LM32_CSR_CFG2 `LM32_CSR_WIDTH'ha 1.254 -`ifdef CFG_JTAG_ENABLED 1.255 -`define LM32_CSR_JTX `LM32_CSR_WIDTH'he 1.256 -`define LM32_CSR_JRX `LM32_CSR_WIDTH'hf 1.257 -`endif 1.258 -`ifdef CFG_DEBUG_ENABLED 1.259 -`define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10 1.260 -`define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11 1.261 -`define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12 1.262 -`define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13 1.263 -`define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18 1.264 -`define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19 1.265 -`define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a 1.266 -`define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b 1.267 -`endif 1.268 - 1.269 -// Values for WPC CSR 1.270 -`define LM32_WPC_C_RNG 1:0 1.271 -`define LM32_WPC_C_DISABLED 2'b00 1.272 -`define LM32_WPC_C_READ 2'b01 1.273 -`define LM32_WPC_C_WRITE 2'b10 1.274 -`define LM32_WPC_C_READ_WRITE 2'b11 1.275 - 1.276 -// Exception IDs 1.277 -`define LM32_EID_WIDTH 3 1.278 -`define LM32_EID_RNG (`LM32_EID_WIDTH-1):0 1.279 -`define LM32_EID_RESET 3'h0 1.280 -`define LM32_EID_BREAKPOINT 3'd1 1.281 -`define LM32_EID_INST_BUS_ERROR 3'h2 1.282 -`define LM32_EID_WATCHPOINT 3'd3 1.283 -`define LM32_EID_DATA_BUS_ERROR 3'h4 1.284 -`define LM32_EID_DIVIDE_BY_ZERO 3'h5 1.285 -`define LM32_EID_INTERRUPT 3'h6 1.286 -`define LM32_EID_SCALL 3'h7 1.287 - 1.288 -// Pipeline result selection mux controls 1.289 - 1.290 -`define LM32_D_RESULT_SEL_0_RNG 0:0 1.291 -`define LM32_D_RESULT_SEL_0_REG_0 1'b0 1.292 -`define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1 1.293 - 1.294 -`define LM32_D_RESULT_SEL_1_RNG 1:0 1.295 -`define LM32_D_RESULT_SEL_1_ZERO 2'b00 1.296 -`define LM32_D_RESULT_SEL_1_REG_1 2'b01 1.297 -`define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10 1.298 - 1.299 -`define LM32_USER_OPCODE_WIDTH 11 1.300 -`define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0 1.301 - 1.302 -// Derive a macro to indicate if either of the caches are implemented 1.303 -`ifdef CFG_ICACHE_ENABLED 1.304 -`define LM32_CACHE_ENABLED 1.305 -`else 1.306 -`ifdef CFG_DCACHE_ENABLED 1.307 -`define LM32_CACHE_ENABLED 1.308 -`endif 1.309 -`endif 1.310 - 1.311 -///////////////////////////////////////////////////// 1.312 -// Interrupts 1.313 -///////////////////////////////////////////////////// 1.314 - 1.315 -// Always enable interrupts 1.316 -`define CFG_INTERRUPTS_ENABLED 1.317 - 1.318 -// Currently this is fixed to 32 and should not be changed 1.319 -`define CFG_INTERRUPTS 32 1.320 -`define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS 1.321 -`define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0 1.322 - 1.323 -///////////////////////////////////////////////////// 1.324 -// General 1.325 -///////////////////////////////////////////////////// 1.326 - 1.327 -// Sub-word range types 1.328 -`define LM32_BYTE_WIDTH 8 1.329 -`define LM32_BYTE_RNG 7:0 1.330 -`define LM32_HWORD_WIDTH 16 1.331 -`define LM32_HWORD_RNG 15:0 1.332 - 1.333 -// Word sub-byte indicies 1.334 -`define LM32_BYTE_0_RNG 7:0 1.335 -`define LM32_BYTE_1_RNG 15:8 1.336 -`define LM32_BYTE_2_RNG 23:16 1.337 -`define LM32_BYTE_3_RNG 31:24 1.338 - 1.339 -// Word sub-halfword indices 1.340 -`define LM32_HWORD_0_RNG 15:0 1.341 -`define LM32_HWORD_1_RNG 31:16 1.342 - 1.343 -// Use an asynchronous reset 1.344 -// To use a synchronous reset, define this macro as nothing 1.345 -//`define CFG_RESET_SENSITIVITY or posedge rst_i 1.346 -`define CFG_RESET_SENSITIVITY 1.347 - 1.348 -// Whether to include context registers for debug exceptions 1.349 -// in addition to standard exception handling registers 1.350 -`define CFG_DEBUG_EXCEPTIONS_ENABLED 1.351 - 1.352 -// Wishbone defines 1.353 -// Refer to Wishbone System-on-Chip Interconnection Architecture 1.354 -// These should probably be moved to a Wishbone common file 1.355 - 1.356 -// Wishbone cycle types 1.357 -`define LM32_CTYPE_WIDTH 3 1.358 -`define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0 1.359 -`define LM32_CTYPE_CLASSIC 3'b000 1.360 -`define LM32_CTYPE_CONSTANT 3'b001 1.361 -`define LM32_CTYPE_INCREMENTING 3'b010 1.362 -`define LM32_CTYPE_END 3'b111 1.363 - 1.364 -// Wishbone burst types 1.365 -`define LM32_BTYPE_WIDTH 2 1.366 -`define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0 1.367 -`define LM32_BTYPE_LINEAR 2'b00 1.368 -`define LM32_BTYPE_4_BEAT 2'b01 1.369 -`define LM32_BTYPE_8_BEAT 2'b10 1.370 -`define LM32_BTYPE_16_BEAT 2'b11 1.371 - 1.372 -`endif