1.1 diff -r 252df75c8f67 -r c336e674a37e lm32_load_store_unit.v 1.2 --- a/lm32_load_store_unit.v Sun Mar 06 21:17:31 2011 +0000 1.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 1.4 @@ -1,806 +0,0 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 -// 1.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 -// U.S.A email: techsupport@latticesemi.com 1.19 -// =============================================================================/ 1.20 -// FILE DETAILS 1.21 -// Project : LatticeMico32 1.22 -// File : lm32_load_store_unit.v 1.23 -// Title : Load and store unit 1.24 -// Dependencies : lm32_include.v 1.25 -// Version : 6.1.17 1.26 -// : Initial Release 1.27 -// Version : 7.0SP2, 3.0 1.28 -// : No Change 1.29 -// Version : 3.1 1.30 -// : Instead of disallowing an instruction cache miss on a data cache 1.31 -// : miss, both can now occur at the same time. If both occur at same 1.32 -// : time, then restart address is the address of instruction that 1.33 -// : caused data cache miss. 1.34 -// Version : 3.2 1.35 -// : EBRs use SYNC resets instead of ASYNC resets. 1.36 -// Version : 3.3 1.37 -// : Support for new non-cacheable Data Memory that is accessible by 1.38 -// : the data port and has a one cycle access latency. 1.39 -// Version : 3.4 1.40 -// : No change 1.41 -// Version : 3.5 1.42 -// : Bug fix: Inline memory is correctly generated if it is not a 1.43 -// : power-of-two 1.44 -// ============================================================================= 1.45 - 1.46 -`include "lm32_include.v" 1.47 - 1.48 -///////////////////////////////////////////////////// 1.49 -// Module interface 1.50 -///////////////////////////////////////////////////// 1.51 - 1.52 -module lm32_load_store_unit ( 1.53 - // ----- Inputs ------- 1.54 - clk_i, 1.55 - rst_i, 1.56 - // From pipeline 1.57 - stall_a, 1.58 - stall_x, 1.59 - stall_m, 1.60 - kill_m, 1.61 - exception_m, 1.62 - store_operand_x, 1.63 - load_store_address_x, 1.64 - load_store_address_m, 1.65 - load_store_address_w, 1.66 - load_x, 1.67 - store_x, 1.68 - load_q_x, 1.69 - store_q_x, 1.70 - load_q_m, 1.71 - store_q_m, 1.72 - sign_extend_x, 1.73 - size_x, 1.74 -`ifdef CFG_DCACHE_ENABLED 1.75 - dflush, 1.76 -`endif 1.77 -`ifdef CFG_IROM_ENABLED 1.78 - irom_data_m, 1.79 -`endif 1.80 - // From Wishbone 1.81 - d_dat_i, 1.82 - d_ack_i, 1.83 - d_err_i, 1.84 - d_rty_i, 1.85 - // ----- Outputs ------- 1.86 - // To pipeline 1.87 -`ifdef CFG_DCACHE_ENABLED 1.88 - dcache_refill_request, 1.89 - dcache_restart_request, 1.90 - dcache_stall_request, 1.91 - dcache_refilling, 1.92 -`endif 1.93 -`ifdef CFG_IROM_ENABLED 1.94 - irom_store_data_m, 1.95 - irom_address_xm, 1.96 - irom_we_xm, 1.97 - irom_stall_request_x, 1.98 -`endif 1.99 - load_data_w, 1.100 - stall_wb_load, 1.101 - // To Wishbone 1.102 - d_dat_o, 1.103 - d_adr_o, 1.104 - d_cyc_o, 1.105 - d_sel_o, 1.106 - d_stb_o, 1.107 - d_we_o, 1.108 - d_cti_o, 1.109 - d_lock_o, 1.110 - d_bte_o 1.111 - ); 1.112 - 1.113 -///////////////////////////////////////////////////// 1.114 -// Parameters 1.115 -///////////////////////////////////////////////////// 1.116 - 1.117 -parameter associativity = 1; // Associativity of the cache (Number of ways) 1.118 -parameter sets = 512; // Number of sets 1.119 -parameter bytes_per_line = 16; // Number of bytes per cache line 1.120 -parameter base_address = 0; // Base address of cachable memory 1.121 -parameter limit = 0; // Limit (highest address) of cachable memory 1.122 - 1.123 -// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 1.124 -localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2; 1.125 -localparam addr_offset_lsb = 2; 1.126 -localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 1.127 - 1.128 -///////////////////////////////////////////////////// 1.129 -// Inputs 1.130 -///////////////////////////////////////////////////// 1.131 - 1.132 -input clk_i; // Clock 1.133 -input rst_i; // Reset 1.134 - 1.135 -input stall_a; // A stage stall 1.136 -input stall_x; // X stage stall 1.137 -input stall_m; // M stage stall 1.138 -input kill_m; // Kill instruction in M stage 1.139 -input exception_m; // An exception occured in the M stage 1.140 - 1.141 -input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store 1.142 -input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address 1.143 -input [`LM32_WORD_RNG] load_store_address_m; // M stage load/store address 1.144 -input [1:0] load_store_address_w; // W stage load/store address (only least two significant bits are needed) 1.145 -input load_x; // Load instruction in X stage 1.146 -input store_x; // Store instruction in X stage 1.147 -input load_q_x; // Load instruction in X stage 1.148 -input store_q_x; // Store instruction in X stage 1.149 -input load_q_m; // Load instruction in M stage 1.150 -input store_q_m; // Store instruction in M stage 1.151 -input sign_extend_x; // Whether load instruction in X stage should sign extend or zero extend 1.152 -input [`LM32_SIZE_RNG] size_x; // Size of load or store (byte, hword, word) 1.153 - 1.154 -`ifdef CFG_DCACHE_ENABLED 1.155 -input dflush; // Flush the data cache 1.156 -`endif 1.157 - 1.158 -`ifdef CFG_IROM_ENABLED 1.159 -input [`LM32_WORD_RNG] irom_data_m; // Data from Instruction-ROM 1.160 -`endif 1.161 - 1.162 -input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data 1.163 -input d_ack_i; // Data Wishbone interface acknowledgement 1.164 -input d_err_i; // Data Wishbone interface error 1.165 -input d_rty_i; // Data Wishbone interface retry 1.166 - 1.167 -///////////////////////////////////////////////////// 1.168 -// Outputs 1.169 -///////////////////////////////////////////////////// 1.170 - 1.171 -`ifdef CFG_DCACHE_ENABLED 1.172 -output dcache_refill_request; // Request to refill data cache 1.173 -wire dcache_refill_request; 1.174 -output dcache_restart_request; // Request to restart the instruction that caused a data cache miss 1.175 -wire dcache_restart_request; 1.176 -output dcache_stall_request; // Data cache stall request 1.177 -wire dcache_stall_request; 1.178 -output dcache_refilling; 1.179 -wire dcache_refilling; 1.180 -`endif 1.181 - 1.182 -`ifdef CFG_IROM_ENABLED 1.183 -output irom_store_data_m; // Store data to Instruction ROM 1.184 -wire [`LM32_WORD_RNG] irom_store_data_m; 1.185 -output [`LM32_WORD_RNG] irom_address_xm; // Load/store address to Instruction ROM 1.186 -wire [`LM32_WORD_RNG] irom_address_xm; 1.187 -output irom_we_xm; // Write-enable of 2nd port of Instruction ROM 1.188 -wire irom_we_xm; 1.189 -output irom_stall_request_x; // Stall instruction in D stage 1.190 -wire irom_stall_request_x; 1.191 -`endif 1.192 - 1.193 -output [`LM32_WORD_RNG] load_data_w; // Result of a load instruction 1.194 -reg [`LM32_WORD_RNG] load_data_w; 1.195 -output stall_wb_load; // Request to stall pipeline due to a load from the Wishbone interface 1.196 -reg stall_wb_load; 1.197 - 1.198 -output [`LM32_WORD_RNG] d_dat_o; // Data Wishbone interface write data 1.199 -reg [`LM32_WORD_RNG] d_dat_o; 1.200 -output [`LM32_WORD_RNG] d_adr_o; // Data Wishbone interface address 1.201 -reg [`LM32_WORD_RNG] d_adr_o; 1.202 -output d_cyc_o; // Data Wishbone interface cycle 1.203 -reg d_cyc_o; 1.204 -output [`LM32_BYTE_SELECT_RNG] d_sel_o; // Data Wishbone interface byte select 1.205 -reg [`LM32_BYTE_SELECT_RNG] d_sel_o; 1.206 -output d_stb_o; // Data Wishbone interface strobe 1.207 -reg d_stb_o; 1.208 -output d_we_o; // Data Wishbone interface write enable 1.209 -reg d_we_o; 1.210 -output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type 1.211 -reg [`LM32_CTYPE_RNG] d_cti_o; 1.212 -output d_lock_o; // Date Wishbone interface lock bus 1.213 -reg d_lock_o; 1.214 -output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type 1.215 -wire [`LM32_BTYPE_RNG] d_bte_o; 1.216 - 1.217 -///////////////////////////////////////////////////// 1.218 -// Internal nets and registers 1.219 -///////////////////////////////////////////////////// 1.220 - 1.221 -// Microcode pipeline registers - See inputs for description 1.222 -reg [`LM32_SIZE_RNG] size_m; 1.223 -reg [`LM32_SIZE_RNG] size_w; 1.224 -reg sign_extend_m; 1.225 -reg sign_extend_w; 1.226 -reg [`LM32_WORD_RNG] store_data_x; 1.227 -reg [`LM32_WORD_RNG] store_data_m; 1.228 -reg [`LM32_BYTE_SELECT_RNG] byte_enable_x; 1.229 -reg [`LM32_BYTE_SELECT_RNG] byte_enable_m; 1.230 -wire [`LM32_WORD_RNG] data_m; 1.231 -reg [`LM32_WORD_RNG] data_w; 1.232 - 1.233 -`ifdef CFG_DCACHE_ENABLED 1.234 -wire dcache_select_x; // Select data cache to load from / store to 1.235 -reg dcache_select_m; 1.236 -wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache 1.237 -wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from 1.238 -reg dcache_refill_ready; // Indicates the next word of refill data is ready 1.239 -wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type 1.240 -wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type 1.241 -wire last_word; // Indicates if this is the last word in the cache line 1.242 -wire [`LM32_WORD_RNG] first_address; // First cache refill address 1.243 -`endif 1.244 -`ifdef CFG_DRAM_ENABLED 1.245 -wire dram_select_x; // Select data RAM to load from / store to 1.246 -reg dram_select_m; 1.247 -reg dram_bypass_en; // RAW in data RAM; read latched (bypass) value rather than value from memory 1.248 -reg [`LM32_WORD_RNG] dram_bypass_data; // Latched value of store'd data to data RAM 1.249 -wire [`LM32_WORD_RNG] dram_data_out; // Data read from data RAM 1.250 -wire [`LM32_WORD_RNG] dram_data_m; // Data read from data RAM: bypass value or value from memory 1.251 -wire [`LM32_WORD_RNG] dram_store_data_m; // Data to write to RAM 1.252 -`endif 1.253 -wire wb_select_x; // Select Wishbone to load from / store to 1.254 -`ifdef CFG_IROM_ENABLED 1.255 -wire irom_select_x; // Select instruction ROM to load from / store to 1.256 -reg irom_select_m; 1.257 -`endif 1.258 -reg wb_select_m; 1.259 -reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone 1.260 -reg wb_load_complete; // Indicates when a Wishbone load is complete 1.261 - 1.262 -///////////////////////////////////////////////////// 1.263 -// Functions 1.264 -///////////////////////////////////////////////////// 1.265 - 1.266 -`include "lm32_functions.v" 1.267 - 1.268 -///////////////////////////////////////////////////// 1.269 -// Instantiations 1.270 -///////////////////////////////////////////////////// 1.271 - 1.272 -`ifdef CFG_DRAM_ENABLED 1.273 - // Data RAM 1.274 - pmi_ram_dp_true 1.275 - #( 1.276 - // ----- Parameters ------- 1.277 - .pmi_family (`LATTICE_FAMILY), 1.278 - 1.279 - //.pmi_addr_depth_a (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 1.280 - //.pmi_addr_width_a ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 1.281 - //.pmi_data_width_a (`LM32_WORD_WIDTH), 1.282 - //.pmi_addr_depth_b (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 1.283 - //.pmi_addr_width_b ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 1.284 - //.pmi_data_width_b (`LM32_WORD_WIDTH), 1.285 - 1.286 - .pmi_addr_depth_a (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1), 1.287 - .pmi_addr_width_a (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)), 1.288 - .pmi_data_width_a (`LM32_WORD_WIDTH), 1.289 - .pmi_addr_depth_b (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1), 1.290 - .pmi_addr_width_b (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)), 1.291 - .pmi_data_width_b (`LM32_WORD_WIDTH), 1.292 - 1.293 - .pmi_regmode_a ("noreg"), 1.294 - .pmi_regmode_b ("noreg"), 1.295 - .pmi_gsr ("enable"), 1.296 - .pmi_resetmode ("sync"), 1.297 - .pmi_init_file (`CFG_DRAM_INIT_FILE), 1.298 - .pmi_init_file_format (`CFG_DRAM_INIT_FILE_FORMAT), 1.299 - .module_type ("pmi_ram_dp_true") 1.300 - ) 1.301 - ram ( 1.302 - // ----- Inputs ------- 1.303 - .ClockA (clk_i), 1.304 - .ClockB (clk_i), 1.305 - .ResetA (rst_i), 1.306 - .ResetB (rst_i), 1.307 - .DataInA ({32{1'b0}}), 1.308 - .DataInB (dram_store_data_m), 1.309 - .AddressA (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.310 - .AddressB (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.311 - // .ClockEnA (!stall_x & (load_x | store_x)), 1.312 - .ClockEnA (!stall_x), 1.313 - .ClockEnB (!stall_m), 1.314 - .WrA (`FALSE), 1.315 - .WrB (store_q_m & dram_select_m), 1.316 - // ----- Outputs ------- 1.317 - .QA (dram_data_out), 1.318 - .QB () 1.319 - ); 1.320 - 1.321 - /*---------------------------------------------------------------------- 1.322 - EBRs cannot perform reads from location 'written to' on the same clock 1.323 - edge. Therefore bypass logic is required to latch the store'd value 1.324 - and use it for the load (instead of value from memory). 1.325 - ----------------------------------------------------------------------*/ 1.326 - always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.327 - if (rst_i == `TRUE) 1.328 - begin 1.329 - dram_bypass_en <= `FALSE; 1.330 - dram_bypass_data <= 0; 1.331 - end 1.332 - else 1.333 - begin 1.334 - if (stall_x == `FALSE) 1.335 - dram_bypass_data <= dram_store_data_m; 1.336 - 1.337 - if ( (stall_m == `FALSE) 1.338 - && (stall_x == `FALSE) 1.339 - && (store_q_m == `TRUE) 1.340 - && ( (load_x == `TRUE) 1.341 - || (store_x == `TRUE) 1.342 - ) 1.343 - && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2]) 1.344 - ) 1.345 - dram_bypass_en <= `TRUE; 1.346 - else 1.347 - if ( (dram_bypass_en == `TRUE) 1.348 - && (stall_x == `FALSE) 1.349 - ) 1.350 - dram_bypass_en <= `FALSE; 1.351 - end 1.352 - 1.353 - assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out; 1.354 -`endif 1.355 - 1.356 -`ifdef CFG_DCACHE_ENABLED 1.357 -// Data cache 1.358 -lm32_dcache #( 1.359 - .associativity (associativity), 1.360 - .sets (sets), 1.361 - .bytes_per_line (bytes_per_line), 1.362 - .base_address (base_address), 1.363 - .limit (limit) 1.364 - ) dcache ( 1.365 - // ----- Inputs ----- 1.366 - .clk_i (clk_i), 1.367 - .rst_i (rst_i), 1.368 - .stall_a (stall_a), 1.369 - .stall_x (stall_x), 1.370 - .stall_m (stall_m), 1.371 - .address_x (load_store_address_x), 1.372 - .address_m (load_store_address_m), 1.373 - .load_q_m (load_q_m & dcache_select_m), 1.374 - .store_q_m (store_q_m & dcache_select_m), 1.375 - .store_data (store_data_m), 1.376 - .store_byte_select (byte_enable_m & {4{dcache_select_m}}), 1.377 - .refill_ready (dcache_refill_ready), 1.378 - .refill_data (wb_data_m), 1.379 - .dflush (dflush), 1.380 - // ----- Outputs ----- 1.381 - .stall_request (dcache_stall_request), 1.382 - .restart_request (dcache_restart_request), 1.383 - .refill_request (dcache_refill_request), 1.384 - .refill_address (dcache_refill_address), 1.385 - .refilling (dcache_refilling), 1.386 - .load_data (dcache_data_m) 1.387 - ); 1.388 -`endif 1.389 - 1.390 -///////////////////////////////////////////////////// 1.391 -// Combinational Logic 1.392 -///////////////////////////////////////////////////// 1.393 - 1.394 -// Select where data should be loaded from / stored to 1.395 -`ifdef CFG_DRAM_ENABLED 1.396 - assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS) 1.397 - && (load_store_address_x <= `CFG_DRAM_LIMIT); 1.398 -`endif 1.399 - 1.400 -`ifdef CFG_IROM_ENABLED 1.401 - assign irom_select_x = (load_store_address_x >= `CFG_IROM_BASE_ADDRESS) 1.402 - && (load_store_address_x <= `CFG_IROM_LIMIT); 1.403 -`endif 1.404 - 1.405 -`ifdef CFG_DCACHE_ENABLED 1.406 - assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS) 1.407 - && (load_store_address_x <= `CFG_DCACHE_LIMIT) 1.408 -`ifdef CFG_DRAM_ENABLED 1.409 - && (dram_select_x == `FALSE) 1.410 -`endif 1.411 -`ifdef CFG_IROM_ENABLED 1.412 - && (irom_select_x == `FALSE) 1.413 -`endif 1.414 - ; 1.415 -`endif 1.416 - 1.417 - assign wb_select_x = `TRUE 1.418 -`ifdef CFG_DCACHE_ENABLED 1.419 - && !dcache_select_x 1.420 -`endif 1.421 -`ifdef CFG_DRAM_ENABLED 1.422 - && !dram_select_x 1.423 -`endif 1.424 -`ifdef CFG_IROM_ENABLED 1.425 - && !irom_select_x 1.426 -`endif 1.427 - ; 1.428 - 1.429 -// Make sure data to store is in correct byte lane 1.430 -always @(*) 1.431 -begin 1.432 - case (size_x) 1.433 - `LM32_SIZE_BYTE: store_data_x = {4{store_operand_x[7:0]}}; 1.434 - `LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}}; 1.435 - `LM32_SIZE_WORD: store_data_x = store_operand_x; 1.436 - default: store_data_x = {`LM32_WORD_WIDTH{1'bx}}; 1.437 - endcase 1.438 -end 1.439 - 1.440 -// Generate byte enable accoring to size of load or store and address being accessed 1.441 -always @(*) 1.442 -begin 1.443 - casez ({size_x, load_store_address_x[1:0]}) 1.444 - {`LM32_SIZE_BYTE, 2'b11}: byte_enable_x = 4'b0001; 1.445 - {`LM32_SIZE_BYTE, 2'b10}: byte_enable_x = 4'b0010; 1.446 - {`LM32_SIZE_BYTE, 2'b01}: byte_enable_x = 4'b0100; 1.447 - {`LM32_SIZE_BYTE, 2'b00}: byte_enable_x = 4'b1000; 1.448 - {`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011; 1.449 - {`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100; 1.450 - {`LM32_SIZE_WORD, 2'b??}: byte_enable_x = 4'b1111; 1.451 - default: byte_enable_x = 4'bxxxx; 1.452 - endcase 1.453 -end 1.454 - 1.455 -`ifdef CFG_DRAM_ENABLED 1.456 -// Only replace selected bytes 1.457 -assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG]; 1.458 -assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG]; 1.459 -assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG]; 1.460 -assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG]; 1.461 -`endif 1.462 - 1.463 -`ifdef CFG_IROM_ENABLED 1.464 -// Only replace selected bytes 1.465 -assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG]; 1.466 -assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG]; 1.467 -assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG]; 1.468 -assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG]; 1.469 -`endif 1.470 - 1.471 -`ifdef CFG_IROM_ENABLED 1.472 - // Instead of implementing a byte-addressable instruction ROM (for store byte instruction), 1.473 - // a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite 1.474 - // byte is replaced, and the whole 32-bit value is written back 1.475 - 1.476 - assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE)) 1.477 - ? load_store_address_m 1.478 - : load_store_address_x; 1.479 - 1.480 - // All store instructions perform a write operation in the M stage 1.481 - assign irom_we_xm = (irom_select_m == `TRUE) 1.482 - && (store_q_m == `TRUE); 1.483 - 1.484 - // A single port in instruction ROM is available to load-store unit for doing loads/stores. 1.485 - // Since every store requires a load (in X stage) and then a store (in M stage), we cannot 1.486 - // allow load (or store) instructions sequentially after the store instructions to proceed 1.487 - // until the store instruction has vacated M stage (i.e., completed the store operation) 1.488 - assign irom_stall_request_x = (irom_select_x == `TRUE) 1.489 - && (store_q_x == `TRUE); 1.490 -`endif 1.491 - 1.492 -`ifdef CFG_DCACHE_ENABLED 1.493 - `ifdef CFG_DRAM_ENABLED 1.494 - `ifdef CFG_IROM_ENABLED 1.495 - // WB + DC + DRAM + IROM 1.496 - assign data_m = wb_select_m == `TRUE 1.497 - ? wb_data_m 1.498 - : dram_select_m == `TRUE 1.499 - ? dram_data_m 1.500 - : irom_select_m == `TRUE 1.501 - ? irom_data_m 1.502 - : dcache_data_m; 1.503 - `else 1.504 - // WB + DC + DRAM 1.505 - assign data_m = wb_select_m == `TRUE 1.506 - ? wb_data_m 1.507 - : dram_select_m == `TRUE 1.508 - ? dram_data_m 1.509 - : dcache_data_m; 1.510 - `endif 1.511 - `else 1.512 - `ifdef CFG_IROM_ENABLED 1.513 - // WB + DC + IROM 1.514 - assign data_m = wb_select_m == `TRUE 1.515 - ? wb_data_m 1.516 - : irom_select_m == `TRUE 1.517 - ? irom_data_m 1.518 - : dcache_data_m; 1.519 - `else 1.520 - // WB + DC 1.521 - assign data_m = wb_select_m == `TRUE 1.522 - ? wb_data_m 1.523 - : dcache_data_m; 1.524 - `endif 1.525 - `endif 1.526 -`else 1.527 - `ifdef CFG_DRAM_ENABLED 1.528 - `ifdef CFG_IROM_ENABLED 1.529 - // WB + DRAM + IROM 1.530 - assign data_m = wb_select_m == `TRUE 1.531 - ? wb_data_m 1.532 - : dram_select_m == `TRUE 1.533 - ? dram_data_m 1.534 - : irom_data_m; 1.535 - `else 1.536 - // WB + DRAM 1.537 - assign data_m = wb_select_m == `TRUE 1.538 - ? wb_data_m 1.539 - : dram_data_m; 1.540 - `endif 1.541 - `else 1.542 - `ifdef CFG_IROM_ENABLED 1.543 - // WB + IROM 1.544 - assign data_m = wb_select_m == `TRUE 1.545 - ? wb_data_m 1.546 - : irom_data_m; 1.547 - `else 1.548 - // WB 1.549 - assign data_m = wb_data_m; 1.550 - `endif 1.551 - `endif 1.552 -`endif 1.553 - 1.554 -// Sub-word selection and sign/zero-extension for loads 1.555 -always @(*) 1.556 -begin 1.557 - casez ({size_w, load_store_address_w[1:0]}) 1.558 - {`LM32_SIZE_BYTE, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]}; 1.559 - {`LM32_SIZE_BYTE, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]}; 1.560 - {`LM32_SIZE_BYTE, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]}; 1.561 - {`LM32_SIZE_BYTE, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]}; 1.562 - {`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]}; 1.563 - {`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]}; 1.564 - {`LM32_SIZE_WORD, 2'b??}: load_data_w = data_w; 1.565 - default: load_data_w = {`LM32_WORD_WIDTH{1'bx}}; 1.566 - endcase 1.567 -end 1.568 - 1.569 -// Unused/constant Wishbone signals 1.570 -assign d_bte_o = `LM32_BTYPE_LINEAR; 1.571 - 1.572 -`ifdef CFG_DCACHE_ENABLED 1.573 -// Generate signal to indicate last word in cache line 1.574 -generate 1.575 - case (bytes_per_line) 1.576 - 4: 1.577 - begin 1.578 -assign first_cycle_type = `LM32_CTYPE_END; 1.579 -assign next_cycle_type = `LM32_CTYPE_END; 1.580 -assign last_word = `TRUE; 1.581 -assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00}; 1.582 - end 1.583 - 8: 1.584 - begin 1.585 -assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 1.586 -assign next_cycle_type = `LM32_CTYPE_END; 1.587 -assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1; 1.588 -assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00}; 1.589 - end 1.590 - 16: 1.591 - begin 1.592 -assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 1.593 -assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING; 1.594 -assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1; 1.595 -assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00}; 1.596 - end 1.597 - endcase 1.598 -endgenerate 1.599 -`endif 1.600 - 1.601 -///////////////////////////////////////////////////// 1.602 -// Sequential Logic 1.603 -///////////////////////////////////////////////////// 1.604 - 1.605 -// Data Wishbone interface 1.606 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.607 -begin 1.608 - if (rst_i == `TRUE) 1.609 - begin 1.610 - d_cyc_o <= `FALSE; 1.611 - d_stb_o <= `FALSE; 1.612 - d_dat_o <= {`LM32_WORD_WIDTH{1'b0}}; 1.613 - d_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 1.614 - d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}}; 1.615 - d_we_o <= `FALSE; 1.616 - d_cti_o <= `LM32_CTYPE_END; 1.617 - d_lock_o <= `FALSE; 1.618 - wb_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 1.619 - wb_load_complete <= `FALSE; 1.620 - stall_wb_load <= `FALSE; 1.621 -`ifdef CFG_DCACHE_ENABLED 1.622 - dcache_refill_ready <= `FALSE; 1.623 -`endif 1.624 - end 1.625 - else 1.626 - begin 1.627 -`ifdef CFG_DCACHE_ENABLED 1.628 - // Refill ready should only be asserted for a single cycle 1.629 - dcache_refill_ready <= `FALSE; 1.630 -`endif 1.631 - // Is a Wishbone cycle already in progress? 1.632 - if (d_cyc_o == `TRUE) 1.633 - begin 1.634 - // Is the cycle complete? 1.635 - if ((d_ack_i == `TRUE) || (d_err_i == `TRUE)) 1.636 - begin 1.637 -`ifdef CFG_DCACHE_ENABLED 1.638 - if ((dcache_refilling == `TRUE) && (!last_word)) 1.639 - begin 1.640 - // Fetch next word of cache line 1.641 - d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 1.642 - end 1.643 - else 1.644 -`endif 1.645 - begin 1.646 - // Refill/access complete 1.647 - d_cyc_o <= `FALSE; 1.648 - d_stb_o <= `FALSE; 1.649 - d_lock_o <= `FALSE; 1.650 - end 1.651 -`ifdef CFG_DCACHE_ENABLED 1.652 - d_cti_o <= next_cycle_type; 1.653 - // If we are performing a refill, indicate to cache next word of data is ready 1.654 - dcache_refill_ready <= dcache_refilling; 1.655 -`endif 1.656 - // Register data read from Wishbone interface 1.657 - wb_data_m <= d_dat_i; 1.658 - // Don't set when stores complete - otherwise we'll deadlock if load in m stage 1.659 - wb_load_complete <= !d_we_o; 1.660 - end 1.661 - // synthesis translate_off 1.662 - if (d_err_i == `TRUE) 1.663 - $display ("Data bus error. Address: %x", d_adr_o); 1.664 - // synthesis translate_on 1.665 - end 1.666 - else 1.667 - begin 1.668 -`ifdef CFG_DCACHE_ENABLED 1.669 - if (dcache_refill_request == `TRUE) 1.670 - begin 1.671 - // Start cache refill 1.672 - d_adr_o <= first_address; 1.673 - d_cyc_o <= `TRUE; 1.674 - d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}}; 1.675 - d_stb_o <= `TRUE; 1.676 - d_we_o <= `FALSE; 1.677 - d_cti_o <= first_cycle_type; 1.678 - //d_lock_o <= `TRUE; 1.679 - end 1.680 - else 1.681 -`endif 1.682 - if ( (store_q_m == `TRUE) 1.683 - && (stall_m == `FALSE) 1.684 -`ifdef CFG_DRAM_ENABLED 1.685 - && (dram_select_m == `FALSE) 1.686 -`endif 1.687 -`ifdef CFG_IROM_ENABLED 1.688 - && (irom_select_m == `FALSE) 1.689 -`endif 1.690 - ) 1.691 - begin 1.692 - // Data cache is write through, so all stores go to memory 1.693 - d_dat_o <= store_data_m; 1.694 - d_adr_o <= load_store_address_m; 1.695 - d_cyc_o <= `TRUE; 1.696 - d_sel_o <= byte_enable_m; 1.697 - d_stb_o <= `TRUE; 1.698 - d_we_o <= `TRUE; 1.699 - d_cti_o <= `LM32_CTYPE_END; 1.700 - end 1.701 - else if ( (load_q_m == `TRUE) 1.702 - && (wb_select_m == `TRUE) 1.703 - && (wb_load_complete == `FALSE) 1.704 - // stall_m will be TRUE, because stall_wb_load will be TRUE 1.705 - ) 1.706 - begin 1.707 - // Read requested address 1.708 - stall_wb_load <= `FALSE; 1.709 - d_adr_o <= load_store_address_m; 1.710 - d_cyc_o <= `TRUE; 1.711 - d_sel_o <= byte_enable_m; 1.712 - d_stb_o <= `TRUE; 1.713 - d_we_o <= `FALSE; 1.714 - d_cti_o <= `LM32_CTYPE_END; 1.715 - end 1.716 - end 1.717 - // Clear load/store complete flag when instruction leaves M stage 1.718 - if (stall_m == `FALSE) 1.719 - wb_load_complete <= `FALSE; 1.720 - // When a Wishbone load first enters the M stage, we need to stall it 1.721 - if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE)) 1.722 - stall_wb_load <= `TRUE; 1.723 - // Clear stall request if load instruction is killed 1.724 - if ((kill_m == `TRUE) || (exception_m == `TRUE)) 1.725 - stall_wb_load <= `FALSE; 1.726 - end 1.727 -end 1.728 - 1.729 -// Pipeline registers 1.730 - 1.731 -// X/M stage pipeline registers 1.732 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.733 -begin 1.734 - if (rst_i == `TRUE) 1.735 - begin 1.736 - sign_extend_m <= `FALSE; 1.737 - size_m <= 2'b00; 1.738 - byte_enable_m <= `FALSE; 1.739 - store_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 1.740 -`ifdef CFG_DCACHE_ENABLED 1.741 - dcache_select_m <= `FALSE; 1.742 -`endif 1.743 -`ifdef CFG_DRAM_ENABLED 1.744 - dram_select_m <= `FALSE; 1.745 -`endif 1.746 -`ifdef CFG_IROM_ENABLED 1.747 - irom_select_m <= `FALSE; 1.748 -`endif 1.749 - wb_select_m <= `FALSE; 1.750 - end 1.751 - else 1.752 - begin 1.753 - if (stall_m == `FALSE) 1.754 - begin 1.755 - sign_extend_m <= sign_extend_x; 1.756 - size_m <= size_x; 1.757 - byte_enable_m <= byte_enable_x; 1.758 - store_data_m <= store_data_x; 1.759 -`ifdef CFG_DCACHE_ENABLED 1.760 - dcache_select_m <= dcache_select_x; 1.761 -`endif 1.762 -`ifdef CFG_DRAM_ENABLED 1.763 - dram_select_m <= dram_select_x; 1.764 -`endif 1.765 -`ifdef CFG_IROM_ENABLED 1.766 - irom_select_m <= irom_select_x; 1.767 -`endif 1.768 - wb_select_m <= wb_select_x; 1.769 - end 1.770 - end 1.771 -end 1.772 - 1.773 -// M/W stage pipeline registers 1.774 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.775 -begin 1.776 - if (rst_i == `TRUE) 1.777 - begin 1.778 - size_w <= 2'b00; 1.779 - data_w <= {`LM32_WORD_WIDTH{1'b0}}; 1.780 - sign_extend_w <= `FALSE; 1.781 - end 1.782 - else 1.783 - begin 1.784 - size_w <= size_m; 1.785 - data_w <= data_m; 1.786 - sign_extend_w <= sign_extend_m; 1.787 - end 1.788 -end 1.789 - 1.790 -///////////////////////////////////////////////////// 1.791 -// Behavioural Logic 1.792 -///////////////////////////////////////////////////// 1.793 - 1.794 -// synthesis translate_off 1.795 - 1.796 -// Check for non-aligned loads or stores 1.797 -always @(posedge clk_i) 1.798 -begin 1.799 - if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE)) 1.800 - begin 1.801 - if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0)) 1.802 - $display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time); 1.803 - if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00)) 1.804 - $display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time); 1.805 - end 1.806 -end 1.807 - 1.808 -// synthesis translate_on 1.809 - 1.810 -endmodule