1.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_dcache.v 1.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 +++ b/rtl/lm32_dcache.v Tue Mar 08 09:40:42 2011 +0000 1.4 @@ -0,0 +1,542 @@ 1.5 +// ============================================================================= 1.6 +// COPYRIGHT NOTICE 1.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 +// ALL RIGHTS RESERVED 1.9 +// This confidential and proprietary software may be used only as authorised by 1.10 +// a licensing agreement from Lattice Semiconductor Corporation. 1.11 +// The entire notice above must be reproduced on all authorized copies and 1.12 +// copies may only be made to the extent permitted by a licensing agreement from 1.13 +// Lattice Semiconductor Corporation. 1.14 +// 1.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 +// U.S.A email: techsupport@latticesemi.com 1.19 +// =============================================================================/ 1.20 +// FILE DETAILS 1.21 +// Project : LatticeMico32 1.22 +// File : lm32_dcache.v 1.23 +// Title : Data cache 1.24 +// Dependencies : lm32_include.v 1.25 +// Version : 6.1.17 1.26 +// : Initial Release 1.27 +// Version : 7.0SP2, 3.0 1.28 +// : No Change 1.29 +// Version : 3.1 1.30 +// : Support for user-selected resource usage when implementing 1.31 +// : cache memory. Additional parameters must be defined when 1.32 +// : invoking lm32_ram.v 1.33 +// ============================================================================= 1.34 + 1.35 +`include "lm32_include.v" 1.36 + 1.37 +`ifdef CFG_DCACHE_ENABLED 1.38 + 1.39 +`define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb 1.40 +`define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb 1.41 +`define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb 1.42 +`define LM32_DC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb 1.43 + 1.44 +`define LM32_DC_TMEM_ADDR_WIDTH addr_set_width 1.45 +`define LM32_DC_TMEM_ADDR_RNG (`LM32_DC_TMEM_ADDR_WIDTH-1):0 1.46 +`define LM32_DC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width) 1.47 +`define LM32_DC_DMEM_ADDR_RNG (`LM32_DC_DMEM_ADDR_WIDTH-1):0 1.48 + 1.49 +`define LM32_DC_TAGS_WIDTH (addr_tag_width+1) 1.50 +`define LM32_DC_TAGS_RNG (`LM32_DC_TAGS_WIDTH-1):0 1.51 +`define LM32_DC_TAGS_TAG_RNG (`LM32_DC_TAGS_WIDTH-1):1 1.52 +`define LM32_DC_TAGS_VALID_RNG 0 1.53 + 1.54 +`define LM32_DC_STATE_RNG 2:0 1.55 +`define LM32_DC_STATE_FLUSH 3'b001 1.56 +`define LM32_DC_STATE_CHECK 3'b010 1.57 +`define LM32_DC_STATE_REFILL 3'b100 1.58 + 1.59 +///////////////////////////////////////////////////// 1.60 +// Module interface 1.61 +///////////////////////////////////////////////////// 1.62 + 1.63 +module lm32_dcache ( 1.64 + // ----- Inputs ----- 1.65 + clk_i, 1.66 + rst_i, 1.67 + stall_a, 1.68 + stall_x, 1.69 + stall_m, 1.70 + address_x, 1.71 + address_m, 1.72 + load_q_m, 1.73 + store_q_m, 1.74 + store_data, 1.75 + store_byte_select, 1.76 + refill_ready, 1.77 + refill_data, 1.78 + dflush, 1.79 + // ----- Outputs ----- 1.80 + stall_request, 1.81 + restart_request, 1.82 + refill_request, 1.83 + refill_address, 1.84 + refilling, 1.85 + load_data 1.86 + ); 1.87 + 1.88 +///////////////////////////////////////////////////// 1.89 +// Parameters 1.90 +///////////////////////////////////////////////////// 1.91 + 1.92 +parameter associativity = 1; // Associativity of the cache (Number of ways) 1.93 +parameter sets = 512; // Number of sets 1.94 +parameter bytes_per_line = 16; // Number of bytes per cache line 1.95 +parameter base_address = 0; // Base address of cachable memory 1.96 +parameter limit = 0; // Limit (highest address) of cachable memory 1.97 + 1.98 +localparam addr_offset_width = clogb2(bytes_per_line)-1-2; 1.99 +localparam addr_set_width = clogb2(sets)-1; 1.100 +localparam addr_offset_lsb = 2; 1.101 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 1.102 +localparam addr_set_lsb = (addr_offset_msb+1); 1.103 +localparam addr_set_msb = (addr_set_lsb+addr_set_width-1); 1.104 +localparam addr_tag_lsb = (addr_set_msb+1); 1.105 +localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1; 1.106 +localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1); 1.107 + 1.108 +///////////////////////////////////////////////////// 1.109 +// Inputs 1.110 +///////////////////////////////////////////////////// 1.111 + 1.112 +input clk_i; // Clock 1.113 +input rst_i; // Reset 1.114 + 1.115 +input stall_a; // Stall A stage 1.116 +input stall_x; // Stall X stage 1.117 +input stall_m; // Stall M stage 1.118 + 1.119 +input [`LM32_WORD_RNG] address_x; // X stage load/store address 1.120 +input [`LM32_WORD_RNG] address_m; // M stage load/store address 1.121 +input load_q_m; // Load instruction in M stage 1.122 +input store_q_m; // Store instruction in M stage 1.123 +input [`LM32_WORD_RNG] store_data; // Data to store 1.124 +input [`LM32_BYTE_SELECT_RNG] store_byte_select; // Which bytes in store data should be modified 1.125 + 1.126 +input refill_ready; // Indicates next word of refill data is ready 1.127 +input [`LM32_WORD_RNG] refill_data; // Refill data 1.128 + 1.129 +input dflush; // Indicates cache should be flushed 1.130 + 1.131 +///////////////////////////////////////////////////// 1.132 +// Outputs 1.133 +///////////////////////////////////////////////////// 1.134 + 1.135 +output stall_request; // Request pipeline be stalled because cache is busy 1.136 +wire stall_request; 1.137 +output restart_request; // Request to restart instruction that caused the cache miss 1.138 +reg restart_request; 1.139 +output refill_request; // Request a refill 1.140 +reg refill_request; 1.141 +output [`LM32_WORD_RNG] refill_address; // Address to refill from 1.142 +reg [`LM32_WORD_RNG] refill_address; 1.143 +output refilling; // Indicates if the cache is currently refilling 1.144 +reg refilling; 1.145 +output [`LM32_WORD_RNG] load_data; // Data read from cache 1.146 +wire [`LM32_WORD_RNG] load_data; 1.147 + 1.148 +///////////////////////////////////////////////////// 1.149 +// Internal nets and registers 1.150 +///////////////////////////////////////////////////// 1.151 + 1.152 +wire read_port_enable; // Cache memory read port clock enable 1.153 +wire write_port_enable; // Cache memory write port clock enable 1.154 +wire [0:associativity-1] way_tmem_we; // Tag memory write enable 1.155 +wire [0:associativity-1] way_dmem_we; // Data memory write enable 1.156 +wire [`LM32_WORD_RNG] way_data[0:associativity-1]; // Data read from data memory 1.157 +wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory 1.158 +wire [0:associativity-1] way_valid; // Indicates which ways are valid 1.159 +wire [0:associativity-1] way_match; // Indicates which ways matched 1.160 +wire miss; // Indicates no ways matched 1.161 + 1.162 +wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read address 1.163 +wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address 1.164 +wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address 1.165 +wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address 1.166 +wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data 1.167 +reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data 1.168 + 1.169 +reg [`LM32_DC_STATE_RNG] state; // Current state of FSM 1.170 +wire flushing; // Indicates if cache is currently flushing 1.171 +wire check; // Indicates if cache is currently checking for hits/misses 1.172 +wire refill; // Indicates if cache is currently refilling 1.173 + 1.174 +wire valid_store; // Indicates if there is a valid store instruction 1.175 +reg [associativity-1:0] refill_way_select; // Which way should be refilled 1.176 +reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache line should be refilled 1.177 +wire last_refill; // Indicates when on last cycle of cache refill 1.178 +reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed 1.179 + 1.180 +genvar i, j; 1.181 + 1.182 +///////////////////////////////////////////////////// 1.183 +// Functions 1.184 +///////////////////////////////////////////////////// 1.185 + 1.186 +`include "lm32_functions.v" 1.187 + 1.188 +///////////////////////////////////////////////////// 1.189 +// Instantiations 1.190 +///////////////////////////////////////////////////// 1.191 + 1.192 + generate 1.193 + for (i = 0; i < associativity; i = i + 1) 1.194 + begin : memories 1.195 + // Way data 1.196 + if (`LM32_DC_DMEM_ADDR_WIDTH < 11) 1.197 + begin : data_memories 1.198 + lm32_ram 1.199 + #( 1.200 + // ----- Parameters ------- 1.201 + .data_width (32), 1.202 + .address_width (`LM32_DC_DMEM_ADDR_WIDTH) 1.203 +`ifdef PLATFORM_LATTICE 1.204 + , 1.205 + `ifdef CFG_DCACHE_DAT_USE_DP_TRUE 1.206 + .RAM_IMPLEMENTATION ("EBR"), 1.207 + .RAM_TYPE ("RAM_DP_TRUE") 1.208 + `else 1.209 + `ifdef CFG_DCACHE_DAT_USE_SLICE 1.210 + .RAM_IMPLEMENTATION ("SLICE") 1.211 + `else 1.212 + .RAM_IMPLEMENTATION ("AUTO") 1.213 + `endif 1.214 + `endif 1.215 +`endif 1.216 + ) way_0_data_ram 1.217 + ( 1.218 + // ----- Inputs ------- 1.219 + .read_clk (clk_i), 1.220 + .write_clk (clk_i), 1.221 + .reset (rst_i), 1.222 + .read_address (dmem_read_address), 1.223 + .enable_read (read_port_enable), 1.224 + .write_address (dmem_write_address), 1.225 + .enable_write (write_port_enable), 1.226 + .write_enable (way_dmem_we[i]), 1.227 + .write_data (dmem_write_data), 1.228 + // ----- Outputs ------- 1.229 + .read_data (way_data[i]) 1.230 + ); 1.231 + end 1.232 + else 1.233 + begin 1.234 + for (j = 0; j < 4; j = j + 1) 1.235 + begin : byte_memories 1.236 + lm32_ram 1.237 + #( 1.238 + // ----- Parameters ------- 1.239 + .data_width (8), 1.240 + .address_width (`LM32_DC_DMEM_ADDR_WIDTH) 1.241 +`ifdef PLATFORM_LATTICE 1.242 + , 1.243 + `ifdef CFG_DCACHE_DAT_USE_DP_TRUE 1.244 + .RAM_IMPLEMENTATION ("EBR"), 1.245 + .RAM_TYPE ("RAM_DP_TRUE") 1.246 + `else 1.247 + `ifdef CFG_DCACHE_DAT_USE_SLICE 1.248 + .RAM_IMPLEMENTATION ("SLICE") 1.249 + `else 1.250 + .RAM_IMPLEMENTATION ("AUTO") 1.251 + `endif 1.252 + `endif 1.253 +`endif 1.254 + ) way_0_data_ram 1.255 + ( 1.256 + // ----- Inputs ------- 1.257 + .read_clk (clk_i), 1.258 + .write_clk (clk_i), 1.259 + .reset (rst_i), 1.260 + .read_address (dmem_read_address), 1.261 + .enable_read (read_port_enable), 1.262 + .write_address (dmem_write_address), 1.263 + .enable_write (write_port_enable), 1.264 + .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)), 1.265 + .write_data (dmem_write_data[(j+1)*8-1:j*8]), 1.266 + // ----- Outputs ------- 1.267 + .read_data (way_data[i][(j+1)*8-1:j*8]) 1.268 + ); 1.269 + end 1.270 + end 1.271 + 1.272 + // Way tags 1.273 + lm32_ram 1.274 + #( 1.275 + // ----- Parameters ------- 1.276 + .data_width (`LM32_DC_TAGS_WIDTH), 1.277 + .address_width (`LM32_DC_TMEM_ADDR_WIDTH) 1.278 +`ifdef PLATFORM_LATTICE 1.279 + , 1.280 + `ifdef CFG_DCACHE_DAT_USE_DP_TRUE 1.281 + .RAM_IMPLEMENTATION ("EBR"), 1.282 + .RAM_TYPE ("RAM_DP_TRUE") 1.283 + `else 1.284 + `ifdef CFG_DCACHE_DAT_USE_SLICE 1.285 + .RAM_IMPLEMENTATION ("SLICE") 1.286 + `else 1.287 + .RAM_IMPLEMENTATION ("AUTO") 1.288 + `endif 1.289 + `endif 1.290 +`endif 1.291 + ) way_0_tag_ram 1.292 + ( 1.293 + // ----- Inputs ------- 1.294 + .read_clk (clk_i), 1.295 + .write_clk (clk_i), 1.296 + .reset (rst_i), 1.297 + .read_address (tmem_read_address), 1.298 + .enable_read (read_port_enable), 1.299 + .write_address (tmem_write_address), 1.300 + .enable_write (`TRUE), 1.301 + .write_enable (way_tmem_we[i]), 1.302 + .write_data (tmem_write_data), 1.303 + // ----- Outputs ------- 1.304 + .read_data ({way_tag[i], way_valid[i]}) 1.305 + ); 1.306 + end 1.307 + 1.308 + endgenerate 1.309 + 1.310 +///////////////////////////////////////////////////// 1.311 +// Combinational logic 1.312 +///////////////////////////////////////////////////// 1.313 + 1.314 +// Compute which ways in the cache match the address being read 1.315 +generate 1.316 + for (i = 0; i < associativity; i = i + 1) 1.317 + begin : match 1.318 +assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE}); 1.319 + end 1.320 +endgenerate 1.321 + 1.322 +// Select data from way that matched the address being read 1.323 +generate 1.324 + if (associativity == 1) 1.325 + begin : data_1 1.326 +assign load_data = way_data[0]; 1.327 + end 1.328 + else if (associativity == 2) 1.329 + begin : data_2 1.330 +assign load_data = way_match[0] ? way_data[0] : way_data[1]; 1.331 + end 1.332 +endgenerate 1.333 + 1.334 +generate 1.335 + if (`LM32_DC_DMEM_ADDR_WIDTH < 11) 1.336 + begin 1.337 +// Select data to write to data memories 1.338 +always @(*) 1.339 +begin 1.340 + if (refill == `TRUE) 1.341 + dmem_write_data = refill_data; 1.342 + else 1.343 + begin 1.344 + dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG]; 1.345 + dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG]; 1.346 + dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG]; 1.347 + dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG]; 1.348 + end 1.349 +end 1.350 + end 1.351 + else 1.352 + begin 1.353 +// Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work 1.354 +always @(*) 1.355 +begin 1.356 + if (refill == `TRUE) 1.357 + dmem_write_data = refill_data; 1.358 + else 1.359 + dmem_write_data = store_data; 1.360 +end 1.361 + end 1.362 +endgenerate 1.363 + 1.364 +// Compute address to use to index into the data memories 1.365 +generate 1.366 + if (bytes_per_line > 4) 1.367 +assign dmem_write_address = (refill == `TRUE) 1.368 + ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset} 1.369 + : address_m[`LM32_DC_ADDR_IDX_RNG]; 1.370 + else 1.371 +assign dmem_write_address = (refill == `TRUE) 1.372 + ? refill_address[`LM32_DC_ADDR_SET_RNG] 1.373 + : address_m[`LM32_DC_ADDR_IDX_RNG]; 1.374 +endgenerate 1.375 +assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG]; 1.376 +// Compute address to use to index into the tag memories 1.377 +assign tmem_write_address = (flushing == `TRUE) 1.378 + ? flush_set 1.379 + : refill_address[`LM32_DC_ADDR_SET_RNG]; 1.380 +assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG]; 1.381 + 1.382 +// Compute signal to indicate when we are on the last refill accesses 1.383 +generate 1.384 + if (bytes_per_line > 4) 1.385 +assign last_refill = refill_offset == {addr_offset_width{1'b1}}; 1.386 + else 1.387 +assign last_refill = `TRUE; 1.388 +endgenerate 1.389 + 1.390 +// Compute data and tag memory access enable 1.391 +assign read_port_enable = (stall_x == `FALSE); 1.392 +assign write_port_enable = (refill_ready == `TRUE) || !stall_m; 1.393 + 1.394 +// Determine when we have a valid store 1.395 +assign valid_store = (store_q_m == `TRUE) && (check == `TRUE); 1.396 + 1.397 +// Compute data and tag memory write enables 1.398 +generate 1.399 + if (associativity == 1) 1.400 + begin : we_1 1.401 +assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE)); 1.402 +assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE); 1.403 + end 1.404 + else 1.405 + begin : we_2 1.406 +assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE)); 1.407 +assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE)); 1.408 +assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE); 1.409 +assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE); 1.410 + end 1.411 +endgenerate 1.412 + 1.413 +// On the last refill cycle set the valid bit, for all other writes it should be cleared 1.414 +assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE); 1.415 +assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG]; 1.416 + 1.417 +// Signals that indicate which state we are in 1.418 +assign flushing = state[0]; 1.419 +assign check = state[1]; 1.420 +assign refill = state[2]; 1.421 + 1.422 +assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE); 1.423 +assign stall_request = (check == `FALSE); 1.424 + 1.425 +///////////////////////////////////////////////////// 1.426 +// Sequential logic 1.427 +///////////////////////////////////////////////////// 1.428 + 1.429 +// Record way selected for replacement on a cache miss 1.430 +generate 1.431 + if (associativity >= 2) 1.432 + begin : way_select 1.433 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.434 +begin 1.435 + if (rst_i == `TRUE) 1.436 + refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 1.437 + else 1.438 + begin 1.439 + if (refill_request == `TRUE) 1.440 + refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 1.441 + end 1.442 +end 1.443 + end 1.444 +endgenerate 1.445 + 1.446 +// Record whether we are currently refilling 1.447 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.448 +begin 1.449 + if (rst_i == `TRUE) 1.450 + refilling <= `FALSE; 1.451 + else 1.452 + refilling <= refill; 1.453 +end 1.454 + 1.455 +// Instruction cache control FSM 1.456 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.457 +begin 1.458 + if (rst_i == `TRUE) 1.459 + begin 1.460 + state <= `LM32_DC_STATE_FLUSH; 1.461 + flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 1.462 + refill_request <= `FALSE; 1.463 + refill_address <= {`LM32_WORD_WIDTH{1'bx}}; 1.464 + restart_request <= `FALSE; 1.465 + end 1.466 + else 1.467 + begin 1.468 + case (state) 1.469 + 1.470 + // Flush the cache 1.471 + `LM32_DC_STATE_FLUSH: 1.472 + begin 1.473 + if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}}) 1.474 + state <= `LM32_DC_STATE_CHECK; 1.475 + flush_set <= flush_set - 1'b1; 1.476 + end 1.477 + 1.478 + // Check for cache misses 1.479 + `LM32_DC_STATE_CHECK: 1.480 + begin 1.481 + if (stall_a == `FALSE) 1.482 + restart_request <= `FALSE; 1.483 + if (miss == `TRUE) 1.484 + begin 1.485 + refill_request <= `TRUE; 1.486 + refill_address <= address_m; 1.487 + state <= `LM32_DC_STATE_REFILL; 1.488 + end 1.489 + else if (dflush == `TRUE) 1.490 + state <= `LM32_DC_STATE_FLUSH; 1.491 + end 1.492 + 1.493 + // Refill a cache line 1.494 + `LM32_DC_STATE_REFILL: 1.495 + begin 1.496 + refill_request <= `FALSE; 1.497 + if (refill_ready == `TRUE) 1.498 + begin 1.499 + if (last_refill == `TRUE) 1.500 + begin 1.501 + restart_request <= `TRUE; 1.502 + state <= `LM32_DC_STATE_CHECK; 1.503 + end 1.504 + end 1.505 + end 1.506 + 1.507 + endcase 1.508 + end 1.509 +end 1.510 + 1.511 +generate 1.512 + if (bytes_per_line > 4) 1.513 + begin 1.514 +// Refill offset 1.515 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.516 +begin 1.517 + if (rst_i == `TRUE) 1.518 + refill_offset <= {addr_offset_width{1'b0}}; 1.519 + else 1.520 + begin 1.521 + case (state) 1.522 + 1.523 + // Check for cache misses 1.524 + `LM32_DC_STATE_CHECK: 1.525 + begin 1.526 + if (miss == `TRUE) 1.527 + refill_offset <= {addr_offset_width{1'b0}}; 1.528 + end 1.529 + 1.530 + // Refill a cache line 1.531 + `LM32_DC_STATE_REFILL: 1.532 + begin 1.533 + if (refill_ready == `TRUE) 1.534 + refill_offset <= refill_offset + 1'b1; 1.535 + end 1.536 + 1.537 + endcase 1.538 + end 1.539 +end 1.540 + end 1.541 +endgenerate 1.542 + 1.543 +endmodule 1.544 + 1.545 +`endif 1.546 +