1.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_debug.v 1.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 +++ b/rtl/lm32_debug.v Tue Mar 08 09:40:42 2011 +0000 1.4 @@ -0,0 +1,348 @@ 1.5 +// ============================================================================= 1.6 +// COPYRIGHT NOTICE 1.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 +// ALL RIGHTS RESERVED 1.9 +// This confidential and proprietary software may be used only as authorised by 1.10 +// a licensing agreement from Lattice Semiconductor Corporation. 1.11 +// The entire notice above must be reproduced on all authorized copies and 1.12 +// copies may only be made to the extent permitted by a licensing agreement from 1.13 +// Lattice Semiconductor Corporation. 1.14 +// 1.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 +// U.S.A email: techsupport@latticesemi.com 1.19 +// =============================================================================/ 1.20 +// FILE DETAILS 1.21 +// Project : LatticeMico32 1.22 +// File : lm32_debug.v 1.23 +// Title : Hardware debug registers and associated logic. 1.24 +// Dependencies : lm32_include.v 1.25 +// Version : 6.1.17 1.26 +// : Initial Release 1.27 +// Version : 7.0SP2, 3.0 1.28 +// : No Change 1.29 +// Version : 3.1 1.30 +// : No Change 1.31 +// Version : 3.2 1.32 +// : Fixed simulation bug which flares up when number of 1.33 +// : watchpoints is zero. 1.34 +// ============================================================================= 1.35 + 1.36 +`include "lm32_include.v" 1.37 + 1.38 +`ifdef CFG_DEBUG_ENABLED 1.39 + 1.40 +// States for single-step FSM 1.41 +`define LM32_DEBUG_SS_STATE_RNG 2:0 1.42 +`define LM32_DEBUG_SS_STATE_IDLE 3'b000 1.43 +`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET 3'b001 1.44 +`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN 3'b010 1.45 +`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT 3'b011 1.46 +`define LM32_DEBUG_SS_STATE_RESTART 3'b100 1.47 + 1.48 +///////////////////////////////////////////////////// 1.49 +// Module interface 1.50 +///////////////////////////////////////////////////// 1.51 + 1.52 +module lm32_debug ( 1.53 + // ----- Inputs ------- 1.54 + clk_i, 1.55 + rst_i, 1.56 + pc_x, 1.57 + load_x, 1.58 + store_x, 1.59 + load_store_address_x, 1.60 + csr_write_enable_x, 1.61 + csr_write_data, 1.62 + csr_x, 1.63 +`ifdef CFG_HW_DEBUG_ENABLED 1.64 + jtag_csr_write_enable, 1.65 + jtag_csr_write_data, 1.66 + jtag_csr, 1.67 +`endif 1.68 +`ifdef LM32_SINGLE_STEP_ENABLED 1.69 + eret_q_x, 1.70 + bret_q_x, 1.71 + stall_x, 1.72 + exception_x, 1.73 + q_x, 1.74 +`ifdef CFG_DCACHE_ENABLED 1.75 + dcache_refill_request, 1.76 +`endif 1.77 +`endif 1.78 + // ----- Outputs ------- 1.79 +`ifdef LM32_SINGLE_STEP_ENABLED 1.80 + dc_ss, 1.81 +`endif 1.82 + dc_re, 1.83 + bp_match, 1.84 + wp_match 1.85 + ); 1.86 + 1.87 +///////////////////////////////////////////////////// 1.88 +// Parameters 1.89 +///////////////////////////////////////////////////// 1.90 + 1.91 +parameter breakpoints = 0; // Number of breakpoint CSRs 1.92 +parameter watchpoints = 0; // Number of watchpoint CSRs 1.93 + 1.94 +///////////////////////////////////////////////////// 1.95 +// Inputs 1.96 +///////////////////////////////////////////////////// 1.97 + 1.98 +input clk_i; // Clock 1.99 +input rst_i; // Reset 1.100 + 1.101 +input [`LM32_PC_RNG] pc_x; // X stage PC 1.102 +input load_x; // Load instruction in X stage 1.103 +input store_x; // Store instruction in X stage 1.104 +input [`LM32_WORD_RNG] load_store_address_x; // Load or store effective address 1.105 +input csr_write_enable_x; // wcsr instruction in X stage 1.106 +input [`LM32_WORD_RNG] csr_write_data; // Data to write to CSR 1.107 +input [`LM32_CSR_RNG] csr_x; // Which CSR to write 1.108 +`ifdef CFG_HW_DEBUG_ENABLED 1.109 +input jtag_csr_write_enable; // JTAG interface CSR write enable 1.110 +input [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to CSR 1.111 +input [`LM32_CSR_RNG] jtag_csr; // Which CSR to write 1.112 +`endif 1.113 +`ifdef LM32_SINGLE_STEP_ENABLED 1.114 +input eret_q_x; // eret instruction in X stage 1.115 +input bret_q_x; // bret instruction in X stage 1.116 +input stall_x; // Instruction in X stage is stalled 1.117 +input exception_x; // An exception has occured in X stage 1.118 +input q_x; // Indicates the instruction in the X stage is qualified 1.119 +`ifdef CFG_DCACHE_ENABLED 1.120 +input dcache_refill_request; // Indicates data cache wants to be refilled 1.121 +`endif 1.122 +`endif 1.123 + 1.124 +///////////////////////////////////////////////////// 1.125 +// Outputs 1.126 +///////////////////////////////////////////////////// 1.127 + 1.128 +`ifdef LM32_SINGLE_STEP_ENABLED 1.129 +output dc_ss; // Single-step enable 1.130 +reg dc_ss; 1.131 +`endif 1.132 +output dc_re; // Remap exceptions 1.133 +reg dc_re; 1.134 +output bp_match; // Indicates a breakpoint has matched 1.135 +wire bp_match; 1.136 +output wp_match; // Indicates a watchpoint has matched 1.137 +wire wp_match; 1.138 + 1.139 +///////////////////////////////////////////////////// 1.140 +// Internal nets and registers 1.141 +///////////////////////////////////////////////////// 1.142 + 1.143 +genvar i; // Loop index for generate statements 1.144 + 1.145 +// Debug CSRs 1.146 + 1.147 +reg [`LM32_PC_RNG] bp_a[0:breakpoints-1]; // Instruction breakpoint address 1.148 +reg bp_e[0:breakpoints-1]; // Instruction breakpoint enable 1.149 +wire [0:breakpoints-1]bp_match_n; // Indicates if a h/w instruction breakpoint matched 1.150 + 1.151 +reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1]; // Watchpoint enable 1.152 +reg [`LM32_WORD_RNG] wp[0:watchpoints-1]; // Watchpoint address 1.153 +wire [0:watchpoints]wp_match_n; // Indicates if a h/w data watchpoint matched 1.154 + 1.155 +wire debug_csr_write_enable; // Debug CSR write enable (from either a wcsr instruction of external debugger) 1.156 +wire [`LM32_WORD_RNG] debug_csr_write_data; // Data to write to debug CSR 1.157 +wire [`LM32_CSR_RNG] debug_csr; // Debug CSR to write to 1.158 + 1.159 +`ifdef LM32_SINGLE_STEP_ENABLED 1.160 +// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now 1.161 +//reg [`LM32_DEBUG_SS_STATE_RNG] state; // State of single-step FSM 1.162 +integer state; // State of single-step FSM 1.163 +`endif 1.164 + 1.165 +///////////////////////////////////////////////////// 1.166 +// Functions 1.167 +///////////////////////////////////////////////////// 1.168 + 1.169 +`include "lm32_functions.v" 1.170 + 1.171 +///////////////////////////////////////////////////// 1.172 +// Combinational Logic 1.173 +///////////////////////////////////////////////////// 1.174 + 1.175 +// Check for breakpoints 1.176 +generate 1.177 + for (i = 0; i < breakpoints; i = i + 1) 1.178 + begin : bp_comb 1.179 +assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE)); 1.180 + end 1.181 +endgenerate 1.182 +generate 1.183 +`ifdef LM32_SINGLE_STEP_ENABLED 1.184 + if (breakpoints > 0) 1.185 +assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT); 1.186 + else 1.187 +assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 1.188 +`else 1.189 + if (breakpoints > 0) 1.190 +assign bp_match = |bp_match_n; 1.191 + else 1.192 +assign bp_match = `FALSE; 1.193 +`endif 1.194 +endgenerate 1.195 + 1.196 +// Check for watchpoints 1.197 +generate 1.198 + for (i = 0; i < watchpoints; i = i + 1) 1.199 + begin : wp_comb 1.200 +assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1])); 1.201 + end 1.202 +endgenerate 1.203 +generate 1.204 + if (watchpoints > 0) 1.205 +assign wp_match = |wp_match_n; 1.206 + else 1.207 +assign wp_match = `FALSE; 1.208 +endgenerate 1.209 + 1.210 +`ifdef CFG_HW_DEBUG_ENABLED 1.211 +// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs 1.212 +assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE); 1.213 +assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data; 1.214 +assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x; 1.215 +`else 1.216 +assign debug_csr_write_enable = csr_write_enable_x; 1.217 +assign debug_csr_write_data = csr_write_data; 1.218 +assign debug_csr = csr_x; 1.219 +`endif 1.220 + 1.221 +///////////////////////////////////////////////////// 1.222 +// Sequential Logic 1.223 +///////////////////////////////////////////////////// 1.224 + 1.225 +// Breakpoint address and enable CSRs 1.226 +generate 1.227 + for (i = 0; i < breakpoints; i = i + 1) 1.228 + begin : bp_seq 1.229 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.230 +begin 1.231 + if (rst_i == `TRUE) 1.232 + begin 1.233 + bp_a[i] <= {`LM32_PC_WIDTH{1'bx}}; 1.234 + bp_e[i] <= `FALSE; 1.235 + end 1.236 + else 1.237 + begin 1.238 + if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i)) 1.239 + begin 1.240 + bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG]; 1.241 + bp_e[i] <= debug_csr_write_data[0]; 1.242 + end 1.243 + end 1.244 +end 1.245 + end 1.246 +endgenerate 1.247 + 1.248 +// Watchpoint address and control flags CSRs 1.249 +generate 1.250 + for (i = 0; i < watchpoints; i = i + 1) 1.251 + begin : wp_seq 1.252 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.253 +begin 1.254 + if (rst_i == `TRUE) 1.255 + begin 1.256 + wp[i] <= {`LM32_WORD_WIDTH{1'bx}}; 1.257 + wpc_c[i] <= `LM32_WPC_C_DISABLED; 1.258 + end 1.259 + else 1.260 + begin 1.261 + if (debug_csr_write_enable == `TRUE) 1.262 + begin 1.263 + if (debug_csr == `LM32_CSR_DC) 1.264 + wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; 1.265 + if (debug_csr == `LM32_CSR_WP0 + i) 1.266 + wp[i] <= debug_csr_write_data; 1.267 + end 1.268 + end 1.269 +end 1.270 + end 1.271 +endgenerate 1.272 + 1.273 +// Remap exceptions control bit 1.274 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.275 +begin 1.276 + if (rst_i == `TRUE) 1.277 + dc_re <= `FALSE; 1.278 + else 1.279 + begin 1.280 + if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 1.281 + dc_re <= debug_csr_write_data[1]; 1.282 + end 1.283 +end 1.284 + 1.285 +`ifdef LM32_SINGLE_STEP_ENABLED 1.286 +// Single-step control flag 1.287 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.288 +begin 1.289 + if (rst_i == `TRUE) 1.290 + begin 1.291 + state <= `LM32_DEBUG_SS_STATE_IDLE; 1.292 + dc_ss <= `FALSE; 1.293 + end 1.294 + else 1.295 + begin 1.296 + if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 1.297 + begin 1.298 + dc_ss <= debug_csr_write_data[0]; 1.299 + if (debug_csr_write_data[0] == `FALSE) 1.300 + state <= `LM32_DEBUG_SS_STATE_IDLE; 1.301 + else 1.302 + state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 1.303 + end 1.304 + case (state) 1.305 + `LM32_DEBUG_SS_STATE_WAIT_FOR_RET: 1.306 + begin 1.307 + // Wait for eret or bret instruction to be executed 1.308 + if ( ( (eret_q_x == `TRUE) 1.309 + || (bret_q_x == `TRUE) 1.310 + ) 1.311 + && (stall_x == `FALSE) 1.312 + ) 1.313 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.314 + end 1.315 + `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN: 1.316 + begin 1.317 + // Wait for an instruction to be executed 1.318 + if ((q_x == `TRUE) && (stall_x == `FALSE)) 1.319 + state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 1.320 + end 1.321 + `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT: 1.322 + begin 1.323 + // Wait for exception to be raised 1.324 +`ifdef CFG_DCACHE_ENABLED 1.325 + if (dcache_refill_request == `TRUE) 1.326 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.327 + else 1.328 +`endif 1.329 + if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 1.330 + begin 1.331 + dc_ss <= `FALSE; 1.332 + state <= `LM32_DEBUG_SS_STATE_RESTART; 1.333 + end 1.334 + end 1.335 + `LM32_DEBUG_SS_STATE_RESTART: 1.336 + begin 1.337 + // Watch to see if stepped instruction is restarted due to a cache miss 1.338 +`ifdef CFG_DCACHE_ENABLED 1.339 + if (dcache_refill_request == `TRUE) 1.340 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.341 + else 1.342 +`endif 1.343 + state <= `LM32_DEBUG_SS_STATE_IDLE; 1.344 + end 1.345 + endcase 1.346 + end 1.347 +end 1.348 +`endif 1.349 + 1.350 +endmodule 1.351 + 1.352 +`endif