1.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_decoder.v 1.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 +++ b/rtl/lm32_decoder.v Tue Mar 08 09:40:42 2011 +0000 1.4 @@ -0,0 +1,583 @@ 1.5 +// ============================================================================= 1.6 +// COPYRIGHT NOTICE 1.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 +// ALL RIGHTS RESERVED 1.9 +// This confidential and proprietary software may be used only as authorised by 1.10 +// a licensing agreement from Lattice Semiconductor Corporation. 1.11 +// The entire notice above must be reproduced on all authorized copies and 1.12 +// copies may only be made to the extent permitted by a licensing agreement from 1.13 +// Lattice Semiconductor Corporation. 1.14 +// 1.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 +// U.S.A email: techsupport@latticesemi.com 1.19 +// =============================================================================/ 1.20 +// FILE DETAILS 1.21 +// Project : LatticeMico32 1.22 +// File : lm32_decoder.v 1.23 +// Title : Instruction decoder 1.24 +// Dependencies : lm32_include.v 1.25 +// Version : 6.1.17 1.26 +// : Initial Release 1.27 +// Version : 7.0SP2, 3.0 1.28 +// : No Change 1.29 +// Version : 3.1 1.30 +// : Support for static branch prediction. Information about 1.31 +// : branch type is generated and passed on to the predictor. 1.32 +// Version : 3.2 1.33 +// : No change 1.34 +// Version : 3.3 1.35 +// : Renamed port names that conflict with keywords reserved 1.36 +// : in System-Verilog. 1.37 +// ============================================================================= 1.38 + 1.39 +`include "lm32_include.v" 1.40 + 1.41 +// Index of opcode field in an instruction 1.42 +`define LM32_OPCODE_RNG 31:26 1.43 +`define LM32_OP_RNG 30:26 1.44 + 1.45 +// Opcodes - Some are only listed as 5 bits as their MSB is a don't care 1.46 +`define LM32_OPCODE_ADD 5'b01101 1.47 +`define LM32_OPCODE_AND 5'b01000 1.48 +`define LM32_OPCODE_ANDHI 6'b011000 1.49 +`define LM32_OPCODE_B 6'b110000 1.50 +`define LM32_OPCODE_BI 6'b111000 1.51 +`define LM32_OPCODE_BE 6'b010001 1.52 +`define LM32_OPCODE_BG 6'b010010 1.53 +`define LM32_OPCODE_BGE 6'b010011 1.54 +`define LM32_OPCODE_BGEU 6'b010100 1.55 +`define LM32_OPCODE_BGU 6'b010101 1.56 +`define LM32_OPCODE_BNE 6'b010111 1.57 +`define LM32_OPCODE_CALL 6'b110110 1.58 +`define LM32_OPCODE_CALLI 6'b111110 1.59 +`define LM32_OPCODE_CMPE 5'b11001 1.60 +`define LM32_OPCODE_CMPG 5'b11010 1.61 +`define LM32_OPCODE_CMPGE 5'b11011 1.62 +`define LM32_OPCODE_CMPGEU 5'b11100 1.63 +`define LM32_OPCODE_CMPGU 5'b11101 1.64 +`define LM32_OPCODE_CMPNE 5'b11111 1.65 +`define LM32_OPCODE_DIVU 6'b100011 1.66 +`define LM32_OPCODE_LB 6'b000100 1.67 +`define LM32_OPCODE_LBU 6'b010000 1.68 +`define LM32_OPCODE_LH 6'b000111 1.69 +`define LM32_OPCODE_LHU 6'b001011 1.70 +`define LM32_OPCODE_LW 6'b001010 1.71 +`define LM32_OPCODE_MODU 6'b110001 1.72 +`define LM32_OPCODE_MUL 5'b00010 1.73 +`define LM32_OPCODE_NOR 5'b00001 1.74 +`define LM32_OPCODE_OR 5'b01110 1.75 +`define LM32_OPCODE_ORHI 6'b011110 1.76 +`define LM32_OPCODE_RAISE 6'b101011 1.77 +`define LM32_OPCODE_RCSR 6'b100100 1.78 +`define LM32_OPCODE_SB 6'b001100 1.79 +`define LM32_OPCODE_SEXTB 6'b101100 1.80 +`define LM32_OPCODE_SEXTH 6'b110111 1.81 +`define LM32_OPCODE_SH 6'b000011 1.82 +`define LM32_OPCODE_SL 5'b01111 1.83 +`define LM32_OPCODE_SR 5'b00101 1.84 +`define LM32_OPCODE_SRU 5'b00000 1.85 +`define LM32_OPCODE_SUB 6'b110010 1.86 +`define LM32_OPCODE_SW 6'b010110 1.87 +`define LM32_OPCODE_USER 6'b110011 1.88 +`define LM32_OPCODE_WCSR 6'b110100 1.89 +`define LM32_OPCODE_XNOR 5'b01001 1.90 +`define LM32_OPCODE_XOR 5'b00110 1.91 + 1.92 +///////////////////////////////////////////////////// 1.93 +// Module interface 1.94 +///////////////////////////////////////////////////// 1.95 + 1.96 +module lm32_decoder ( 1.97 + // ----- Inputs ------- 1.98 + instruction, 1.99 + // ----- Outputs ------- 1.100 + d_result_sel_0, 1.101 + d_result_sel_1, 1.102 + x_result_sel_csr, 1.103 +`ifdef LM32_MC_ARITHMETIC_ENABLED 1.104 + x_result_sel_mc_arith, 1.105 +`endif 1.106 +`ifdef LM32_NO_BARREL_SHIFT 1.107 + x_result_sel_shift, 1.108 +`endif 1.109 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.110 + x_result_sel_sext, 1.111 +`endif 1.112 + x_result_sel_logic, 1.113 +`ifdef CFG_USER_ENABLED 1.114 + x_result_sel_user, 1.115 +`endif 1.116 + x_result_sel_add, 1.117 + m_result_sel_compare, 1.118 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.119 + m_result_sel_shift, 1.120 +`endif 1.121 + w_result_sel_load, 1.122 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.123 + w_result_sel_mul, 1.124 +`endif 1.125 + x_bypass_enable, 1.126 + m_bypass_enable, 1.127 + read_enable_0, 1.128 + read_idx_0, 1.129 + read_enable_1, 1.130 + read_idx_1, 1.131 + write_enable, 1.132 + write_idx, 1.133 + immediate, 1.134 + branch_offset, 1.135 + load, 1.136 + store, 1.137 + size, 1.138 + sign_extend, 1.139 + adder_op, 1.140 + logic_op, 1.141 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.142 + direction, 1.143 +`endif 1.144 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.145 + shift_left, 1.146 + shift_right, 1.147 +`endif 1.148 +`ifdef CFG_MC_MULTIPLY_ENABLED 1.149 + multiply, 1.150 +`endif 1.151 +`ifdef CFG_MC_DIVIDE_ENABLED 1.152 + divide, 1.153 + modulus, 1.154 +`endif 1.155 + branch, 1.156 + branch_reg, 1.157 + condition, 1.158 + bi_conditional, 1.159 + bi_unconditional, 1.160 +`ifdef CFG_DEBUG_ENABLED 1.161 + break_opcode, 1.162 +`endif 1.163 + scall, 1.164 + eret, 1.165 +`ifdef CFG_DEBUG_ENABLED 1.166 + bret, 1.167 +`endif 1.168 +`ifdef CFG_USER_ENABLED 1.169 + user_opcode, 1.170 +`endif 1.171 + csr_write_enable 1.172 + ); 1.173 + 1.174 +///////////////////////////////////////////////////// 1.175 +// Inputs 1.176 +///////////////////////////////////////////////////// 1.177 + 1.178 +input [`LM32_INSTRUCTION_RNG] instruction; // Instruction to decode 1.179 + 1.180 +///////////////////////////////////////////////////// 1.181 +// Outputs 1.182 +///////////////////////////////////////////////////// 1.183 + 1.184 +output [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0; 1.185 +reg [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0; 1.186 +output [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1; 1.187 +reg [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1; 1.188 +output x_result_sel_csr; 1.189 +reg x_result_sel_csr; 1.190 +`ifdef LM32_MC_ARITHMETIC_ENABLED 1.191 +output x_result_sel_mc_arith; 1.192 +reg x_result_sel_mc_arith; 1.193 +`endif 1.194 +`ifdef LM32_NO_BARREL_SHIFT 1.195 +output x_result_sel_shift; 1.196 +reg x_result_sel_shift; 1.197 +`endif 1.198 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.199 +output x_result_sel_sext; 1.200 +reg x_result_sel_sext; 1.201 +`endif 1.202 +output x_result_sel_logic; 1.203 +reg x_result_sel_logic; 1.204 +`ifdef CFG_USER_ENABLED 1.205 +output x_result_sel_user; 1.206 +reg x_result_sel_user; 1.207 +`endif 1.208 +output x_result_sel_add; 1.209 +reg x_result_sel_add; 1.210 +output m_result_sel_compare; 1.211 +reg m_result_sel_compare; 1.212 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.213 +output m_result_sel_shift; 1.214 +reg m_result_sel_shift; 1.215 +`endif 1.216 +output w_result_sel_load; 1.217 +reg w_result_sel_load; 1.218 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.219 +output w_result_sel_mul; 1.220 +reg w_result_sel_mul; 1.221 +`endif 1.222 +output x_bypass_enable; 1.223 +wire x_bypass_enable; 1.224 +output m_bypass_enable; 1.225 +wire m_bypass_enable; 1.226 +output read_enable_0; 1.227 +wire read_enable_0; 1.228 +output [`LM32_REG_IDX_RNG] read_idx_0; 1.229 +wire [`LM32_REG_IDX_RNG] read_idx_0; 1.230 +output read_enable_1; 1.231 +wire read_enable_1; 1.232 +output [`LM32_REG_IDX_RNG] read_idx_1; 1.233 +wire [`LM32_REG_IDX_RNG] read_idx_1; 1.234 +output write_enable; 1.235 +wire write_enable; 1.236 +output [`LM32_REG_IDX_RNG] write_idx; 1.237 +wire [`LM32_REG_IDX_RNG] write_idx; 1.238 +output [`LM32_WORD_RNG] immediate; 1.239 +wire [`LM32_WORD_RNG] immediate; 1.240 +output [`LM32_PC_RNG] branch_offset; 1.241 +wire [`LM32_PC_RNG] branch_offset; 1.242 +output load; 1.243 +wire load; 1.244 +output store; 1.245 +wire store; 1.246 +output [`LM32_SIZE_RNG] size; 1.247 +wire [`LM32_SIZE_RNG] size; 1.248 +output sign_extend; 1.249 +wire sign_extend; 1.250 +output adder_op; 1.251 +wire adder_op; 1.252 +output [`LM32_LOGIC_OP_RNG] logic_op; 1.253 +wire [`LM32_LOGIC_OP_RNG] logic_op; 1.254 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.255 +output direction; 1.256 +wire direction; 1.257 +`endif 1.258 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.259 +output shift_left; 1.260 +wire shift_left; 1.261 +output shift_right; 1.262 +wire shift_right; 1.263 +`endif 1.264 +`ifdef CFG_MC_MULTIPLY_ENABLED 1.265 +output multiply; 1.266 +wire multiply; 1.267 +`endif 1.268 +`ifdef CFG_MC_DIVIDE_ENABLED 1.269 +output divide; 1.270 +wire divide; 1.271 +output modulus; 1.272 +wire modulus; 1.273 +`endif 1.274 +output branch; 1.275 +wire branch; 1.276 +output branch_reg; 1.277 +wire branch_reg; 1.278 +output [`LM32_CONDITION_RNG] condition; 1.279 +wire [`LM32_CONDITION_RNG] condition; 1.280 +output bi_conditional; 1.281 +wire bi_conditional; 1.282 +output bi_unconditional; 1.283 +wire bi_unconditional; 1.284 +`ifdef CFG_DEBUG_ENABLED 1.285 +output break_opcode; 1.286 +wire break_opcode; 1.287 +`endif 1.288 +output scall; 1.289 +wire scall; 1.290 +output eret; 1.291 +wire eret; 1.292 +`ifdef CFG_DEBUG_ENABLED 1.293 +output bret; 1.294 +wire bret; 1.295 +`endif 1.296 +`ifdef CFG_USER_ENABLED 1.297 +output [`LM32_USER_OPCODE_RNG] user_opcode; 1.298 +wire [`LM32_USER_OPCODE_RNG] user_opcode; 1.299 +`endif 1.300 +output csr_write_enable; 1.301 +wire csr_write_enable; 1.302 + 1.303 +///////////////////////////////////////////////////// 1.304 +// Internal nets and registers 1.305 +///////////////////////////////////////////////////// 1.306 + 1.307 +wire [`LM32_WORD_RNG] extended_immediate; // Zero or sign extended immediate 1.308 +wire [`LM32_WORD_RNG] high_immediate; // Immediate as high 16 bits 1.309 +wire [`LM32_WORD_RNG] call_immediate; // Call immediate 1.310 +wire [`LM32_WORD_RNG] branch_immediate; // Conditional branch immediate 1.311 +wire sign_extend_immediate; // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE) 1.312 +wire select_high_immediate; // Whether to select the high immediate 1.313 +wire select_call_immediate; // Whether to select the call immediate 1.314 + 1.315 +///////////////////////////////////////////////////// 1.316 +// Functions 1.317 +///////////////////////////////////////////////////// 1.318 + 1.319 +`include "lm32_functions.v" 1.320 + 1.321 +///////////////////////////////////////////////////// 1.322 +// Combinational logic 1.323 +///////////////////////////////////////////////////// 1.324 + 1.325 +// Determine opcode 1.326 +assign op_add = instruction[`LM32_OP_RNG] == `LM32_OPCODE_ADD; 1.327 +assign op_and = instruction[`LM32_OP_RNG] == `LM32_OPCODE_AND; 1.328 +assign op_andhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ANDHI; 1.329 +assign op_b = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_B; 1.330 +assign op_bi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BI; 1.331 +assign op_be = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BE; 1.332 +assign op_bg = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BG; 1.333 +assign op_bge = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGE; 1.334 +assign op_bgeu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGEU; 1.335 +assign op_bgu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGU; 1.336 +assign op_bne = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BNE; 1.337 +assign op_call = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALL; 1.338 +assign op_calli = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALLI; 1.339 +assign op_cmpe = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPE; 1.340 +assign op_cmpg = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPG; 1.341 +assign op_cmpge = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGE; 1.342 +assign op_cmpgeu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGEU; 1.343 +assign op_cmpgu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGU; 1.344 +assign op_cmpne = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPNE; 1.345 +`ifdef CFG_MC_DIVIDE_ENABLED 1.346 +assign op_divu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_DIVU; 1.347 +`endif 1.348 +assign op_lb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LB; 1.349 +assign op_lbu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LBU; 1.350 +assign op_lh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LH; 1.351 +assign op_lhu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LHU; 1.352 +assign op_lw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LW; 1.353 +`ifdef CFG_MC_DIVIDE_ENABLED 1.354 +assign op_modu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_MODU; 1.355 +`endif 1.356 +`ifdef LM32_MULTIPLY_ENABLED 1.357 +assign op_mul = instruction[`LM32_OP_RNG] == `LM32_OPCODE_MUL; 1.358 +`endif 1.359 +assign op_nor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_NOR; 1.360 +assign op_or = instruction[`LM32_OP_RNG] == `LM32_OPCODE_OR; 1.361 +assign op_orhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ORHI; 1.362 +assign op_raise = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RAISE; 1.363 +assign op_rcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RCSR; 1.364 +assign op_sb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SB; 1.365 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.366 +assign op_sextb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTB; 1.367 +assign op_sexth = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH; 1.368 +`endif 1.369 +assign op_sh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH; 1.370 +`ifdef LM32_BARREL_SHIFT_ENABLED 1.371 +assign op_sl = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL; 1.372 +`endif 1.373 +assign op_sr = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR; 1.374 +assign op_sru = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU; 1.375 +assign op_sub = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB; 1.376 +assign op_sw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW; 1.377 +assign op_user = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER; 1.378 +assign op_wcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR; 1.379 +assign op_xnor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR; 1.380 +assign op_xor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR; 1.381 + 1.382 +// Group opcodes by function 1.383 +assign arith = op_add | op_sub; 1.384 +assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor; 1.385 +assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne; 1.386 +assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne; 1.387 +assign bi_unconditional = op_bi; 1.388 +assign bra = op_b | bi_unconditional | bi_conditional; 1.389 +assign call = op_call | op_calli; 1.390 +`ifdef LM32_BARREL_SHIFT_ENABLED 1.391 +assign shift = op_sl | op_sr | op_sru; 1.392 +`endif 1.393 +`ifdef LM32_NO_BARREL_SHIFT 1.394 +assign shift = op_sr | op_sru; 1.395 +`endif 1.396 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.397 +assign shift_left = op_sl; 1.398 +assign shift_right = op_sr | op_sru; 1.399 +`endif 1.400 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.401 +assign sext = op_sextb | op_sexth; 1.402 +`endif 1.403 +`ifdef LM32_MULTIPLY_ENABLED 1.404 +assign multiply = op_mul; 1.405 +`endif 1.406 +`ifdef CFG_MC_DIVIDE_ENABLED 1.407 +assign divide = op_divu; 1.408 +assign modulus = op_modu; 1.409 +`endif 1.410 +assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw; 1.411 +assign store = op_sb | op_sh | op_sw; 1.412 + 1.413 +// Select pipeline multiplexor controls 1.414 +always @(*) 1.415 +begin 1.416 + // D stage 1.417 + if (call) 1.418 + d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC; 1.419 + else 1.420 + d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0; 1.421 + if (call) 1.422 + d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO; 1.423 + else if ((instruction[31] == 1'b0) && !bra) 1.424 + d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE; 1.425 + else 1.426 + d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1; 1.427 + // X stage 1.428 + x_result_sel_csr = `FALSE; 1.429 +`ifdef LM32_MC_ARITHMETIC_ENABLED 1.430 + x_result_sel_mc_arith = `FALSE; 1.431 +`endif 1.432 +`ifdef LM32_NO_BARREL_SHIFT 1.433 + x_result_sel_shift = `FALSE; 1.434 +`endif 1.435 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.436 + x_result_sel_sext = `FALSE; 1.437 +`endif 1.438 + x_result_sel_logic = `FALSE; 1.439 +`ifdef CFG_USER_ENABLED 1.440 + x_result_sel_user = `FALSE; 1.441 +`endif 1.442 + x_result_sel_add = `FALSE; 1.443 + if (op_rcsr) 1.444 + x_result_sel_csr = `TRUE; 1.445 +`ifdef LM32_MC_ARITHMETIC_ENABLED 1.446 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.447 + else if (shift_left | shift_right) 1.448 + x_result_sel_mc_arith = `TRUE; 1.449 +`endif 1.450 +`ifdef CFG_MC_DIVIDE_ENABLED 1.451 + else if (divide | modulus) 1.452 + x_result_sel_mc_arith = `TRUE; 1.453 +`endif 1.454 +`ifdef CFG_MC_MULTIPLY_ENABLED 1.455 + else if (multiply) 1.456 + x_result_sel_mc_arith = `TRUE; 1.457 +`endif 1.458 +`endif 1.459 +`ifdef LM32_NO_BARREL_SHIFT 1.460 + else if (shift) 1.461 + x_result_sel_shift = `TRUE; 1.462 +`endif 1.463 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.464 + else if (sext) 1.465 + x_result_sel_sext = `TRUE; 1.466 +`endif 1.467 + else if (logical) 1.468 + x_result_sel_logic = `TRUE; 1.469 +`ifdef CFG_USER_ENABLED 1.470 + else if (op_user) 1.471 + x_result_sel_user = `TRUE; 1.472 +`endif 1.473 + else 1.474 + x_result_sel_add = `TRUE; 1.475 + 1.476 + // M stage 1.477 + 1.478 + m_result_sel_compare = cmp; 1.479 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.480 + m_result_sel_shift = shift; 1.481 +`endif 1.482 + 1.483 + // W stage 1.484 + w_result_sel_load = load; 1.485 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.486 + w_result_sel_mul = op_mul; 1.487 +`endif 1.488 +end 1.489 + 1.490 +// Set if result is valid at end of X stage 1.491 +assign x_bypass_enable = arith 1.492 + | logical 1.493 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.494 + | shift_left 1.495 + | shift_right 1.496 +`endif 1.497 +`ifdef CFG_MC_MULTIPLY_ENABLED 1.498 + | multiply 1.499 +`endif 1.500 +`ifdef CFG_MC_DIVIDE_ENABLED 1.501 + | divide 1.502 + | modulus 1.503 +`endif 1.504 +`ifdef LM32_NO_BARREL_SHIFT 1.505 + | shift 1.506 +`endif 1.507 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.508 + | sext 1.509 +`endif 1.510 +`ifdef CFG_USER_ENABLED 1.511 + | op_user 1.512 +`endif 1.513 + | op_rcsr 1.514 + ; 1.515 +// Set if result is valid at end of M stage 1.516 +assign m_bypass_enable = x_bypass_enable 1.517 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.518 + | shift 1.519 +`endif 1.520 + | cmp 1.521 + ; 1.522 +// Register file read port 0 1.523 +assign read_enable_0 = ~(op_bi | op_calli); 1.524 +assign read_idx_0 = instruction[25:21]; 1.525 +// Register file read port 1 1.526 +assign read_enable_1 = ~(op_bi | op_calli | load); 1.527 +assign read_idx_1 = instruction[20:16]; 1.528 +// Register file write port 1.529 +assign write_enable = ~(bra | op_raise | store | op_wcsr); 1.530 +assign write_idx = call 1.531 + ? 5'd29 1.532 + : instruction[31] == 1'b0 1.533 + ? instruction[20:16] 1.534 + : instruction[15:11]; 1.535 + 1.536 +// Size of load/stores 1.537 +assign size = instruction[27:26]; 1.538 +// Whether to sign or zero extend 1.539 +assign sign_extend = instruction[28]; 1.540 +// Set adder_op to 1 to perform a subtraction 1.541 +assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra; 1.542 +// Logic operation (and, or, etc) 1.543 +assign logic_op = instruction[29:26]; 1.544 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.545 +// Shift direction 1.546 +assign direction = instruction[29]; 1.547 +`endif 1.548 +// Control flow microcodes 1.549 +assign branch = bra | call; 1.550 +assign branch_reg = op_call | op_b; 1.551 +assign condition = instruction[28:26]; 1.552 +`ifdef CFG_DEBUG_ENABLED 1.553 +assign break_opcode = op_raise & ~instruction[2]; 1.554 +`endif 1.555 +assign scall = op_raise & instruction[2]; 1.556 +assign eret = op_b & (instruction[25:21] == 5'd30); 1.557 +`ifdef CFG_DEBUG_ENABLED 1.558 +assign bret = op_b & (instruction[25:21] == 5'd31); 1.559 +`endif 1.560 +`ifdef CFG_USER_ENABLED 1.561 +// Extract user opcode 1.562 +assign user_opcode = instruction[10:0]; 1.563 +`endif 1.564 +// CSR read/write 1.565 +assign csr_write_enable = op_wcsr; 1.566 + 1.567 +// Extract immediate from instruction 1.568 + 1.569 +assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor); 1.570 +assign select_high_immediate = op_andhi | op_orhi; 1.571 +assign select_call_immediate = instruction[31]; 1.572 + 1.573 +assign high_immediate = {instruction[15:0], 16'h0000}; 1.574 +assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]}; 1.575 +assign call_immediate = {{6{instruction[25]}}, instruction[25:0]}; 1.576 +assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]}; 1.577 + 1.578 +assign immediate = select_high_immediate == `TRUE 1.579 + ? high_immediate 1.580 + : extended_immediate; 1.581 + 1.582 +assign branch_offset = select_call_immediate == `TRUE 1.583 + ? call_immediate 1.584 + : branch_immediate; 1.585 + 1.586 +endmodule 1.587 +