1.1 diff -r 000000000000 -r cd0b58aa6f83 er1.v 1.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 +++ b/er1.v Sun Apr 04 20:40:03 2010 +0100 1.4 @@ -0,0 +1,230 @@ 1.5 +// ============================================================================= 1.6 +// COPYRIGHT NOTICE 1.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 +// ALL RIGHTS RESERVED 1.9 +// This confidential and proprietary software may be used only as authorised by 1.10 +// a licensing agreement from Lattice Semiconductor Corporation. 1.11 +// The entire notice above must be reproduced on all authorized copies and 1.12 +// copies may only be made to the extent permitted by a licensing agreement from 1.13 +// Lattice Semiconductor Corporation. 1.14 +// 1.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 +// U.S.A email: techsupport@latticesemi.com 1.19 +// =============================================================================/ 1.20 +// FILE DETAILS 1.21 +// Project : LatticeMico32 1.22 +// File : er1.v 1.23 +// Description: 1.24 +// This module is where the ER1 register implemented. ER1 and ER2 registers 1.25 +// can be registers implemented in Lattice FPGAs using normal FPGA's 1.26 +// programmable logic resources. Once they are implemented, they can be 1.27 +// accessed as if they are JTAG data registers through the FPGA JTAG port. 1.28 +// In order to accessing these registers, JTAG instructions ER1(0x32) or 1.29 +// ER2(0x38) needs to be written to the JTAG IR register for enabling the 1.30 +// ER1/ER2 accessing logic. The ER1 or ER2 accessing logic can only be 1.31 +// enabled one at a time. Once they are enabled, they will be disabled if 1.32 +// another JTAG instruction is written into the JTAG instruction register. 1.33 +// The registers allow dynamically accessing the FPGA internal information 1.34 +// even when the device is running. Therefore, they are very useful for some 1.35 +// of the IP cores. In order to let ER1/ER2 registers shared by multiple IP 1.36 +// cores or other designs, there is a ER1/ER2 structure patterned by Lattice. 1.37 +// The ER1/ER2 structure allows only one ER1 register but more than one ER2 1.38 +// registers in an FPGA device. Please refer to the related document for 1.39 +// this patterned ER1/ER2 structure. 1.40 +// Dependencies : None 1.41 +// Version : 6.0.14 1.42 +// : Initial Version 1.43 +// Version : 7.0SP2, 3.0 1.44 +// : No Change 1.45 +// Version : 3.1 1.46 +// : No Change 1.47 +// ============================================================================= 1.48 +module ER1 (input JTCK, 1.49 + input JTDI, 1.50 + output JTDO1, 1.51 + output reg JTDO2, 1.52 + input JSHIFT, 1.53 + input JUPDATE, 1.54 + input JRSTN, 1.55 + input JCE1, 1.56 + input [14:0] ER2_TDO, 1.57 + output reg [14:0] IP_ENABLE, 1.58 + input ISPTRACY_ER2_TDO, 1.59 + output ISPTRACY_ENABLE, 1.60 + output CONTROL_DATAN)/* synthesis syn_hier = hard */; 1.61 + 1.62 + 1.63 + wire controlDataNBit; 1.64 + wire ispTracyEnableBit; 1.65 + wire [3:0] encodedIpEnableBits; 1.66 + wire [9:0] er1TdiBit; 1.67 + wire captureDrER1; 1.68 + 1.69 + 1.70 + assign JTDO1 = er1TdiBit[0]; 1.71 + 1.72 + TYPEB BIT0 (.CLK(JTCK), 1.73 + .RESET_N(JRSTN), 1.74 + .CLKEN(JCE1), 1.75 + .TDI(er1TdiBit[1]), 1.76 + .TDO(er1TdiBit[0]), 1.77 + .DATA_IN(1'b0), 1.78 + .CAPTURE_DR(captureDrER1)); 1.79 + 1.80 + TYPEB BIT1 (.CLK(JTCK), 1.81 + .RESET_N(JRSTN), 1.82 + .CLKEN(JCE1), 1.83 + .TDI(er1TdiBit[2]), 1.84 + .TDO(er1TdiBit[1]), 1.85 + .DATA_IN(1'b0), 1.86 + .CAPTURE_DR(captureDrER1)); 1.87 + 1.88 + TYPEB BIT2 (.CLK(JTCK), 1.89 + .RESET_N(JRSTN), 1.90 + .CLKEN(JCE1), 1.91 + .TDI(er1TdiBit[3]), 1.92 + .TDO(er1TdiBit[2]), 1.93 + .DATA_IN(1'b1), 1.94 + .CAPTURE_DR(captureDrER1)); 1.95 + 1.96 + TYPEA BIT3 (.CLK(JTCK), 1.97 + .RESET_N(JRSTN), 1.98 + .CLKEN(JCE1), 1.99 + .TDI(er1TdiBit[4]), 1.100 + .TDO(er1TdiBit[3]), 1.101 + .DATA_OUT(controlDataNBit), 1.102 + .DATA_IN(controlDataNBit), 1.103 + .CAPTURE_DR(captureDrER1), 1.104 + .UPDATE_DR(JUPDATE)); 1.105 + 1.106 + assign CONTROL_DATAN = controlDataNBit; 1.107 + 1.108 + TYPEA BIT4 (.CLK(JTCK), 1.109 + .RESET_N(JRSTN), 1.110 + .CLKEN(JCE1), 1.111 + .TDI(er1TdiBit[5]), 1.112 + .TDO(er1TdiBit[4]), 1.113 + .DATA_OUT(ispTracyEnableBit), 1.114 + .DATA_IN(ispTracyEnableBit), 1.115 + .CAPTURE_DR(captureDrER1), 1.116 + .UPDATE_DR(JUPDATE) 1.117 + ); 1.118 + 1.119 + assign ISPTRACY_ENABLE = ispTracyEnableBit; 1.120 + 1.121 + TYPEA BIT5 (.CLK(JTCK), 1.122 + .RESET_N(JRSTN), 1.123 + .CLKEN(JCE1), 1.124 + .TDI(er1TdiBit[6]), 1.125 + .TDO(er1TdiBit[5]), 1.126 + .DATA_OUT(encodedIpEnableBits[0]), 1.127 + .DATA_IN(encodedIpEnableBits[0]), 1.128 + .CAPTURE_DR(captureDrER1), 1.129 + .UPDATE_DR(JUPDATE)); 1.130 + 1.131 + TYPEA BIT6 (.CLK(JTCK), 1.132 + .RESET_N(JRSTN), 1.133 + .CLKEN(JCE1), 1.134 + .TDI(er1TdiBit[7]), 1.135 + .TDO(er1TdiBit[6]), 1.136 + .DATA_OUT(encodedIpEnableBits[1]), 1.137 + .DATA_IN(encodedIpEnableBits[1]), 1.138 + .CAPTURE_DR(captureDrER1), 1.139 + .UPDATE_DR(JUPDATE)); 1.140 + 1.141 + TYPEA BIT7 (.CLK(JTCK), 1.142 + .RESET_N(JRSTN), 1.143 + .CLKEN(JCE1), 1.144 + .TDI(er1TdiBit[8]), 1.145 + .TDO(er1TdiBit[7]), 1.146 + .DATA_OUT(encodedIpEnableBits[2]), 1.147 + .DATA_IN(encodedIpEnableBits[2]), 1.148 + .CAPTURE_DR(captureDrER1), 1.149 + .UPDATE_DR(JUPDATE)); 1.150 + 1.151 + TYPEA BIT8 (.CLK(JTCK), 1.152 + .RESET_N(JRSTN), 1.153 + .CLKEN(JCE1), 1.154 + .TDI(er1TdiBit[9]), 1.155 + .TDO(er1TdiBit[8]), 1.156 + .DATA_OUT(encodedIpEnableBits[3]), 1.157 + .DATA_IN(encodedIpEnableBits[3]), 1.158 + .CAPTURE_DR(captureDrER1), 1.159 + .UPDATE_DR(JUPDATE) 1.160 + ); 1.161 + 1.162 + assign er1TdiBit[9] = JTDI; 1.163 + assign captureDrER1 = !JSHIFT & JCE1; 1.164 + 1.165 + always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO) 1.166 + begin 1.167 + case (encodedIpEnableBits) 1.168 + 4'h0: begin 1.169 + IP_ENABLE <= 15'b000000000000000; 1.170 + JTDO2 <= ISPTRACY_ER2_TDO; 1.171 + end 1.172 + 4'h1: begin 1.173 + IP_ENABLE <= 15'b000000000000001; 1.174 + JTDO2 <= ER2_TDO[0]; 1.175 + end 1.176 + 4'h2: begin 1.177 + IP_ENABLE <= 15'b000000000000010; 1.178 + JTDO2 <= ER2_TDO[1]; 1.179 + end 1.180 + 4'h3: begin 1.181 + IP_ENABLE <= 15'b000000000000100; 1.182 + JTDO2 <= ER2_TDO[2]; 1.183 + end 1.184 + 4'h4: begin 1.185 + IP_ENABLE <= 15'b000000000001000; 1.186 + JTDO2 <= ER2_TDO[3]; 1.187 + end 1.188 + 4'h5: begin 1.189 + IP_ENABLE <= 15'b000000000010000; 1.190 + JTDO2 <= ER2_TDO[4]; 1.191 + end 1.192 + 4'h6: begin 1.193 + IP_ENABLE <= 15'b000000000100000; 1.194 + JTDO2 <= ER2_TDO[5]; 1.195 + end 1.196 + 4'h7: begin 1.197 + IP_ENABLE <= 15'b000000001000000; 1.198 + JTDO2 <= ER2_TDO[6]; 1.199 + end 1.200 + 4'h8: begin 1.201 + IP_ENABLE <= 15'b000000010000000; 1.202 + JTDO2 <= ER2_TDO[7]; 1.203 + end 1.204 + 4'h9: begin 1.205 + IP_ENABLE <= 15'b000000100000000; 1.206 + JTDO2 <= ER2_TDO[8]; 1.207 + end 1.208 + 4'hA: begin 1.209 + IP_ENABLE <= 15'b000001000000000; 1.210 + JTDO2 <= ER2_TDO[9]; 1.211 + end 1.212 + 4'hB: begin 1.213 + IP_ENABLE <= 15'b000010000000000; 1.214 + JTDO2 <= ER2_TDO[10]; 1.215 + end 1.216 + 4'hC: begin 1.217 + IP_ENABLE <= 15'b000100000000000; 1.218 + JTDO2 <= ER2_TDO[11]; 1.219 + end 1.220 + 4'hD: begin 1.221 + IP_ENABLE <= 15'b001000000000000; 1.222 + JTDO2 <= ER2_TDO[12]; 1.223 + end 1.224 + 4'hE: begin 1.225 + IP_ENABLE <= 15'b010000000000000; 1.226 + JTDO2 <= ER2_TDO[13]; 1.227 + end 1.228 + 4'hF: begin 1.229 + IP_ENABLE <= 15'b100000000000000; 1.230 + JTDO2 <= ER2_TDO[14]; 1.231 + end 1.232 + endcase 1.233 + end 1.234 +endmodule