1.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_cpu.v 1.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 +++ b/lm32_cpu.v Sun Apr 04 20:40:03 2010 +0100 1.4 @@ -0,0 +1,2732 @@ 1.5 +// ============================================================================= 1.6 +// COPYRIGHT NOTICE 1.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 +// ALL RIGHTS RESERVED 1.9 +// This confidential and proprietary software may be used only as authorised by 1.10 +// a licensing agreement from Lattice Semiconductor Corporation. 1.11 +// The entire notice above must be reproduced on all authorized copies and 1.12 +// copies may only be made to the extent permitted by a licensing agreement from 1.13 +// Lattice Semiconductor Corporation. 1.14 +// 1.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 +// U.S.A email: techsupport@latticesemi.com 1.19 +// =============================================================================/ 1.20 +// FILE DETAILS 1.21 +// Project : LatticeMico32 1.22 +// File : lm32_cpu.v 1.23 +// Title : Top-level of CPU. 1.24 +// Dependencies : lm32_include.v 1.25 +// 1.26 +// Version 3.4 1.27 +// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 1.28 +// never serviced. 1.29 +// 1.30 +// Version 3.3 1.31 +// 1. Feature: Support for memory that is tightly coupled to processor core, and 1.32 +// has a single-cycle access latency (same as caches). Instruction port has 1.33 +// access to a dedicated physically-mapped memory. Data port has access to 1.34 +// a dedicated physically-mapped memory. In order to be able to manipulate 1.35 +// values in both these memories via the debugger, these memories also 1.36 +// interface with the data port of LM32. 1.37 +// 2. Feature: Extended Configuration Register 1.38 +// 3. Bug Fix: Removed port names that conflict with keywords reserved in System- 1.39 +// Verilog. 1.40 +// 1.41 +// Version 3.2 1.42 +// 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to 1.43 +// hang. At the same time CPU fails to register data bus error exception. Bug 1.44 +// is caused because (a) data bus error exception occurs after load/store has 1.45 +// passed X stage and next sequential instruction (e.g., brk) is already in X 1.46 +// stage, and (b) data bus error exception had lower priority than, say, brk 1.47 +// exception. 1.48 +// 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to 1.49 +// invalid location, CPU will fail to register data bus error exception. The 1.50 +// solution is to stall scall/eret/bret/brk instructions in D pipeline stage 1.51 +// until load/store has completed. 1.52 +// 3. Feature: Enable precise identification of load/store that causes seg fault. 1.53 +// 4. SYNC resets used for register file when implemented in EBRs. 1.54 +// 1.55 +// Version 3.1 1.56 +// 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR) 1.57 +// instead of distributed memory by enabling the option in LM32 GUI. 1.58 +// 2. Feature: LM32 also adds a static branch predictor to improve branch 1.59 +// performance. All immediate-based forward-pointing branches are predicted 1.60 +// not-taken. All immediate-based backward-pointing branches are predicted taken. 1.61 +// 1.62 +// Version 7.0SP2, 3.0 1.63 +// No Change 1.64 +// 1.65 +// Version 6.1.17 1.66 +// Initial Release 1.67 +// ============================================================================= 1.68 + 1.69 +`include "lm32_include.v" 1.70 + 1.71 +///////////////////////////////////////////////////// 1.72 +// Module interface 1.73 +///////////////////////////////////////////////////// 1.74 + 1.75 +module lm32_cpu ( 1.76 + // ----- Inputs ------- 1.77 + clk_i, 1.78 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 1.79 + clk_n_i, 1.80 +`endif 1.81 + rst_i, 1.82 + // From external devices 1.83 +`ifdef CFG_INTERRUPTS_ENABLED 1.84 + interrupt_n, 1.85 +`endif 1.86 + // From user logic 1.87 +`ifdef CFG_USER_ENABLED 1.88 + user_result, 1.89 + user_complete, 1.90 +`endif 1.91 +`ifdef CFG_JTAG_ENABLED 1.92 + // From JTAG 1.93 + jtag_clk, 1.94 + jtag_update, 1.95 + jtag_reg_q, 1.96 + jtag_reg_addr_q, 1.97 +`endif 1.98 +`ifdef CFG_IWB_ENABLED 1.99 + // Instruction Wishbone master 1.100 + I_DAT_I, 1.101 + I_ACK_I, 1.102 + I_ERR_I, 1.103 + I_RTY_I, 1.104 +`endif 1.105 + // Data Wishbone master 1.106 + D_DAT_I, 1.107 + D_ACK_I, 1.108 + D_ERR_I, 1.109 + D_RTY_I, 1.110 + // ----- Outputs ------- 1.111 +`ifdef CFG_TRACE_ENABLED 1.112 + trace_pc, 1.113 + trace_pc_valid, 1.114 + trace_exception, 1.115 + trace_eid, 1.116 + trace_eret, 1.117 +`ifdef CFG_DEBUG_ENABLED 1.118 + trace_bret, 1.119 +`endif 1.120 +`endif 1.121 +`ifdef CFG_JTAG_ENABLED 1.122 + jtag_reg_d, 1.123 + jtag_reg_addr_d, 1.124 +`endif 1.125 +`ifdef CFG_USER_ENABLED 1.126 + user_valid, 1.127 + user_opcode, 1.128 + user_operand_0, 1.129 + user_operand_1, 1.130 +`endif 1.131 +`ifdef CFG_IWB_ENABLED 1.132 + // Instruction Wishbone master 1.133 + I_DAT_O, 1.134 + I_ADR_O, 1.135 + I_CYC_O, 1.136 + I_SEL_O, 1.137 + I_STB_O, 1.138 + I_WE_O, 1.139 + I_CTI_O, 1.140 + I_LOCK_O, 1.141 + I_BTE_O, 1.142 +`endif 1.143 + // Data Wishbone master 1.144 + D_DAT_O, 1.145 + D_ADR_O, 1.146 + D_CYC_O, 1.147 + D_SEL_O, 1.148 + D_STB_O, 1.149 + D_WE_O, 1.150 + D_CTI_O, 1.151 + D_LOCK_O, 1.152 + D_BTE_O 1.153 + ); 1.154 + 1.155 +///////////////////////////////////////////////////// 1.156 +// Parameters 1.157 +///////////////////////////////////////////////////// 1.158 + 1.159 +parameter eba_reset = `CFG_EBA_RESET; // Reset value for EBA CSR 1.160 +`ifdef CFG_DEBUG_ENABLED 1.161 +parameter deba_reset = `CFG_DEBA_RESET; // Reset value for DEBA CSR 1.162 +`endif 1.163 + 1.164 +`ifdef CFG_ICACHE_ENABLED 1.165 +parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways) 1.166 +parameter icache_sets = `CFG_ICACHE_SETS; // Number of sets 1.167 +parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE; // Number of bytes per cache line 1.168 +parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS; // Base address of cachable memory 1.169 +parameter icache_limit = `CFG_ICACHE_LIMIT; // Limit (highest address) of cachable memory 1.170 +`else 1.171 +parameter icache_associativity = 1; 1.172 +parameter icache_sets = 512; 1.173 +parameter icache_bytes_per_line = 16; 1.174 +parameter icache_base_address = 0; 1.175 +parameter icache_limit = 0; 1.176 +`endif 1.177 + 1.178 +`ifdef CFG_DCACHE_ENABLED 1.179 +parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways) 1.180 +parameter dcache_sets = `CFG_DCACHE_SETS; // Number of sets 1.181 +parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE; // Number of bytes per cache line 1.182 +parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS; // Base address of cachable memory 1.183 +parameter dcache_limit = `CFG_DCACHE_LIMIT; // Limit (highest address) of cachable memory 1.184 +`else 1.185 +parameter dcache_associativity = 1; 1.186 +parameter dcache_sets = 512; 1.187 +parameter dcache_bytes_per_line = 16; 1.188 +parameter dcache_base_address = 0; 1.189 +parameter dcache_limit = 0; 1.190 +`endif 1.191 + 1.192 +`ifdef CFG_DEBUG_ENABLED 1.193 +parameter watchpoints = `CFG_WATCHPOINTS; // Number of h/w watchpoint CSRs 1.194 +`else 1.195 +parameter watchpoints = 0; 1.196 +`endif 1.197 +`ifdef CFG_ROM_DEBUG_ENABLED 1.198 +parameter breakpoints = `CFG_BREAKPOINTS; // Number of h/w breakpoint CSRs 1.199 +`else 1.200 +parameter breakpoints = 0; 1.201 +`endif 1.202 + 1.203 +`ifdef CFG_INTERRUPTS_ENABLED 1.204 +parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts 1.205 +`else 1.206 +parameter interrupts = 0; 1.207 +`endif 1.208 + 1.209 +///////////////////////////////////////////////////// 1.210 +// Inputs 1.211 +///////////////////////////////////////////////////// 1.212 + 1.213 +input clk_i; // Clock 1.214 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 1.215 +input clk_n_i; // Inverted clock 1.216 +`endif 1.217 +input rst_i; // Reset 1.218 + 1.219 +`ifdef CFG_INTERRUPTS_ENABLED 1.220 +input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low 1.221 +`endif 1.222 + 1.223 +`ifdef CFG_USER_ENABLED 1.224 +input [`LM32_WORD_RNG] user_result; // User-defined instruction result 1.225 +input user_complete; // User-defined instruction execution is complete 1.226 +`endif 1.227 + 1.228 +`ifdef CFG_JTAG_ENABLED 1.229 +input jtag_clk; // JTAG clock 1.230 +input jtag_update; // JTAG state machine is in data register update state 1.231 +input [`LM32_BYTE_RNG] jtag_reg_q; 1.232 +input [2:0] jtag_reg_addr_q; 1.233 +`endif 1.234 + 1.235 +`ifdef CFG_IWB_ENABLED 1.236 +input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data 1.237 +input I_ACK_I; // Instruction Wishbone interface acknowledgement 1.238 +input I_ERR_I; // Instruction Wishbone interface error 1.239 +input I_RTY_I; // Instruction Wishbone interface retry 1.240 +`endif 1.241 + 1.242 +input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data 1.243 +input D_ACK_I; // Data Wishbone interface acknowledgement 1.244 +input D_ERR_I; // Data Wishbone interface error 1.245 +input D_RTY_I; // Data Wishbone interface retry 1.246 + 1.247 +///////////////////////////////////////////////////// 1.248 +// Outputs 1.249 +///////////////////////////////////////////////////// 1.250 + 1.251 +`ifdef CFG_TRACE_ENABLED 1.252 +output [`LM32_PC_RNG] trace_pc; // PC to trace 1.253 +reg [`LM32_PC_RNG] trace_pc; 1.254 +output trace_pc_valid; // Indicates that a new trace PC is valid 1.255 +reg trace_pc_valid; 1.256 +output trace_exception; // Indicates an exception has occured 1.257 +reg trace_exception; 1.258 +output [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured 1.259 +reg [`LM32_EID_RNG] trace_eid; 1.260 +output trace_eret; // Indicates an eret instruction has been executed 1.261 +reg trace_eret; 1.262 +`ifdef CFG_DEBUG_ENABLED 1.263 +output trace_bret; // Indicates a bret instruction has been executed 1.264 +reg trace_bret; 1.265 +`endif 1.266 +`endif 1.267 + 1.268 +`ifdef CFG_JTAG_ENABLED 1.269 +output [`LM32_BYTE_RNG] jtag_reg_d; 1.270 +wire [`LM32_BYTE_RNG] jtag_reg_d; 1.271 +output [2:0] jtag_reg_addr_d; 1.272 +wire [2:0] jtag_reg_addr_d; 1.273 +`endif 1.274 + 1.275 +`ifdef CFG_USER_ENABLED 1.276 +output user_valid; // Indicates if user_opcode is valid 1.277 +wire user_valid; 1.278 +output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode 1.279 +reg [`LM32_USER_OPCODE_RNG] user_opcode; 1.280 +output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction 1.281 +wire [`LM32_WORD_RNG] user_operand_0; 1.282 +output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction 1.283 +wire [`LM32_WORD_RNG] user_operand_1; 1.284 +`endif 1.285 + 1.286 +`ifdef CFG_IWB_ENABLED 1.287 +output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data 1.288 +wire [`LM32_WORD_RNG] I_DAT_O; 1.289 +output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address 1.290 +wire [`LM32_WORD_RNG] I_ADR_O; 1.291 +output I_CYC_O; // Instruction Wishbone interface cycle 1.292 +wire I_CYC_O; 1.293 +output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select 1.294 +wire [`LM32_BYTE_SELECT_RNG] I_SEL_O; 1.295 +output I_STB_O; // Instruction Wishbone interface strobe 1.296 +wire I_STB_O; 1.297 +output I_WE_O; // Instruction Wishbone interface write enable 1.298 +wire I_WE_O; 1.299 +output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type 1.300 +wire [`LM32_CTYPE_RNG] I_CTI_O; 1.301 +output I_LOCK_O; // Instruction Wishbone interface lock bus 1.302 +wire I_LOCK_O; 1.303 +output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type 1.304 +wire [`LM32_BTYPE_RNG] I_BTE_O; 1.305 +`endif 1.306 + 1.307 +output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data 1.308 +wire [`LM32_WORD_RNG] D_DAT_O; 1.309 +output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address 1.310 +wire [`LM32_WORD_RNG] D_ADR_O; 1.311 +output D_CYC_O; // Data Wishbone interface cycle 1.312 +wire D_CYC_O; 1.313 +output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select 1.314 +wire [`LM32_BYTE_SELECT_RNG] D_SEL_O; 1.315 +output D_STB_O; // Data Wishbone interface strobe 1.316 +wire D_STB_O; 1.317 +output D_WE_O; // Data Wishbone interface write enable 1.318 +wire D_WE_O; 1.319 +output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type 1.320 +wire [`LM32_CTYPE_RNG] D_CTI_O; 1.321 +output D_LOCK_O; // Date Wishbone interface lock bus 1.322 +wire D_LOCK_O; 1.323 +output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type 1.324 +wire [`LM32_BTYPE_RNG] D_BTE_O; 1.325 + 1.326 +///////////////////////////////////////////////////// 1.327 +// Internal nets and registers 1.328 +///////////////////////////////////////////////////// 1.329 + 1.330 +// Pipeline registers 1.331 + 1.332 +`ifdef LM32_CACHE_ENABLED 1.333 +reg valid_a; // Instruction in A stage is valid 1.334 +`endif 1.335 +reg valid_f; // Instruction in F stage is valid 1.336 +reg valid_d; // Instruction in D stage is valid 1.337 +reg valid_x; // Instruction in X stage is valid 1.338 +reg valid_m; // Instruction in M stage is valid 1.339 +reg valid_w; // Instruction in W stage is valid 1.340 + 1.341 +wire q_x; 1.342 +wire [`LM32_WORD_RNG] immediate_d; // Immediate operand 1.343 +wire load_d; // Indicates a load instruction 1.344 +reg load_x; 1.345 +reg load_m; 1.346 +wire load_q_x; 1.347 +wire store_q_x; 1.348 +wire store_d; // Indicates a store instruction 1.349 +reg store_x; 1.350 +reg store_m; 1.351 +wire [`LM32_SIZE_RNG] size_d; // Size of load/store (byte, hword, word) 1.352 +reg [`LM32_SIZE_RNG] size_x; 1.353 +wire branch_d; // Indicates a branch instruction 1.354 +wire branch_predict_d; // Indicates a branch is predicted 1.355 +wire branch_predict_taken_d; // Indicates a branch is predicted taken 1.356 +wire [`LM32_PC_RNG] branch_predict_address_d; // Address to which predicted branch jumps 1.357 +wire [`LM32_PC_RNG] branch_target_d; 1.358 +wire bi_unconditional; 1.359 +wire bi_conditional; 1.360 +reg branch_x; 1.361 +reg branch_predict_x; 1.362 +reg branch_predict_taken_x; 1.363 +reg branch_m; 1.364 +reg branch_predict_m; 1.365 +reg branch_predict_taken_m; 1.366 +wire branch_mispredict_taken_m; // Indicates a branch was mispredicted as taken 1.367 +wire branch_flushX_m; // Indicates that instruction in X stage must be squashed 1.368 +wire branch_reg_d; // Branch to register or immediate 1.369 +wire [`LM32_PC_RNG] branch_offset_d; // Branch offset for immediate branches 1.370 +reg [`LM32_PC_RNG] branch_target_x; // Address to branch to 1.371 +reg [`LM32_PC_RNG] branch_target_m; 1.372 +wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0 1.373 +wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1 1.374 + 1.375 +wire x_result_sel_csr_d; // Select X stage result from CSRs 1.376 +reg x_result_sel_csr_x; 1.377 +`ifdef LM32_MC_ARITHMETIC_ENABLED 1.378 +wire x_result_sel_mc_arith_d; // Select X stage result from multi-cycle arithmetic unit 1.379 +reg x_result_sel_mc_arith_x; 1.380 +`endif 1.381 +`ifdef LM32_NO_BARREL_SHIFT 1.382 +wire x_result_sel_shift_d; // Select X stage result from shifter 1.383 +reg x_result_sel_shift_x; 1.384 +`endif 1.385 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.386 +wire x_result_sel_sext_d; // Select X stage result from sign-extend logic 1.387 +reg x_result_sel_sext_x; 1.388 +`endif 1.389 +wire x_result_sel_logic_d; // Select X stage result from logic op unit 1.390 +reg x_result_sel_logic_x; 1.391 +`ifdef CFG_USER_ENABLED 1.392 +wire x_result_sel_user_d; // Select X stage result from user-defined logic 1.393 +reg x_result_sel_user_x; 1.394 +`endif 1.395 +wire x_result_sel_add_d; // Select X stage result from adder 1.396 +reg x_result_sel_add_x; 1.397 +wire m_result_sel_compare_d; // Select M stage result from comparison logic 1.398 +reg m_result_sel_compare_x; 1.399 +reg m_result_sel_compare_m; 1.400 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.401 +wire m_result_sel_shift_d; // Select M stage result from shifter 1.402 +reg m_result_sel_shift_x; 1.403 +reg m_result_sel_shift_m; 1.404 +`endif 1.405 +wire w_result_sel_load_d; // Select W stage result from load/store unit 1.406 +reg w_result_sel_load_x; 1.407 +reg w_result_sel_load_m; 1.408 +reg w_result_sel_load_w; 1.409 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.410 +wire w_result_sel_mul_d; // Select W stage result from multiplier 1.411 +reg w_result_sel_mul_x; 1.412 +reg w_result_sel_mul_m; 1.413 +reg w_result_sel_mul_w; 1.414 +`endif 1.415 +wire x_bypass_enable_d; // Whether result is bypassable in X stage 1.416 +reg x_bypass_enable_x; 1.417 +wire m_bypass_enable_d; // Whether result is bypassable in M stage 1.418 +reg m_bypass_enable_x; 1.419 +reg m_bypass_enable_m; 1.420 +wire sign_extend_d; // Whether to sign-extend or zero-extend 1.421 +reg sign_extend_x; 1.422 +wire write_enable_d; // Register file write enable 1.423 +reg write_enable_x; 1.424 +wire write_enable_q_x; 1.425 +reg write_enable_m; 1.426 +wire write_enable_q_m; 1.427 +reg write_enable_w; 1.428 +wire write_enable_q_w; 1.429 +wire read_enable_0_d; // Register file read enable 0 1.430 +wire [`LM32_REG_IDX_RNG] read_idx_0_d; // Register file read index 0 1.431 +wire read_enable_1_d; // Register file read enable 1 1.432 +wire [`LM32_REG_IDX_RNG] read_idx_1_d; // Register file read index 1 1.433 +wire [`LM32_REG_IDX_RNG] write_idx_d; // Register file write index 1.434 +reg [`LM32_REG_IDX_RNG] write_idx_x; 1.435 +reg [`LM32_REG_IDX_RNG] write_idx_m; 1.436 +reg [`LM32_REG_IDX_RNG] write_idx_w; 1.437 +wire [`LM32_CSR_RNG] csr_d; // CSR read/write index 1.438 +reg [`LM32_CSR_RNG] csr_x; 1.439 +wire [`LM32_CONDITION_RNG] condition_d; // Branch condition 1.440 +reg [`LM32_CONDITION_RNG] condition_x; 1.441 +`ifdef CFG_DEBUG_ENABLED 1.442 +wire break_d; // Indicates a break instruction 1.443 +reg break_x; 1.444 +`endif 1.445 +wire scall_d; // Indicates a scall instruction 1.446 +reg scall_x; 1.447 +wire eret_d; // Indicates an eret instruction 1.448 +reg eret_x; 1.449 +wire eret_q_x; 1.450 +reg eret_m; 1.451 +`ifdef CFG_TRACE_ENABLED 1.452 +reg eret_w; 1.453 +`endif 1.454 +`ifdef CFG_DEBUG_ENABLED 1.455 +wire bret_d; // Indicates a bret instruction 1.456 +reg bret_x; 1.457 +wire bret_q_x; 1.458 +reg bret_m; 1.459 +`ifdef CFG_TRACE_ENABLED 1.460 +reg bret_w; 1.461 +`endif 1.462 +`endif 1.463 +wire csr_write_enable_d; // CSR write enable 1.464 +reg csr_write_enable_x; 1.465 +wire csr_write_enable_q_x; 1.466 +`ifdef CFG_USER_ENABLED 1.467 +wire [`LM32_USER_OPCODE_RNG] user_opcode_d; // User-defined instruction opcode 1.468 +`endif 1.469 + 1.470 +`ifdef CFG_BUS_ERRORS_ENABLED 1.471 +wire bus_error_d; // Indicates an bus error occured while fetching the instruction in this pipeline stage 1.472 +reg bus_error_x; 1.473 +reg data_bus_error_exception_m; 1.474 +reg [`LM32_PC_RNG] memop_pc_w; 1.475 +`endif 1.476 + 1.477 +reg [`LM32_WORD_RNG] d_result_0; // Result of instruction in D stage (operand 0) 1.478 +reg [`LM32_WORD_RNG] d_result_1; // Result of instruction in D stage (operand 1) 1.479 +reg [`LM32_WORD_RNG] x_result; // Result of instruction in X stage 1.480 +reg [`LM32_WORD_RNG] m_result; // Result of instruction in M stage 1.481 +reg [`LM32_WORD_RNG] w_result; // Result of instruction in W stage 1.482 + 1.483 +reg [`LM32_WORD_RNG] operand_0_x; // Operand 0 for X stage instruction 1.484 +reg [`LM32_WORD_RNG] operand_1_x; // Operand 1 for X stage instruction 1.485 +reg [`LM32_WORD_RNG] store_operand_x; // Data read from register to store 1.486 +reg [`LM32_WORD_RNG] operand_m; // Operand for M stage instruction 1.487 +reg [`LM32_WORD_RNG] operand_w; // Operand for W stage instruction 1.488 + 1.489 +// To/from register file 1.490 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.491 +reg [`LM32_WORD_RNG] reg_data_live_0; 1.492 +reg [`LM32_WORD_RNG] reg_data_live_1; 1.493 +reg use_buf; // Whether to use reg_data_live or reg_data_buf 1.494 +reg [`LM32_WORD_RNG] reg_data_buf_0; 1.495 +reg [`LM32_WORD_RNG] reg_data_buf_1; 1.496 +`endif 1.497 +`ifdef LM32_EBR_REGISTER_FILE 1.498 +`else 1.499 +reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1]; // Register file 1.500 +`endif 1.501 +wire [`LM32_WORD_RNG] reg_data_0; // Register file read port 0 data 1.502 +wire [`LM32_WORD_RNG] reg_data_1; // Register file read port 1 data 1.503 +reg [`LM32_WORD_RNG] bypass_data_0; // Register value 0 after bypassing 1.504 +reg [`LM32_WORD_RNG] bypass_data_1; // Register value 1 after bypassing 1.505 +wire reg_write_enable_q_w; 1.506 + 1.507 +reg interlock; // Indicates pipeline should be stalled because of a read-after-write hazzard 1.508 + 1.509 +wire stall_a; // Stall instruction in A pipeline stage 1.510 +wire stall_f; // Stall instruction in F pipeline stage 1.511 +wire stall_d; // Stall instruction in D pipeline stage 1.512 +wire stall_x; // Stall instruction in X pipeline stage 1.513 +wire stall_m; // Stall instruction in M pipeline stage 1.514 + 1.515 +// To/from adder 1.516 +wire adder_op_d; // Whether to add or subtract 1.517 +reg adder_op_x; 1.518 +reg adder_op_x_n; // Inverted version of adder_op_x 1.519 +wire [`LM32_WORD_RNG] adder_result_x; // Result from adder 1.520 +wire adder_overflow_x; // Whether a signed overflow occured 1.521 +wire adder_carry_n_x; // Whether a carry was generated 1.522 + 1.523 +// To/from logical operations unit 1.524 +wire [`LM32_LOGIC_OP_RNG] logic_op_d; // Which operation to perform 1.525 +reg [`LM32_LOGIC_OP_RNG] logic_op_x; 1.526 +wire [`LM32_WORD_RNG] logic_result_x; // Result of logical operation 1.527 + 1.528 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.529 +// From sign-extension unit 1.530 +wire [`LM32_WORD_RNG] sextb_result_x; // Result of byte sign-extension 1.531 +wire [`LM32_WORD_RNG] sexth_result_x; // Result of half-word sign-extenstion 1.532 +wire [`LM32_WORD_RNG] sext_result_x; // Result of sign-extension specified by instruction 1.533 +`endif 1.534 + 1.535 +// To/from shifter 1.536 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.537 +`ifdef CFG_ROTATE_ENABLED 1.538 +wire rotate_d; // Whether we should rotate or shift 1.539 +reg rotate_x; 1.540 +`endif 1.541 +wire direction_d; // Which direction to shift in 1.542 +reg direction_x; 1.543 +reg direction_m; 1.544 +wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter 1.545 +`endif 1.546 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.547 +wire shift_left_d; // Indicates whether to perform a left shift or not 1.548 +wire shift_left_q_d; 1.549 +wire shift_right_d; // Indicates whether to perform a right shift or not 1.550 +wire shift_right_q_d; 1.551 +`endif 1.552 +`ifdef LM32_NO_BARREL_SHIFT 1.553 +wire [`LM32_WORD_RNG] shifter_result_x; // Result of single-bit right shifter 1.554 +`endif 1.555 + 1.556 +// To/from multiplier 1.557 +`ifdef LM32_MULTIPLY_ENABLED 1.558 +wire [`LM32_WORD_RNG] multiplier_result_w; // Result from multiplier 1.559 +`endif 1.560 +`ifdef CFG_MC_MULTIPLY_ENABLED 1.561 +wire multiply_d; // Indicates whether to perform a multiply or not 1.562 +wire multiply_q_d; 1.563 +`endif 1.564 + 1.565 +// To/from divider 1.566 +`ifdef CFG_MC_DIVIDE_ENABLED 1.567 +wire divide_d; // Indicates whether to perform a divider or not 1.568 +wire divide_q_d; 1.569 +wire modulus_d; 1.570 +wire modulus_q_d; 1.571 +wire divide_by_zero_x; // Indicates an attempt was made to divide by zero 1.572 +`endif 1.573 + 1.574 +// To from multi-cycle arithmetic unit 1.575 +`ifdef LM32_MC_ARITHMETIC_ENABLED 1.576 +wire mc_stall_request_x; // Multi-cycle arithmetic unit stall request 1.577 +wire [`LM32_WORD_RNG] mc_result_x; 1.578 +`endif 1.579 + 1.580 +// From CSRs 1.581 +`ifdef CFG_INTERRUPTS_ENABLED 1.582 +wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs 1.583 +`endif 1.584 +wire [`LM32_WORD_RNG] cfg; // Configuration CSR 1.585 +wire [`LM32_WORD_RNG] cfg2; // Extended Configuration CSR 1.586 +`ifdef CFG_CYCLE_COUNTER_ENABLED 1.587 +reg [`LM32_WORD_RNG] cc; // Cycle counter CSR 1.588 +`endif 1.589 +reg [`LM32_WORD_RNG] csr_read_data_x; // Data read from CSRs 1.590 + 1.591 +// To/from instruction unit 1.592 +wire [`LM32_PC_RNG] pc_f; // PC of instruction in F stage 1.593 +wire [`LM32_PC_RNG] pc_d; // PC of instruction in D stage 1.594 +wire [`LM32_PC_RNG] pc_x; // PC of instruction in X stage 1.595 +wire [`LM32_PC_RNG] pc_m; // PC of instruction in M stage 1.596 +wire [`LM32_PC_RNG] pc_w; // PC of instruction in W stage 1.597 +`ifdef CFG_TRACE_ENABLED 1.598 +reg [`LM32_PC_RNG] pc_c; // PC of last commited instruction 1.599 +`endif 1.600 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.601 +wire [`LM32_INSTRUCTION_RNG] instruction_f; // Instruction in F stage 1.602 +`endif 1.603 +//pragma attribute instruction_d preserve_signal true 1.604 +//pragma attribute instruction_d preserve_driver true 1.605 +wire [`LM32_INSTRUCTION_RNG] instruction_d; // Instruction in D stage 1.606 +`ifdef CFG_ICACHE_ENABLED 1.607 +wire iflush; // Flush instruction cache 1.608 +wire icache_stall_request; // Stall pipeline because instruction cache is busy 1.609 +wire icache_restart_request; // Restart instruction that caused an instruction cache miss 1.610 +wire icache_refill_request; // Request to refill instruction cache 1.611 +wire icache_refilling; // Indicates the instruction cache is being refilled 1.612 +`endif 1.613 +`ifdef CFG_IROM_ENABLED 1.614 +wire [`LM32_WORD_RNG] irom_store_data_m; // Store data to instruction ROM 1.615 +wire [`LM32_WORD_RNG] irom_address_xm; // Address to instruction ROM from load-store unit 1.616 +wire [`LM32_WORD_RNG] irom_data_m; // Load data from instruction ROM 1.617 +wire irom_we_xm; // Indicates data needs to be written to instruction ROM 1.618 +wire irom_stall_request_x; // Indicates D stage needs to be stalled on a store to instruction ROM 1.619 +`endif 1.620 + 1.621 +// To/from load/store unit 1.622 +`ifdef CFG_DCACHE_ENABLED 1.623 +wire dflush_x; // Flush data cache 1.624 +reg dflush_m; 1.625 +wire dcache_stall_request; // Stall pipeline because data cache is busy 1.626 +wire dcache_restart_request; // Restart instruction that caused a data cache miss 1.627 +wire dcache_refill_request; // Request to refill data cache 1.628 +wire dcache_refilling; // Indicates the data cache is being refilled 1.629 +`endif 1.630 +wire [`LM32_WORD_RNG] load_data_w; // Result of a load instruction 1.631 +wire stall_wb_load; // Stall pipeline because of a load via the data Wishbone interface 1.632 + 1.633 +// To/from JTAG interface 1.634 +`ifdef CFG_JTAG_ENABLED 1.635 +`ifdef CFG_JTAG_UART_ENABLED 1.636 +wire [`LM32_WORD_RNG] jtx_csr_read_data; // Read data for JTX CSR 1.637 +wire [`LM32_WORD_RNG] jrx_csr_read_data; // Read data for JRX CSR 1.638 +`endif 1.639 +`ifdef CFG_HW_DEBUG_ENABLED 1.640 +wire jtag_csr_write_enable; // Debugger CSR write enable 1.641 +wire [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR 1.642 +wire [`LM32_CSR_RNG] jtag_csr; // Which CSR to write 1.643 +wire jtag_read_enable; 1.644 +wire [`LM32_BYTE_RNG] jtag_read_data; 1.645 +wire jtag_write_enable; 1.646 +wire [`LM32_BYTE_RNG] jtag_write_data; 1.647 +wire [`LM32_WORD_RNG] jtag_address; 1.648 +wire jtag_access_complete; 1.649 +`endif 1.650 +`ifdef CFG_DEBUG_ENABLED 1.651 +wire jtag_break; // Request from debugger to raise a breakpoint 1.652 +`endif 1.653 +`endif 1.654 + 1.655 +// Hazzard detection 1.656 +wire raw_x_0; // RAW hazzard between instruction in X stage and read port 0 1.657 +wire raw_x_1; // RAW hazzard between instruction in X stage and read port 1 1.658 +wire raw_m_0; // RAW hazzard between instruction in M stage and read port 0 1.659 +wire raw_m_1; // RAW hazzard between instruction in M stage and read port 1 1.660 +wire raw_w_0; // RAW hazzard between instruction in W stage and read port 0 1.661 +wire raw_w_1; // RAW hazzard between instruction in W stage and read port 1 1.662 + 1.663 +// Control flow 1.664 +wire cmp_zero; // Result of comparison is zero 1.665 +wire cmp_negative; // Result of comparison is negative 1.666 +wire cmp_overflow; // Comparison produced an overflow 1.667 +wire cmp_carry_n; // Comparison produced a carry, inverted 1.668 +reg condition_met_x; // Condition of branch instruction is met 1.669 +reg condition_met_m; 1.670 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.671 +wire branch_taken_x; // Branch is taken in X stage 1.672 +`endif 1.673 +wire branch_taken_m; // Branch is taken in M stage 1.674 + 1.675 +wire kill_f; // Kill instruction in F stage 1.676 +wire kill_d; // Kill instruction in D stage 1.677 +wire kill_x; // Kill instruction in X stage 1.678 +wire kill_m; // Kill instruction in M stage 1.679 +wire kill_w; // Kill instruction in W stage 1.680 + 1.681 +reg [`LM32_PC_WIDTH+2-1:8] eba; // Exception Base Address (EBA) CSR 1.682 +`ifdef CFG_DEBUG_ENABLED 1.683 +reg [`LM32_PC_WIDTH+2-1:8] deba; // Debug Exception Base Address (DEBA) CSR 1.684 +`endif 1.685 +reg [`LM32_EID_RNG] eid_x; // Exception ID in X stage 1.686 +`ifdef CFG_TRACE_ENABLED 1.687 +reg [`LM32_EID_RNG] eid_m; // Exception ID in M stage 1.688 +reg [`LM32_EID_RNG] eid_w; // Exception ID in W stage 1.689 +`endif 1.690 + 1.691 +`ifdef CFG_DEBUG_ENABLED 1.692 +`ifdef LM32_SINGLE_STEP_ENABLED 1.693 +wire dc_ss; // Is single-step enabled 1.694 +`endif 1.695 +wire dc_re; // Remap all exceptions 1.696 +wire exception_x; // An exception occured in the X stage 1.697 +reg exception_m; // An instruction that caused an exception is in the M stage 1.698 +wire debug_exception_x; // Indicates if a debug exception has occured 1.699 +reg debug_exception_m; 1.700 +reg debug_exception_w; 1.701 +wire debug_exception_q_w; 1.702 +wire non_debug_exception_x; // Indicates if a non debug exception has occured 1.703 +reg non_debug_exception_m; 1.704 +reg non_debug_exception_w; 1.705 +wire non_debug_exception_q_w; 1.706 +`else 1.707 +wire exception_x; // Indicates if a debug exception has occured 1.708 +reg exception_m; 1.709 +reg exception_w; 1.710 +wire exception_q_w; 1.711 +`endif 1.712 + 1.713 +`ifdef CFG_DEBUG_ENABLED 1.714 +`ifdef CFG_JTAG_ENABLED 1.715 +wire reset_exception; // Indicates if a reset exception has occured 1.716 +`endif 1.717 +`endif 1.718 +`ifdef CFG_INTERRUPTS_ENABLED 1.719 +wire interrupt_exception; // Indicates if an interrupt exception has occured 1.720 +`endif 1.721 +`ifdef CFG_DEBUG_ENABLED 1.722 +wire breakpoint_exception; // Indicates if a breakpoint exception has occured 1.723 +wire watchpoint_exception; // Indicates if a watchpoint exception has occured 1.724 +`endif 1.725 +`ifdef CFG_BUS_ERRORS_ENABLED 1.726 +wire instruction_bus_error_exception; // Indicates if an instruction bus error exception has occured 1.727 +wire data_bus_error_exception; // Indicates if a data bus error exception has occured 1.728 +`endif 1.729 +`ifdef CFG_MC_DIVIDE_ENABLED 1.730 +wire divide_by_zero_exception; // Indicates if a divide by zero exception has occured 1.731 +`endif 1.732 +wire system_call_exception; // Indicates if a system call exception has occured 1.733 + 1.734 +`ifdef CFG_BUS_ERRORS_ENABLED 1.735 +reg data_bus_error_seen; // Indicates if a data bus error was seen 1.736 +`endif 1.737 + 1.738 +///////////////////////////////////////////////////// 1.739 +// Functions 1.740 +///////////////////////////////////////////////////// 1.741 + 1.742 +`include "lm32_functions.v" 1.743 + 1.744 +///////////////////////////////////////////////////// 1.745 +// Instantiations 1.746 +///////////////////////////////////////////////////// 1.747 + 1.748 +// Instruction unit 1.749 +lm32_instruction_unit #( 1.750 + .associativity (icache_associativity), 1.751 + .sets (icache_sets), 1.752 + .bytes_per_line (icache_bytes_per_line), 1.753 + .base_address (icache_base_address), 1.754 + .limit (icache_limit) 1.755 + ) instruction_unit ( 1.756 + // ----- Inputs ------- 1.757 + .clk_i (clk_i), 1.758 + .rst_i (rst_i), 1.759 + // From pipeline 1.760 + .stall_a (stall_a), 1.761 + .stall_f (stall_f), 1.762 + .stall_d (stall_d), 1.763 + .stall_x (stall_x), 1.764 + .stall_m (stall_m), 1.765 + .valid_f (valid_f), 1.766 + .valid_d (valid_d), 1.767 + .kill_f (kill_f), 1.768 + .branch_predict_taken_d (branch_predict_taken_d), 1.769 + .branch_predict_address_d (branch_predict_address_d), 1.770 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.771 + .branch_taken_x (branch_taken_x), 1.772 + .branch_target_x (branch_target_x), 1.773 +`endif 1.774 + .exception_m (exception_m), 1.775 + .branch_taken_m (branch_taken_m), 1.776 + .branch_mispredict_taken_m (branch_mispredict_taken_m), 1.777 + .branch_target_m (branch_target_m), 1.778 +`ifdef CFG_ICACHE_ENABLED 1.779 + .iflush (iflush), 1.780 +`endif 1.781 +`ifdef CFG_IROM_ENABLED 1.782 + .irom_store_data_m (irom_store_data_m), 1.783 + .irom_address_xm (irom_address_xm), 1.784 + .irom_we_xm (irom_we_xm), 1.785 +`endif 1.786 +`ifdef CFG_DCACHE_ENABLED 1.787 + .dcache_restart_request (dcache_restart_request), 1.788 + .dcache_refill_request (dcache_refill_request), 1.789 + .dcache_refilling (dcache_refilling), 1.790 +`endif 1.791 +`ifdef CFG_IWB_ENABLED 1.792 + // From Wishbone 1.793 + .i_dat_i (I_DAT_I), 1.794 + .i_ack_i (I_ACK_I), 1.795 + .i_err_i (I_ERR_I), 1.796 + .i_rty_i (I_RTY_I), 1.797 +`endif 1.798 +`ifdef CFG_HW_DEBUG_ENABLED 1.799 + .jtag_read_enable (jtag_read_enable), 1.800 + .jtag_write_enable (jtag_write_enable), 1.801 + .jtag_write_data (jtag_write_data), 1.802 + .jtag_address (jtag_address), 1.803 +`endif 1.804 + // ----- Outputs ------- 1.805 + // To pipeline 1.806 + .pc_f (pc_f), 1.807 + .pc_d (pc_d), 1.808 + .pc_x (pc_x), 1.809 + .pc_m (pc_m), 1.810 + .pc_w (pc_w), 1.811 +`ifdef CFG_ICACHE_ENABLED 1.812 + .icache_stall_request (icache_stall_request), 1.813 + .icache_restart_request (icache_restart_request), 1.814 + .icache_refill_request (icache_refill_request), 1.815 + .icache_refilling (icache_refilling), 1.816 +`endif 1.817 +`ifdef CFG_IROM_ENABLED 1.818 + .irom_data_m (irom_data_m), 1.819 +`endif 1.820 +`ifdef CFG_IWB_ENABLED 1.821 + // To Wishbone 1.822 + .i_dat_o (I_DAT_O), 1.823 + .i_adr_o (I_ADR_O), 1.824 + .i_cyc_o (I_CYC_O), 1.825 + .i_sel_o (I_SEL_O), 1.826 + .i_stb_o (I_STB_O), 1.827 + .i_we_o (I_WE_O), 1.828 + .i_cti_o (I_CTI_O), 1.829 + .i_lock_o (I_LOCK_O), 1.830 + .i_bte_o (I_BTE_O), 1.831 +`endif 1.832 +`ifdef CFG_HW_DEBUG_ENABLED 1.833 + .jtag_read_data (jtag_read_data), 1.834 + .jtag_access_complete (jtag_access_complete), 1.835 +`endif 1.836 +`ifdef CFG_BUS_ERRORS_ENABLED 1.837 + .bus_error_d (bus_error_d), 1.838 +`endif 1.839 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.840 + .instruction_f (instruction_f), 1.841 +`endif 1.842 + .instruction_d (instruction_d) 1.843 + ); 1.844 + 1.845 +// Instruction decoder 1.846 +lm32_decoder decoder ( 1.847 + // ----- Inputs ------- 1.848 + .instruction (instruction_d), 1.849 + // ----- Outputs ------- 1.850 + .d_result_sel_0 (d_result_sel_0_d), 1.851 + .d_result_sel_1 (d_result_sel_1_d), 1.852 + .x_result_sel_csr (x_result_sel_csr_d), 1.853 +`ifdef LM32_MC_ARITHMETIC_ENABLED 1.854 + .x_result_sel_mc_arith (x_result_sel_mc_arith_d), 1.855 +`endif 1.856 +`ifdef LM32_NO_BARREL_SHIFT 1.857 + .x_result_sel_shift (x_result_sel_shift_d), 1.858 +`endif 1.859 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.860 + .x_result_sel_sext (x_result_sel_sext_d), 1.861 +`endif 1.862 + .x_result_sel_logic (x_result_sel_logic_d), 1.863 +`ifdef CFG_USER_ENABLED 1.864 + .x_result_sel_user (x_result_sel_user_d), 1.865 +`endif 1.866 + .x_result_sel_add (x_result_sel_add_d), 1.867 + .m_result_sel_compare (m_result_sel_compare_d), 1.868 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.869 + .m_result_sel_shift (m_result_sel_shift_d), 1.870 +`endif 1.871 + .w_result_sel_load (w_result_sel_load_d), 1.872 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.873 + .w_result_sel_mul (w_result_sel_mul_d), 1.874 +`endif 1.875 + .x_bypass_enable (x_bypass_enable_d), 1.876 + .m_bypass_enable (m_bypass_enable_d), 1.877 + .read_enable_0 (read_enable_0_d), 1.878 + .read_idx_0 (read_idx_0_d), 1.879 + .read_enable_1 (read_enable_1_d), 1.880 + .read_idx_1 (read_idx_1_d), 1.881 + .write_enable (write_enable_d), 1.882 + .write_idx (write_idx_d), 1.883 + .immediate (immediate_d), 1.884 + .branch_offset (branch_offset_d), 1.885 + .load (load_d), 1.886 + .store (store_d), 1.887 + .size (size_d), 1.888 + .sign_extend (sign_extend_d), 1.889 + .adder_op (adder_op_d), 1.890 + .logic_op (logic_op_d), 1.891 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.892 + .direction (direction_d), 1.893 +`endif 1.894 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.895 + .shift_left (shift_left_d), 1.896 + .shift_right (shift_right_d), 1.897 +`endif 1.898 +`ifdef CFG_MC_MULTIPLY_ENABLED 1.899 + .multiply (multiply_d), 1.900 +`endif 1.901 +`ifdef CFG_MC_DIVIDE_ENABLED 1.902 + .divide (divide_d), 1.903 + .modulus (modulus_d), 1.904 +`endif 1.905 + .branch (branch_d), 1.906 + .bi_unconditional (bi_unconditional), 1.907 + .bi_conditional (bi_conditional), 1.908 + .branch_reg (branch_reg_d), 1.909 + .condition (condition_d), 1.910 +`ifdef CFG_DEBUG_ENABLED 1.911 + .break_opcode (break_d), 1.912 +`endif 1.913 + .scall (scall_d), 1.914 + .eret (eret_d), 1.915 +`ifdef CFG_DEBUG_ENABLED 1.916 + .bret (bret_d), 1.917 +`endif 1.918 +`ifdef CFG_USER_ENABLED 1.919 + .user_opcode (user_opcode_d), 1.920 +`endif 1.921 + .csr_write_enable (csr_write_enable_d) 1.922 + ); 1.923 + 1.924 +// Load/store unit 1.925 +lm32_load_store_unit #( 1.926 + .associativity (dcache_associativity), 1.927 + .sets (dcache_sets), 1.928 + .bytes_per_line (dcache_bytes_per_line), 1.929 + .base_address (dcache_base_address), 1.930 + .limit (dcache_limit) 1.931 + ) load_store_unit ( 1.932 + // ----- Inputs ------- 1.933 + .clk_i (clk_i), 1.934 + .rst_i (rst_i), 1.935 + // From pipeline 1.936 + .stall_a (stall_a), 1.937 + .stall_x (stall_x), 1.938 + .stall_m (stall_m), 1.939 + .kill_x (kill_x), 1.940 + .kill_m (kill_m), 1.941 + .exception_m (exception_m), 1.942 + .store_operand_x (store_operand_x), 1.943 + .load_store_address_x (adder_result_x), 1.944 + .load_store_address_m (operand_m), 1.945 + .load_store_address_w (operand_w[1:0]), 1.946 + .load_x (load_x), 1.947 + .store_x (store_x), 1.948 + .load_q_x (load_q_x), 1.949 + .store_q_x (store_q_x), 1.950 + .load_q_m (load_q_m), 1.951 + .store_q_m (store_q_m), 1.952 + .sign_extend_x (sign_extend_x), 1.953 + .size_x (size_x), 1.954 +`ifdef CFG_DCACHE_ENABLED 1.955 + .dflush (dflush_m), 1.956 +`endif 1.957 +`ifdef CFG_IROM_ENABLED 1.958 + .irom_data_m (irom_data_m), 1.959 +`endif 1.960 + // From Wishbone 1.961 + .d_dat_i (D_DAT_I), 1.962 + .d_ack_i (D_ACK_I), 1.963 + .d_err_i (D_ERR_I), 1.964 + .d_rty_i (D_RTY_I), 1.965 + // ----- Outputs ------- 1.966 + // To pipeline 1.967 +`ifdef CFG_DCACHE_ENABLED 1.968 + .dcache_refill_request (dcache_refill_request), 1.969 + .dcache_restart_request (dcache_restart_request), 1.970 + .dcache_stall_request (dcache_stall_request), 1.971 + .dcache_refilling (dcache_refilling), 1.972 +`endif 1.973 +`ifdef CFG_IROM_ENABLED 1.974 + .irom_store_data_m (irom_store_data_m), 1.975 + .irom_address_xm (irom_address_xm), 1.976 + .irom_we_xm (irom_we_xm), 1.977 + .irom_stall_request_x (irom_stall_request_x), 1.978 +`endif 1.979 + .load_data_w (load_data_w), 1.980 + .stall_wb_load (stall_wb_load), 1.981 + // To Wishbone 1.982 + .d_dat_o (D_DAT_O), 1.983 + .d_adr_o (D_ADR_O), 1.984 + .d_cyc_o (D_CYC_O), 1.985 + .d_sel_o (D_SEL_O), 1.986 + .d_stb_o (D_STB_O), 1.987 + .d_we_o (D_WE_O), 1.988 + .d_cti_o (D_CTI_O), 1.989 + .d_lock_o (D_LOCK_O), 1.990 + .d_bte_o (D_BTE_O) 1.991 + ); 1.992 + 1.993 +// Adder 1.994 +lm32_adder adder ( 1.995 + // ----- Inputs ------- 1.996 + .adder_op_x (adder_op_x), 1.997 + .adder_op_x_n (adder_op_x_n), 1.998 + .operand_0_x (operand_0_x), 1.999 + .operand_1_x (operand_1_x), 1.1000 + // ----- Outputs ------- 1.1001 + .adder_result_x (adder_result_x), 1.1002 + .adder_carry_n_x (adder_carry_n_x), 1.1003 + .adder_overflow_x (adder_overflow_x) 1.1004 + ); 1.1005 + 1.1006 +// Logic operations 1.1007 +lm32_logic_op logic_op ( 1.1008 + // ----- Inputs ------- 1.1009 + .logic_op_x (logic_op_x), 1.1010 + .operand_0_x (operand_0_x), 1.1011 + 1.1012 + .operand_1_x (operand_1_x), 1.1013 + // ----- Outputs ------- 1.1014 + .logic_result_x (logic_result_x) 1.1015 + ); 1.1016 + 1.1017 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.1018 +// Pipelined barrel-shifter 1.1019 +lm32_shifter shifter ( 1.1020 + // ----- Inputs ------- 1.1021 + .clk_i (clk_i), 1.1022 + .rst_i (rst_i), 1.1023 + .stall_x (stall_x), 1.1024 + .direction_x (direction_x), 1.1025 + .sign_extend_x (sign_extend_x), 1.1026 + .operand_0_x (operand_0_x), 1.1027 + .operand_1_x (operand_1_x), 1.1028 + // ----- Outputs ------- 1.1029 + .shifter_result_m (shifter_result_m) 1.1030 + ); 1.1031 +`endif 1.1032 + 1.1033 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.1034 +// Pipeline fixed-point multiplier 1.1035 +lm32_multiplier multiplier ( 1.1036 + // ----- Inputs ------- 1.1037 + .clk_i (clk_i), 1.1038 + .rst_i (rst_i), 1.1039 + .stall_x (stall_x), 1.1040 + .stall_m (stall_m), 1.1041 + .operand_0 (d_result_0), 1.1042 + .operand_1 (d_result_1), 1.1043 + // ----- Outputs ------- 1.1044 + .result (multiplier_result_w) 1.1045 + ); 1.1046 +`endif 1.1047 + 1.1048 +`ifdef LM32_MC_ARITHMETIC_ENABLED 1.1049 +// Multi-cycle arithmetic 1.1050 +lm32_mc_arithmetic mc_arithmetic ( 1.1051 + // ----- Inputs ------- 1.1052 + .clk_i (clk_i), 1.1053 + .rst_i (rst_i), 1.1054 + .stall_d (stall_d), 1.1055 + .kill_x (kill_x), 1.1056 +`ifdef CFG_MC_DIVIDE_ENABLED 1.1057 + .divide_d (divide_q_d), 1.1058 + .modulus_d (modulus_q_d), 1.1059 +`endif 1.1060 +`ifdef CFG_MC_MULTIPLY_ENABLED 1.1061 + .multiply_d (multiply_q_d), 1.1062 +`endif 1.1063 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.1064 + .shift_left_d (shift_left_q_d), 1.1065 + .shift_right_d (shift_right_q_d), 1.1066 + .sign_extend_d (sign_extend_d), 1.1067 +`endif 1.1068 + .operand_0_d (d_result_0), 1.1069 + .operand_1_d (d_result_1), 1.1070 + // ----- Outputs ------- 1.1071 + .result_x (mc_result_x), 1.1072 +`ifdef CFG_MC_DIVIDE_ENABLED 1.1073 + .divide_by_zero_x (divide_by_zero_x), 1.1074 +`endif 1.1075 + .stall_request_x (mc_stall_request_x) 1.1076 + ); 1.1077 +`endif 1.1078 + 1.1079 +`ifdef CFG_INTERRUPTS_ENABLED 1.1080 +// Interrupt unit 1.1081 +lm32_interrupt interrupt ( 1.1082 + // ----- Inputs ------- 1.1083 + .clk_i (clk_i), 1.1084 + .rst_i (rst_i), 1.1085 + // From external devices 1.1086 + .interrupt_n (interrupt_n), 1.1087 + // From pipeline 1.1088 + .stall_x (stall_x), 1.1089 +`ifdef CFG_DEBUG_ENABLED 1.1090 + .non_debug_exception (non_debug_exception_q_w), 1.1091 + .debug_exception (debug_exception_q_w), 1.1092 +`else 1.1093 + .exception (exception_q_w), 1.1094 +`endif 1.1095 + .eret_q_x (eret_q_x), 1.1096 +`ifdef CFG_DEBUG_ENABLED 1.1097 + .bret_q_x (bret_q_x), 1.1098 +`endif 1.1099 + .csr (csr_x), 1.1100 + .csr_write_data (operand_1_x), 1.1101 + .csr_write_enable (csr_write_enable_q_x), 1.1102 + // ----- Outputs ------- 1.1103 + .interrupt_exception (interrupt_exception), 1.1104 + // To pipeline 1.1105 + .csr_read_data (interrupt_csr_read_data_x) 1.1106 + ); 1.1107 +`endif 1.1108 + 1.1109 +`ifdef CFG_JTAG_ENABLED 1.1110 +// JTAG interface 1.1111 +lm32_jtag jtag ( 1.1112 + // ----- Inputs ------- 1.1113 + .clk_i (clk_i), 1.1114 + .rst_i (rst_i), 1.1115 + // From JTAG 1.1116 + .jtag_clk (jtag_clk), 1.1117 + .jtag_update (jtag_update), 1.1118 + .jtag_reg_q (jtag_reg_q), 1.1119 + .jtag_reg_addr_q (jtag_reg_addr_q), 1.1120 + // From pipeline 1.1121 +`ifdef CFG_JTAG_UART_ENABLED 1.1122 + .csr (csr_x), 1.1123 + .csr_write_data (operand_1_x), 1.1124 + .csr_write_enable (csr_write_enable_q_x), 1.1125 + .stall_x (stall_x), 1.1126 +`endif 1.1127 +`ifdef CFG_HW_DEBUG_ENABLED 1.1128 + .jtag_read_data (jtag_read_data), 1.1129 + .jtag_access_complete (jtag_access_complete), 1.1130 +`endif 1.1131 +`ifdef CFG_DEBUG_ENABLED 1.1132 + .exception_q_w (debug_exception_q_w || non_debug_exception_q_w), 1.1133 +`endif 1.1134 + // ----- Outputs ------- 1.1135 + // To pipeline 1.1136 +`ifdef CFG_JTAG_UART_ENABLED 1.1137 + .jtx_csr_read_data (jtx_csr_read_data), 1.1138 + .jrx_csr_read_data (jrx_csr_read_data), 1.1139 +`endif 1.1140 +`ifdef CFG_HW_DEBUG_ENABLED 1.1141 + .jtag_csr_write_enable (jtag_csr_write_enable), 1.1142 + .jtag_csr_write_data (jtag_csr_write_data), 1.1143 + .jtag_csr (jtag_csr), 1.1144 + .jtag_read_enable (jtag_read_enable), 1.1145 + .jtag_write_enable (jtag_write_enable), 1.1146 + .jtag_write_data (jtag_write_data), 1.1147 + .jtag_address (jtag_address), 1.1148 +`endif 1.1149 +`ifdef CFG_DEBUG_ENABLED 1.1150 + .jtag_break (jtag_break), 1.1151 + .jtag_reset (reset_exception), 1.1152 +`endif 1.1153 + // To JTAG 1.1154 + .jtag_reg_d (jtag_reg_d), 1.1155 + .jtag_reg_addr_d (jtag_reg_addr_d) 1.1156 + ); 1.1157 +`endif 1.1158 + 1.1159 +`ifdef CFG_DEBUG_ENABLED 1.1160 +// Debug unit 1.1161 +lm32_debug #( 1.1162 + .breakpoints (breakpoints), 1.1163 + .watchpoints (watchpoints) 1.1164 + ) hw_debug ( 1.1165 + // ----- Inputs ------- 1.1166 + .clk_i (clk_i), 1.1167 + .rst_i (rst_i), 1.1168 + .pc_x (pc_x), 1.1169 + .load_x (load_x), 1.1170 + .store_x (store_x), 1.1171 + .load_store_address_x (adder_result_x), 1.1172 + .csr_write_enable_x (csr_write_enable_q_x), 1.1173 + .csr_write_data (operand_1_x), 1.1174 + .csr_x (csr_x), 1.1175 +`ifdef CFG_HW_DEBUG_ENABLED 1.1176 + .jtag_csr_write_enable (jtag_csr_write_enable), 1.1177 + .jtag_csr_write_data (jtag_csr_write_data), 1.1178 + .jtag_csr (jtag_csr), 1.1179 +`endif 1.1180 +`ifdef LM32_SINGLE_STEP_ENABLED 1.1181 + .eret_q_x (eret_q_x), 1.1182 + .bret_q_x (bret_q_x), 1.1183 + .stall_x (stall_x), 1.1184 + .exception_x (exception_x), 1.1185 + .q_x (q_x), 1.1186 +`ifdef CFG_DCACHE_ENABLED 1.1187 + .dcache_refill_request (dcache_refill_request), 1.1188 +`endif 1.1189 +`endif 1.1190 + // ----- Outputs ------- 1.1191 +`ifdef LM32_SINGLE_STEP_ENABLED 1.1192 + .dc_ss (dc_ss), 1.1193 +`endif 1.1194 + .dc_re (dc_re), 1.1195 + .bp_match (bp_match), 1.1196 + .wp_match (wp_match) 1.1197 + ); 1.1198 +`endif 1.1199 + 1.1200 +// Register file 1.1201 + 1.1202 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.1203 + /*---------------------------------------------------------------------- 1.1204 + Register File is implemented using EBRs. There can be three accesses to 1.1205 + the register file in each cycle: two reads and one write. On-chip block 1.1206 + RAM has two read/write ports. To accomodate three accesses, two on-chip 1.1207 + block RAMs are used (each register file "write" is made to both block 1.1208 + RAMs). 1.1209 + 1.1210 + One limitation of the on-chip block RAMs is that one cannot perform a 1.1211 + read and write to same location in a cycle (if this is done, then the 1.1212 + data read out is indeterminate). 1.1213 + ----------------------------------------------------------------------*/ 1.1214 + wire [31:0] regfile_data_0, regfile_data_1; 1.1215 + reg [31:0] w_result_d; 1.1216 + reg regfile_raw_0, regfile_raw_0_nxt; 1.1217 + reg regfile_raw_1, regfile_raw_1_nxt; 1.1218 + 1.1219 + /*---------------------------------------------------------------------- 1.1220 + Check if read and write is being performed to same register in current 1.1221 + cycle? This is done by comparing the read and write IDXs. 1.1222 + ----------------------------------------------------------------------*/ 1.1223 + always @(reg_write_enable_q_w or write_idx_w or instruction_f) 1.1224 + begin 1.1225 + if (reg_write_enable_q_w 1.1226 + && (write_idx_w == instruction_f[25:21])) 1.1227 + regfile_raw_0_nxt = 1'b1; 1.1228 + else 1.1229 + regfile_raw_0_nxt = 1'b0; 1.1230 + 1.1231 + if (reg_write_enable_q_w 1.1232 + && (write_idx_w == instruction_f[20:16])) 1.1233 + regfile_raw_1_nxt = 1'b1; 1.1234 + else 1.1235 + regfile_raw_1_nxt = 1'b0; 1.1236 + end 1.1237 + 1.1238 + /*---------------------------------------------------------------------- 1.1239 + Select latched (delayed) write value or data from register file. If 1.1240 + read in previous cycle was performed to register written to in same 1.1241 + cycle, then latched (delayed) write value is selected. 1.1242 + ----------------------------------------------------------------------*/ 1.1243 + always @(regfile_raw_0 or w_result_d or regfile_data_0) 1.1244 + if (regfile_raw_0) 1.1245 + reg_data_live_0 = w_result_d; 1.1246 + else 1.1247 + reg_data_live_0 = regfile_data_0; 1.1248 + 1.1249 + /*---------------------------------------------------------------------- 1.1250 + Select latched (delayed) write value or data from register file. If 1.1251 + read in previous cycle was performed to register written to in same 1.1252 + cycle, then latched (delayed) write value is selected. 1.1253 + ----------------------------------------------------------------------*/ 1.1254 + always @(regfile_raw_1 or w_result_d or regfile_data_1) 1.1255 + if (regfile_raw_1) 1.1256 + reg_data_live_1 = w_result_d; 1.1257 + else 1.1258 + reg_data_live_1 = regfile_data_1; 1.1259 + 1.1260 + /*---------------------------------------------------------------------- 1.1261 + Latch value written to register file 1.1262 + ----------------------------------------------------------------------*/ 1.1263 + always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.1264 + if (rst_i == `TRUE) 1.1265 + begin 1.1266 + regfile_raw_0 <= 1'b0; 1.1267 + regfile_raw_1 <= 1'b0; 1.1268 + w_result_d <= 32'b0; 1.1269 + end 1.1270 + else 1.1271 + begin 1.1272 + regfile_raw_0 <= regfile_raw_0_nxt; 1.1273 + regfile_raw_1 <= regfile_raw_1_nxt; 1.1274 + w_result_d <= w_result; 1.1275 + end 1.1276 + 1.1277 + /*---------------------------------------------------------------------- 1.1278 + Register file instantiation as Pseudo-Dual Port EBRs. 1.1279 + ----------------------------------------------------------------------*/ 1.1280 + pmi_ram_dp 1.1281 + #( 1.1282 + // ----- Parameters ----- 1.1283 + .pmi_wr_addr_depth(1<<5), 1.1284 + .pmi_wr_addr_width(5), 1.1285 + .pmi_wr_data_width(32), 1.1286 + .pmi_rd_addr_depth(1<<5), 1.1287 + .pmi_rd_addr_width(5), 1.1288 + .pmi_rd_data_width(32), 1.1289 + .pmi_regmode("noreg"), 1.1290 + .pmi_gsr("enable"), 1.1291 + .pmi_resetmode("sync"), 1.1292 + .pmi_init_file("none"), 1.1293 + .pmi_init_file_format("binary"), 1.1294 + .pmi_family(`LATTICE_FAMILY), 1.1295 + .module_type("pmi_ram_dp") 1.1296 + ) 1.1297 + reg_0 1.1298 + ( 1.1299 + // ----- Inputs ----- 1.1300 + .Data(w_result), 1.1301 + .WrAddress(write_idx_w), 1.1302 + .RdAddress(instruction_f[25:21]), 1.1303 + .WrClock(clk_i), 1.1304 + .RdClock(clk_i), 1.1305 + .WrClockEn(`TRUE), 1.1306 + .RdClockEn(`TRUE), 1.1307 + .WE(reg_write_enable_q_w), 1.1308 + .Reset(rst_i), 1.1309 + // ----- Outputs ----- 1.1310 + .Q(regfile_data_0) 1.1311 + ); 1.1312 + 1.1313 + pmi_ram_dp 1.1314 + #( 1.1315 + // ----- Parameters ----- 1.1316 + .pmi_wr_addr_depth(1<<5), 1.1317 + .pmi_wr_addr_width(5), 1.1318 + .pmi_wr_data_width(32), 1.1319 + .pmi_rd_addr_depth(1<<5), 1.1320 + .pmi_rd_addr_width(5), 1.1321 + .pmi_rd_data_width(32), 1.1322 + .pmi_regmode("noreg"), 1.1323 + .pmi_gsr("enable"), 1.1324 + .pmi_resetmode("sync"), 1.1325 + .pmi_init_file("none"), 1.1326 + .pmi_init_file_format("binary"), 1.1327 + .pmi_family(`LATTICE_FAMILY), 1.1328 + .module_type("pmi_ram_dp") 1.1329 + ) 1.1330 + reg_1 1.1331 + ( 1.1332 + // ----- Inputs ----- 1.1333 + .Data(w_result), 1.1334 + .WrAddress(write_idx_w), 1.1335 + .RdAddress(instruction_f[20:16]), 1.1336 + .WrClock(clk_i), 1.1337 + .RdClock(clk_i), 1.1338 + .WrClockEn(`TRUE), 1.1339 + .RdClockEn(`TRUE), 1.1340 + .WE(reg_write_enable_q_w), 1.1341 + .Reset(rst_i), 1.1342 + // ----- Outputs ----- 1.1343 + .Q(regfile_data_1) 1.1344 + ); 1.1345 +`endif 1.1346 + 1.1347 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 1.1348 + pmi_ram_dp 1.1349 + #( 1.1350 + // ----- Parameters ----- 1.1351 + .pmi_wr_addr_depth(1<<5), 1.1352 + .pmi_wr_addr_width(5), 1.1353 + .pmi_wr_data_width(32), 1.1354 + .pmi_rd_addr_depth(1<<5), 1.1355 + .pmi_rd_addr_width(5), 1.1356 + .pmi_rd_data_width(32), 1.1357 + .pmi_regmode("noreg"), 1.1358 + .pmi_gsr("enable"), 1.1359 + .pmi_resetmode("sync"), 1.1360 + .pmi_init_file("none"), 1.1361 + .pmi_init_file_format("binary"), 1.1362 + .pmi_family(`LATTICE_FAMILY), 1.1363 + .module_type("pmi_ram_dp") 1.1364 + ) 1.1365 + reg_0 1.1366 + ( 1.1367 + // ----- Inputs ----- 1.1368 + .Data(w_result), 1.1369 + .WrAddress(write_idx_w), 1.1370 + .RdAddress(read_idx_0_d), 1.1371 + .WrClock(clk_i), 1.1372 + .RdClock(clk_n_i), 1.1373 + .WrClockEn(`TRUE), 1.1374 + .RdClockEn(stall_f == `FALSE), 1.1375 + .WE(reg_write_enable_q_w), 1.1376 + .Reset(rst_i), 1.1377 + // ----- Outputs ----- 1.1378 + .Q(reg_data_0) 1.1379 + ); 1.1380 + 1.1381 + pmi_ram_dp 1.1382 + #( 1.1383 + // ----- Parameters ----- 1.1384 + .pmi_wr_addr_depth(1<<5), 1.1385 + .pmi_wr_addr_width(5), 1.1386 + .pmi_wr_data_width(32), 1.1387 + .pmi_rd_addr_depth(1<<5), 1.1388 + .pmi_rd_addr_width(5), 1.1389 + .pmi_rd_data_width(32), 1.1390 + .pmi_regmode("noreg"), 1.1391 + .pmi_gsr("enable"), 1.1392 + .pmi_resetmode("sync"), 1.1393 + .pmi_init_file("none"), 1.1394 + .pmi_init_file_format("binary"), 1.1395 + .pmi_family(`LATTICE_FAMILY), 1.1396 + .module_type("pmi_ram_dp") 1.1397 + ) 1.1398 + reg_1 1.1399 + ( 1.1400 + // ----- Inputs ----- 1.1401 + .Data(w_result), 1.1402 + .WrAddress(write_idx_w), 1.1403 + .RdAddress(read_idx_1_d), 1.1404 + .WrClock(clk_i), 1.1405 + .RdClock(clk_n_i), 1.1406 + .WrClockEn(`TRUE), 1.1407 + .RdClockEn(stall_f == `FALSE), 1.1408 + .WE(reg_write_enable_q_w), 1.1409 + .Reset(rst_i), 1.1410 + // ----- Outputs ----- 1.1411 + .Q(reg_data_1) 1.1412 + ); 1.1413 +`endif 1.1414 + 1.1415 + 1.1416 +///////////////////////////////////////////////////// 1.1417 +// Combinational Logic 1.1418 +///////////////////////////////////////////////////// 1.1419 + 1.1420 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.1421 +// Select between buffered and live data from register file 1.1422 +assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0; 1.1423 +assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1; 1.1424 +`endif 1.1425 +`ifdef LM32_EBR_REGISTER_FILE 1.1426 +`else 1.1427 +// Register file read ports 1.1428 +assign reg_data_0 = registers[read_idx_0_d]; 1.1429 +assign reg_data_1 = registers[read_idx_1_d]; 1.1430 +`endif 1.1431 + 1.1432 +// Detect read-after-write hazzards 1.1433 +assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE); 1.1434 +assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE); 1.1435 +assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE); 1.1436 +assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE); 1.1437 +assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE); 1.1438 +assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE); 1.1439 + 1.1440 +// Interlock detection - Raise an interlock for RAW hazzards 1.1441 +always @(*) 1.1442 +begin 1.1443 + if ( ( (x_bypass_enable_x == `FALSE) 1.1444 + && ( ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE)) 1.1445 + || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE)) 1.1446 + ) 1.1447 + ) 1.1448 + || ( (m_bypass_enable_m == `FALSE) 1.1449 + && ( ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE)) 1.1450 + || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE)) 1.1451 + ) 1.1452 + ) 1.1453 + ) 1.1454 + interlock = `TRUE; 1.1455 + else 1.1456 + interlock = `FALSE; 1.1457 +end 1.1458 + 1.1459 +// Bypass for reg port 0 1.1460 +always @(*) 1.1461 +begin 1.1462 + if (raw_x_0 == `TRUE) 1.1463 + bypass_data_0 = x_result; 1.1464 + else if (raw_m_0 == `TRUE) 1.1465 + bypass_data_0 = m_result; 1.1466 + else if (raw_w_0 == `TRUE) 1.1467 + bypass_data_0 = w_result; 1.1468 + else 1.1469 + bypass_data_0 = reg_data_0; 1.1470 +end 1.1471 + 1.1472 +// Bypass for reg port 1 1.1473 +always @(*) 1.1474 +begin 1.1475 + if (raw_x_1 == `TRUE) 1.1476 + bypass_data_1 = x_result; 1.1477 + else if (raw_m_1 == `TRUE) 1.1478 + bypass_data_1 = m_result; 1.1479 + else if (raw_w_1 == `TRUE) 1.1480 + bypass_data_1 = w_result; 1.1481 + else 1.1482 + bypass_data_1 = reg_data_1; 1.1483 +end 1.1484 + 1.1485 + /*---------------------------------------------------------------------- 1.1486 + Branch prediction is performed in D stage of pipeline. Only PC-relative 1.1487 + branches are predicted: forward-pointing conditional branches are not- 1.1488 + taken, while backward-pointing conditional branches are taken. 1.1489 + Unconditional branches are always predicted taken! 1.1490 + ----------------------------------------------------------------------*/ 1.1491 + assign branch_predict_d = bi_unconditional | bi_conditional; 1.1492 + assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0); 1.1493 + 1.1494 + // Compute branch target address: Branch PC PLUS Offset 1.1495 + assign branch_target_d = pc_d + branch_offset_d; 1.1496 + 1.1497 + // Compute fetch address. Address of instruction sequentially after the 1.1498 + // branch if branch is not taken. Target address of branch is branch is 1.1499 + // taken 1.1500 + assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f; 1.1501 + 1.1502 +// D stage result selection 1.1503 +always @(*) 1.1504 +begin 1.1505 + d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 1.1506 + case (d_result_sel_1_d) 1.1507 + `LM32_D_RESULT_SEL_1_ZERO: d_result_1 = {`LM32_WORD_WIDTH{1'b0}}; 1.1508 + `LM32_D_RESULT_SEL_1_REG_1: d_result_1 = bypass_data_1; 1.1509 + `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d; 1.1510 + default: d_result_1 = {`LM32_WORD_WIDTH{1'bx}}; 1.1511 + endcase 1.1512 +end 1.1513 + 1.1514 +`ifdef CFG_USER_ENABLED 1.1515 +// Operands for user-defined instructions 1.1516 +assign user_operand_0 = operand_0_x; 1.1517 +assign user_operand_1 = operand_1_x; 1.1518 +`endif 1.1519 + 1.1520 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.1521 +// Sign-extension 1.1522 +assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]}; 1.1523 +assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]}; 1.1524 +assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x; 1.1525 +`endif 1.1526 + 1.1527 +`ifdef LM32_NO_BARREL_SHIFT 1.1528 +// Only single bit shift operations are supported when barrel-shifter isn't implemented 1.1529 +assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]}; 1.1530 +`endif 1.1531 + 1.1532 +// Condition evaluation 1.1533 +assign cmp_zero = operand_0_x == operand_1_x; 1.1534 +assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1]; 1.1535 +assign cmp_overflow = adder_overflow_x; 1.1536 +assign cmp_carry_n = adder_carry_n_x; 1.1537 +always @(*) 1.1538 +begin 1.1539 + case (condition_x) 1.1540 + `LM32_CONDITION_U1: condition_met_x = `TRUE; 1.1541 + `LM32_CONDITION_U2: condition_met_x = `TRUE; 1.1542 + `LM32_CONDITION_E: condition_met_x = cmp_zero; 1.1543 + `LM32_CONDITION_NE: condition_met_x = !cmp_zero; 1.1544 + `LM32_CONDITION_G: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow); 1.1545 + `LM32_CONDITION_GU: condition_met_x = cmp_carry_n && !cmp_zero; 1.1546 + `LM32_CONDITION_GE: condition_met_x = cmp_negative == cmp_overflow; 1.1547 + `LM32_CONDITION_GEU: condition_met_x = cmp_carry_n; 1.1548 + default: condition_met_x = 1'bx; 1.1549 + endcase 1.1550 +end 1.1551 + 1.1552 +// X stage result selection 1.1553 +always @(*) 1.1554 +begin 1.1555 + x_result = x_result_sel_add_x ? adder_result_x 1.1556 + : x_result_sel_csr_x ? csr_read_data_x 1.1557 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.1558 + : x_result_sel_sext_x ? sext_result_x 1.1559 +`endif 1.1560 +`ifdef CFG_USER_ENABLED 1.1561 + : x_result_sel_user_x ? user_result 1.1562 +`endif 1.1563 +`ifdef LM32_NO_BARREL_SHIFT 1.1564 + : x_result_sel_shift_x ? shifter_result_x 1.1565 +`endif 1.1566 +`ifdef LM32_MC_ARITHMETIC_ENABLED 1.1567 + : x_result_sel_mc_arith_x ? mc_result_x 1.1568 +`endif 1.1569 + : logic_result_x; 1.1570 +end 1.1571 + 1.1572 +// M stage result selection 1.1573 +always @(*) 1.1574 +begin 1.1575 + m_result = m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m} 1.1576 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.1577 + : m_result_sel_shift_m ? shifter_result_m 1.1578 +`endif 1.1579 + : operand_m; 1.1580 +end 1.1581 + 1.1582 +// W stage result selection 1.1583 +always @(*) 1.1584 +begin 1.1585 + w_result = w_result_sel_load_w ? load_data_w 1.1586 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.1587 + : w_result_sel_mul_w ? multiplier_result_w 1.1588 +`endif 1.1589 + : operand_w; 1.1590 +end 1.1591 + 1.1592 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.1593 +// Indicate when a branch should be taken in X stage 1.1594 +assign branch_taken_x = (stall_x == `FALSE) 1.1595 + && ( (branch_x == `TRUE) 1.1596 + && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2)) 1.1597 + && (valid_x == `TRUE) 1.1598 + && (branch_predict_x == `FALSE) 1.1599 + ); 1.1600 +`endif 1.1601 + 1.1602 +// Indicate when a branch should be taken in M stage (exceptions are a type of branch) 1.1603 +assign branch_taken_m = (stall_m == `FALSE) 1.1604 + && ( ( (branch_m == `TRUE) 1.1605 + && (valid_m == `TRUE) 1.1606 + && ( ( (condition_met_m == `TRUE) 1.1607 + && (branch_predict_taken_m == `FALSE) 1.1608 + ) 1.1609 + || ( (condition_met_m == `FALSE) 1.1610 + && (branch_predict_m == `TRUE) 1.1611 + && (branch_predict_taken_m == `TRUE) 1.1612 + ) 1.1613 + ) 1.1614 + ) 1.1615 + || (exception_m == `TRUE) 1.1616 + ); 1.1617 + 1.1618 +// Indicate when a branch in M stage is mispredicted as being taken 1.1619 +assign branch_mispredict_taken_m = (condition_met_m == `FALSE) 1.1620 + && (branch_predict_m == `TRUE) 1.1621 + && (branch_predict_taken_m == `TRUE); 1.1622 + 1.1623 +// Indicate when a branch in M stage will cause flush in X stage 1.1624 +assign branch_flushX_m = (stall_m == `FALSE) 1.1625 + && ( ( (branch_m == `TRUE) 1.1626 + && (valid_m == `TRUE) 1.1627 + && ( (condition_met_m == `TRUE) 1.1628 + || ( (condition_met_m == `FALSE) 1.1629 + && (branch_predict_m == `TRUE) 1.1630 + && (branch_predict_taken_m == `TRUE) 1.1631 + ) 1.1632 + ) 1.1633 + ) 1.1634 + || (exception_m == `TRUE) 1.1635 + ); 1.1636 + 1.1637 +// Generate signal that will kill instructions in each pipeline stage when necessary 1.1638 +assign kill_f = ( (valid_d == `TRUE) 1.1639 + && (branch_predict_taken_d == `TRUE) 1.1640 + ) 1.1641 + || (branch_taken_m == `TRUE) 1.1642 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.1643 + || (branch_taken_x == `TRUE) 1.1644 +`endif 1.1645 +`ifdef CFG_ICACHE_ENABLED 1.1646 + || (icache_refill_request == `TRUE) 1.1647 +`endif 1.1648 +`ifdef CFG_DCACHE_ENABLED 1.1649 + || (dcache_refill_request == `TRUE) 1.1650 +`endif 1.1651 + ; 1.1652 +assign kill_d = (branch_taken_m == `TRUE) 1.1653 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.1654 + || (branch_taken_x == `TRUE) 1.1655 +`endif 1.1656 +`ifdef CFG_ICACHE_ENABLED 1.1657 + || (icache_refill_request == `TRUE) 1.1658 +`endif 1.1659 +`ifdef CFG_DCACHE_ENABLED 1.1660 + || (dcache_refill_request == `TRUE) 1.1661 +`endif 1.1662 + ; 1.1663 +assign kill_x = (branch_flushX_m == `TRUE) 1.1664 +`ifdef CFG_DCACHE_ENABLED 1.1665 + || (dcache_refill_request == `TRUE) 1.1666 +`endif 1.1667 + ; 1.1668 +assign kill_m = `FALSE 1.1669 +`ifdef CFG_DCACHE_ENABLED 1.1670 + || (dcache_refill_request == `TRUE) 1.1671 +`endif 1.1672 + ; 1.1673 +assign kill_w = `FALSE 1.1674 +`ifdef CFG_DCACHE_ENABLED 1.1675 + || (dcache_refill_request == `TRUE) 1.1676 +`endif 1.1677 + ; 1.1678 + 1.1679 +// Exceptions 1.1680 + 1.1681 +`ifdef CFG_DEBUG_ENABLED 1.1682 +assign breakpoint_exception = ( ( (break_x == `TRUE) 1.1683 + || (bp_match == `TRUE) 1.1684 + ) 1.1685 + && (valid_x == `TRUE) 1.1686 + ) 1.1687 +`ifdef CFG_JTAG_ENABLED 1.1688 + || (jtag_break == `TRUE) 1.1689 +`endif 1.1690 + ; 1.1691 +`endif 1.1692 + 1.1693 +`ifdef CFG_DEBUG_ENABLED 1.1694 +assign watchpoint_exception = wp_match == `TRUE; 1.1695 +`endif 1.1696 + 1.1697 +`ifdef CFG_BUS_ERRORS_ENABLED 1.1698 +assign instruction_bus_error_exception = ( (bus_error_x == `TRUE) 1.1699 + && (valid_x == `TRUE) 1.1700 + ); 1.1701 +assign data_bus_error_exception = data_bus_error_seen == `TRUE; 1.1702 +`endif 1.1703 + 1.1704 +`ifdef CFG_MC_DIVIDE_ENABLED 1.1705 +assign divide_by_zero_exception = divide_by_zero_x == `TRUE; 1.1706 +`endif 1.1707 + 1.1708 +assign system_call_exception = ( (scall_x == `TRUE) 1.1709 +`ifdef CFG_BUS_ERRORS_ENABLED 1.1710 + && (valid_x == `TRUE) 1.1711 +`endif 1.1712 + ); 1.1713 + 1.1714 +`ifdef CFG_DEBUG_ENABLED 1.1715 +assign debug_exception_x = (breakpoint_exception == `TRUE) 1.1716 + || (watchpoint_exception == `TRUE) 1.1717 + ; 1.1718 + 1.1719 +assign non_debug_exception_x = (system_call_exception == `TRUE) 1.1720 +`ifdef CFG_JTAG_ENABLED 1.1721 + || (reset_exception == `TRUE) 1.1722 +`endif 1.1723 +`ifdef CFG_BUS_ERRORS_ENABLED 1.1724 + || (instruction_bus_error_exception == `TRUE) 1.1725 + || (data_bus_error_exception == `TRUE) 1.1726 +`endif 1.1727 +`ifdef CFG_MC_DIVIDE_ENABLED 1.1728 + || (divide_by_zero_exception == `TRUE) 1.1729 +`endif 1.1730 +`ifdef CFG_INTERRUPTS_ENABLED 1.1731 + || ( (interrupt_exception == `TRUE) 1.1732 +`ifdef LM32_SINGLE_STEP_ENABLED 1.1733 + && (dc_ss == `FALSE) 1.1734 +`endif 1.1735 +`ifdef CFG_BUS_ERRORS_ENABLED 1.1736 + && (store_q_m == `FALSE) 1.1737 + && (D_CYC_O == `FALSE) 1.1738 +`endif 1.1739 + ) 1.1740 +`endif 1.1741 + ; 1.1742 + 1.1743 +assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE); 1.1744 +`else 1.1745 +assign exception_x = (system_call_exception == `TRUE) 1.1746 +`ifdef CFG_BUS_ERRORS_ENABLED 1.1747 + || (instruction_bus_error_exception == `TRUE) 1.1748 + || (data_bus_error_exception == `TRUE) 1.1749 +`endif 1.1750 +`ifdef CFG_MC_DIVIDE_ENABLED 1.1751 + || (divide_by_zero_exception == `TRUE) 1.1752 +`endif 1.1753 +`ifdef CFG_INTERRUPTS_ENABLED 1.1754 + || ( (interrupt_exception == `TRUE) 1.1755 +`ifdef LM32_SINGLE_STEP_ENABLED 1.1756 + && (dc_ss == `FALSE) 1.1757 +`endif 1.1758 +`ifdef CFG_BUS_ERRORS_ENABLED 1.1759 + && (store_q_m == `FALSE) 1.1760 + && (D_CYC_O == `FALSE) 1.1761 +`endif 1.1762 + ) 1.1763 +`endif 1.1764 + ; 1.1765 +`endif 1.1766 + 1.1767 +// Exception ID 1.1768 +always @(*) 1.1769 +begin 1.1770 +`ifdef CFG_DEBUG_ENABLED 1.1771 +`ifdef CFG_JTAG_ENABLED 1.1772 + if (reset_exception == `TRUE) 1.1773 + eid_x = `LM32_EID_RESET; 1.1774 + else 1.1775 +`endif 1.1776 +`ifdef CFG_BUS_ERRORS_ENABLED 1.1777 + if (data_bus_error_exception == `TRUE) 1.1778 + eid_x = `LM32_EID_DATA_BUS_ERROR; 1.1779 + else 1.1780 +`endif 1.1781 + if (breakpoint_exception == `TRUE) 1.1782 + eid_x = `LM32_EID_BREAKPOINT; 1.1783 + else 1.1784 +`endif 1.1785 +`ifdef CFG_BUS_ERRORS_ENABLED 1.1786 + if (data_bus_error_exception == `TRUE) 1.1787 + eid_x = `LM32_EID_DATA_BUS_ERROR; 1.1788 + else 1.1789 + if (instruction_bus_error_exception == `TRUE) 1.1790 + eid_x = `LM32_EID_INST_BUS_ERROR; 1.1791 + else 1.1792 +`endif 1.1793 +`ifdef CFG_DEBUG_ENABLED 1.1794 + if (watchpoint_exception == `TRUE) 1.1795 + eid_x = `LM32_EID_WATCHPOINT; 1.1796 + else 1.1797 +`endif 1.1798 +`ifdef CFG_MC_DIVIDE_ENABLED 1.1799 + if (divide_by_zero_exception == `TRUE) 1.1800 + eid_x = `LM32_EID_DIVIDE_BY_ZERO; 1.1801 + else 1.1802 +`endif 1.1803 +`ifdef CFG_INTERRUPTS_ENABLED 1.1804 + if ( (interrupt_exception == `TRUE) 1.1805 +`ifdef LM32_SINGLE_STEP_ENABLED 1.1806 + && (dc_ss == `FALSE) 1.1807 +`endif 1.1808 + ) 1.1809 + eid_x = `LM32_EID_INTERRUPT; 1.1810 + else 1.1811 +`endif 1.1812 + eid_x = `LM32_EID_SCALL; 1.1813 +end 1.1814 + 1.1815 +// Stall generation 1.1816 + 1.1817 +assign stall_a = (stall_f == `TRUE); 1.1818 + 1.1819 +assign stall_f = (stall_d == `TRUE); 1.1820 + 1.1821 +assign stall_d = (stall_x == `TRUE) 1.1822 + || ( (interlock == `TRUE) 1.1823 + && (kill_d == `FALSE) 1.1824 + ) 1.1825 + || ( ( (eret_d == `TRUE) 1.1826 + || (scall_d == `TRUE) 1.1827 + || (bus_error_d == `TRUE) 1.1828 + ) 1.1829 + && ( (load_q_x == `TRUE) 1.1830 + || (load_q_m == `TRUE) 1.1831 + || (store_q_x == `TRUE) 1.1832 + || (store_q_m == `TRUE) 1.1833 + || (D_CYC_O == `TRUE) 1.1834 + ) 1.1835 + && (kill_d == `FALSE) 1.1836 + ) 1.1837 +`ifdef CFG_DEBUG_ENABLED 1.1838 + || ( ( (break_d == `TRUE) 1.1839 + || (bret_d == `TRUE) 1.1840 + ) 1.1841 + && ( (load_q_x == `TRUE) 1.1842 + || (store_q_x == `TRUE) 1.1843 + || (load_q_m == `TRUE) 1.1844 + || (store_q_m == `TRUE) 1.1845 + || (D_CYC_O == `TRUE) 1.1846 + ) 1.1847 + && (kill_d == `FALSE) 1.1848 + ) 1.1849 +`endif 1.1850 + || ( (csr_write_enable_d == `TRUE) 1.1851 + && (load_q_x == `TRUE) 1.1852 + ) 1.1853 + ; 1.1854 + 1.1855 +assign stall_x = (stall_m == `TRUE) 1.1856 +`ifdef LM32_MC_ARITHMETIC_ENABLED 1.1857 + || ( (mc_stall_request_x == `TRUE) 1.1858 + && (kill_x == `FALSE) 1.1859 + ) 1.1860 +`endif 1.1861 +`ifdef CFG_IROM_ENABLED 1.1862 + // Stall load/store instruction in D stage if there is an ongoing store 1.1863 + // operation to instruction ROM in M stage 1.1864 + || ( (irom_stall_request_x == `TRUE) 1.1865 + && ( (load_d == `TRUE) 1.1866 + || (store_d == `TRUE) 1.1867 + ) 1.1868 + ) 1.1869 +`endif 1.1870 + ; 1.1871 + 1.1872 +assign stall_m = (stall_wb_load == `TRUE) 1.1873 +`ifdef CFG_SIZE_OVER_SPEED 1.1874 + || (D_CYC_O == `TRUE) 1.1875 +`else 1.1876 + || ( (D_CYC_O == `TRUE) 1.1877 + && ( (store_m == `TRUE) 1.1878 + /* 1.1879 + Bug: Following loop does not allow interrupts to be services since 1.1880 + either D_CYC_O or store_m is always high during entire duration of 1.1881 + loop. 1.1882 + L1: addi r1, r1, 1 1.1883 + sw (r2,0), r1 1.1884 + bi L1 1.1885 + 1.1886 + Introduce a single-cycle stall when a wishbone cycle is in progress 1.1887 + and a new store instruction is in Execute stage and a interrupt 1.1888 + exception has occured. This stall will ensure that D_CYC_O and 1.1889 + store_m will both be low for one cycle. 1.1890 + */ 1.1891 + || ((store_x == `TRUE) && (interrupt_exception == `TRUE)) 1.1892 + || (load_m == `TRUE) 1.1893 + || (load_x == `TRUE) 1.1894 + ) 1.1895 + ) 1.1896 +`endif 1.1897 +`ifdef CFG_DCACHE_ENABLED 1.1898 + || (dcache_stall_request == `TRUE) // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted 1.1899 +`endif 1.1900 +`ifdef CFG_ICACHE_ENABLED 1.1901 + || (icache_stall_request == `TRUE) // Pipeline needs to be stalled otherwise branches may be lost 1.1902 + || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE))) 1.1903 +`else 1.1904 +`ifdef CFG_IWB_ENABLED 1.1905 + || (I_CYC_O == `TRUE) 1.1906 +`endif 1.1907 +`endif 1.1908 +`ifdef CFG_USER_ENABLED 1.1909 + || ( (user_valid == `TRUE) // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe) 1.1910 + && (user_complete == `FALSE) 1.1911 + ) 1.1912 +`endif 1.1913 + ; 1.1914 + 1.1915 +// Qualify state changing control signals 1.1916 +`ifdef LM32_MC_ARITHMETIC_ENABLED 1.1917 +assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE); 1.1918 +`endif 1.1919 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.1920 +assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE); 1.1921 +assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE); 1.1922 +`endif 1.1923 +`ifdef CFG_MC_MULTIPLY_ENABLED 1.1924 +assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE); 1.1925 +`endif 1.1926 +`ifdef CFG_MC_DIVIDE_ENABLED 1.1927 +assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE); 1.1928 +assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE); 1.1929 +`endif 1.1930 +assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE); 1.1931 +assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE); 1.1932 +assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE); 1.1933 +`ifdef CFG_DEBUG_ENABLED 1.1934 +assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE); 1.1935 +`endif 1.1936 +assign load_q_x = (load_x == `TRUE) 1.1937 + && (q_x == `TRUE) 1.1938 +`ifdef CFG_DEBUG_ENABLED 1.1939 + && (bp_match == `FALSE) 1.1940 +`endif 1.1941 + ; 1.1942 +assign store_q_x = (store_x == `TRUE) 1.1943 + && (q_x == `TRUE) 1.1944 +`ifdef CFG_DEBUG_ENABLED 1.1945 + && (bp_match == `FALSE) 1.1946 +`endif 1.1947 + ; 1.1948 +`ifdef CFG_USER_ENABLED 1.1949 +assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE); 1.1950 +`endif 1.1951 +assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE); 1.1952 +assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE); 1.1953 +assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE); 1.1954 +`ifdef CFG_DEBUG_ENABLED 1.1955 +assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE)); 1.1956 +assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE)); 1.1957 +`else 1.1958 +assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE)); 1.1959 +`endif 1.1960 +// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately) 1.1961 +assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE); 1.1962 +assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE); 1.1963 +assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE); 1.1964 +// The enable that actually does write the registers needs to be qualified with kill 1.1965 +assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE); 1.1966 + 1.1967 +// Configuration (CFG) CSR 1.1968 +assign cfg = { 1.1969 + `LM32_REVISION, 1.1970 + watchpoints[3:0], 1.1971 + breakpoints[3:0], 1.1972 + interrupts[5:0], 1.1973 +`ifdef CFG_JTAG_UART_ENABLED 1.1974 + `TRUE, 1.1975 +`else 1.1976 + `FALSE, 1.1977 +`endif 1.1978 +`ifdef CFG_ROM_DEBUG_ENABLED 1.1979 + `TRUE, 1.1980 +`else 1.1981 + `FALSE, 1.1982 +`endif 1.1983 +`ifdef CFG_HW_DEBUG_ENABLED 1.1984 + `TRUE, 1.1985 +`else 1.1986 + `FALSE, 1.1987 +`endif 1.1988 +`ifdef CFG_DEBUG_ENABLED 1.1989 + `TRUE, 1.1990 +`else 1.1991 + `FALSE, 1.1992 +`endif 1.1993 +`ifdef CFG_ICACHE_ENABLED 1.1994 + `TRUE, 1.1995 +`else 1.1996 + `FALSE, 1.1997 +`endif 1.1998 +`ifdef CFG_DCACHE_ENABLED 1.1999 + `TRUE, 1.2000 +`else 1.2001 + `FALSE, 1.2002 +`endif 1.2003 +`ifdef CFG_CYCLE_COUNTER_ENABLED 1.2004 + `TRUE, 1.2005 +`else 1.2006 + `FALSE, 1.2007 +`endif 1.2008 +`ifdef CFG_USER_ENABLED 1.2009 + `TRUE, 1.2010 +`else 1.2011 + `FALSE, 1.2012 +`endif 1.2013 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.2014 + `TRUE, 1.2015 +`else 1.2016 + `FALSE, 1.2017 +`endif 1.2018 +`ifdef LM32_BARREL_SHIFT_ENABLED 1.2019 + `TRUE, 1.2020 +`else 1.2021 + `FALSE, 1.2022 +`endif 1.2023 +`ifdef CFG_MC_DIVIDE_ENABLED 1.2024 + `TRUE, 1.2025 +`else 1.2026 + `FALSE, 1.2027 +`endif 1.2028 +`ifdef LM32_MULTIPLY_ENABLED 1.2029 + `TRUE 1.2030 +`else 1.2031 + `FALSE 1.2032 +`endif 1.2033 + }; 1.2034 + 1.2035 +assign cfg2 = { 1.2036 + 30'b0, 1.2037 +`ifdef CFG_IROM_ENABLED 1.2038 + `TRUE, 1.2039 +`else 1.2040 + `FALSE, 1.2041 +`endif 1.2042 +`ifdef CFG_DRAM_ENABLED 1.2043 + `TRUE 1.2044 +`else 1.2045 + `FALSE 1.2046 +`endif 1.2047 + }; 1.2048 + 1.2049 +// Cache flush 1.2050 +`ifdef CFG_ICACHE_ENABLED 1.2051 +assign iflush = (csr_write_enable_d == `TRUE) 1.2052 + && (csr_d == `LM32_CSR_ICC) 1.2053 + && (stall_d == `FALSE) 1.2054 + && (kill_d == `FALSE) 1.2055 + && (valid_d == `TRUE); 1.2056 +`endif 1.2057 +`ifdef CFG_DCACHE_ENABLED 1.2058 +assign dflush_x = (csr_write_enable_q_x == `TRUE) 1.2059 + && (csr_x == `LM32_CSR_DCC); 1.2060 +`endif 1.2061 + 1.2062 +// Extract CSR index 1.2063 +assign csr_d = read_idx_0_d[`LM32_CSR_RNG]; 1.2064 + 1.2065 +// CSR reads 1.2066 +always @(*) 1.2067 +begin 1.2068 + case (csr_x) 1.2069 +`ifdef CFG_INTERRUPTS_ENABLED 1.2070 + `LM32_CSR_IE, 1.2071 + `LM32_CSR_IM, 1.2072 + `LM32_CSR_IP: csr_read_data_x = interrupt_csr_read_data_x; 1.2073 +`endif 1.2074 +`ifdef CFG_CYCLE_COUNTER_ENABLED 1.2075 + `LM32_CSR_CC: csr_read_data_x = cc; 1.2076 +`endif 1.2077 + `LM32_CSR_CFG: csr_read_data_x = cfg; 1.2078 + `LM32_CSR_EBA: csr_read_data_x = {eba, 8'h00}; 1.2079 +`ifdef CFG_DEBUG_ENABLED 1.2080 + `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00}; 1.2081 +`endif 1.2082 +`ifdef CFG_JTAG_UART_ENABLED 1.2083 + `LM32_CSR_JTX: csr_read_data_x = jtx_csr_read_data; 1.2084 + `LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data; 1.2085 +`endif 1.2086 + `LM32_CSR_CFG2: csr_read_data_x = cfg2; 1.2087 + 1.2088 + default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}}; 1.2089 + endcase 1.2090 +end 1.2091 + 1.2092 +///////////////////////////////////////////////////// 1.2093 +// Sequential Logic 1.2094 +///////////////////////////////////////////////////// 1.2095 + 1.2096 +// Exception Base Address (EBA) CSR 1.2097 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.2098 +begin 1.2099 + if (rst_i == `TRUE) 1.2100 + eba <= eba_reset[`LM32_PC_WIDTH+2-1:8]; 1.2101 + else 1.2102 + begin 1.2103 + if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE)) 1.2104 + eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.2105 +`ifdef CFG_HW_DEBUG_ENABLED 1.2106 + if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA)) 1.2107 + eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.2108 +`endif 1.2109 + end 1.2110 +end 1.2111 + 1.2112 +`ifdef CFG_DEBUG_ENABLED 1.2113 +// Debug Exception Base Address (DEBA) CSR 1.2114 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.2115 +begin 1.2116 + if (rst_i == `TRUE) 1.2117 + deba <= deba_reset[`LM32_PC_WIDTH+2-1:8]; 1.2118 + else 1.2119 + begin 1.2120 + if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE)) 1.2121 + deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.2122 +`ifdef CFG_HW_DEBUG_ENABLED 1.2123 + if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA)) 1.2124 + deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.2125 +`endif 1.2126 + end 1.2127 +end 1.2128 +`endif 1.2129 + 1.2130 +// Cycle Counter (CC) CSR 1.2131 +`ifdef CFG_CYCLE_COUNTER_ENABLED 1.2132 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.2133 +begin 1.2134 + if (rst_i == `TRUE) 1.2135 + cc <= {`LM32_WORD_WIDTH{1'b0}}; 1.2136 + else 1.2137 + cc <= cc + 1'b1; 1.2138 +end 1.2139 +`endif 1.2140 + 1.2141 +`ifdef CFG_BUS_ERRORS_ENABLED 1.2142 +// Watch for data bus errors 1.2143 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.2144 +begin 1.2145 + if (rst_i == `TRUE) 1.2146 + data_bus_error_seen <= `FALSE; 1.2147 + else 1.2148 + begin 1.2149 + // Set flag when bus error is detected 1.2150 + if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE)) 1.2151 + data_bus_error_seen <= `TRUE; 1.2152 + // Clear flag when exception is taken 1.2153 + if ((exception_m == `TRUE) && (kill_m == `FALSE)) 1.2154 + data_bus_error_seen <= `FALSE; 1.2155 + end 1.2156 +end 1.2157 +`endif 1.2158 + 1.2159 +// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not 1.2160 + 1.2161 +`ifdef CFG_ICACHE_ENABLED 1.2162 +`ifdef CFG_DCACHE_ENABLED 1.2163 +always @(*) 1.2164 +begin 1.2165 + if ( (icache_refill_request == `TRUE) 1.2166 + || (dcache_refill_request == `TRUE) 1.2167 + ) 1.2168 + valid_a = `FALSE; 1.2169 + else if ( (icache_restart_request == `TRUE) 1.2170 + || (dcache_restart_request == `TRUE) 1.2171 + ) 1.2172 + valid_a = `TRUE; 1.2173 + else 1.2174 + valid_a = !icache_refilling && !dcache_refilling; 1.2175 +end 1.2176 +`else 1.2177 +always @(*) 1.2178 +begin 1.2179 + if (icache_refill_request == `TRUE) 1.2180 + valid_a = `FALSE; 1.2181 + else if (icache_restart_request == `TRUE) 1.2182 + valid_a = `TRUE; 1.2183 + else 1.2184 + valid_a = !icache_refilling; 1.2185 +end 1.2186 +`endif 1.2187 +`else 1.2188 +`ifdef CFG_DCACHE_ENABLED 1.2189 +always @(*) 1.2190 +begin 1.2191 + if (dcache_refill_request == `TRUE) 1.2192 + valid_a = `FALSE; 1.2193 + else if (dcache_restart_request == `TRUE) 1.2194 + valid_a = `TRUE; 1.2195 + else 1.2196 + valid_a = !dcache_refilling; 1.2197 +end 1.2198 +`endif 1.2199 +`endif 1.2200 + 1.2201 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.2202 +begin 1.2203 + if (rst_i == `TRUE) 1.2204 + begin 1.2205 + valid_f <= `FALSE; 1.2206 + valid_d <= `FALSE; 1.2207 + valid_x <= `FALSE; 1.2208 + valid_m <= `FALSE; 1.2209 + valid_w <= `FALSE; 1.2210 + end 1.2211 + else 1.2212 + begin 1.2213 + if ((kill_f == `TRUE) || (stall_a == `FALSE)) 1.2214 +`ifdef LM32_CACHE_ENABLED 1.2215 + valid_f <= valid_a; 1.2216 +`else 1.2217 + valid_f <= `TRUE; 1.2218 +`endif 1.2219 + else if (stall_f == `FALSE) 1.2220 + valid_f <= `FALSE; 1.2221 + 1.2222 + if (kill_d == `TRUE) 1.2223 + valid_d <= `FALSE; 1.2224 + else if (stall_f == `FALSE) 1.2225 + valid_d <= valid_f & !kill_f; 1.2226 + else if (stall_d == `FALSE) 1.2227 + valid_d <= `FALSE; 1.2228 + 1.2229 + if (stall_d == `FALSE) 1.2230 + valid_x <= valid_d & !kill_d; 1.2231 + else if (kill_x == `TRUE) 1.2232 + valid_x <= `FALSE; 1.2233 + else if (stall_x == `FALSE) 1.2234 + valid_x <= `FALSE; 1.2235 + 1.2236 + if (kill_m == `TRUE) 1.2237 + valid_m <= `FALSE; 1.2238 + else if (stall_x == `FALSE) 1.2239 + valid_m <= valid_x & !kill_x; 1.2240 + else if (stall_m == `FALSE) 1.2241 + valid_m <= `FALSE; 1.2242 + 1.2243 + if (stall_m == `FALSE) 1.2244 + valid_w <= valid_m & !kill_m; 1.2245 + else 1.2246 + valid_w <= `FALSE; 1.2247 + end 1.2248 +end 1.2249 + 1.2250 +// Microcode pipeline registers 1.2251 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.2252 +begin 1.2253 + if (rst_i == `TRUE) 1.2254 + begin 1.2255 +`ifdef CFG_USER_ENABLED 1.2256 + user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}}; 1.2257 +`endif 1.2258 + operand_0_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.2259 + operand_1_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.2260 + store_operand_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.2261 + branch_target_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.2262 + x_result_sel_csr_x <= `FALSE; 1.2263 +`ifdef LM32_MC_ARITHMETIC_ENABLED 1.2264 + x_result_sel_mc_arith_x <= `FALSE; 1.2265 +`endif 1.2266 +`ifdef LM32_NO_BARREL_SHIFT 1.2267 + x_result_sel_shift_x <= `FALSE; 1.2268 +`endif 1.2269 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.2270 + x_result_sel_sext_x <= `FALSE; 1.2271 +`endif 1.2272 + x_result_sel_logic_x <= `FALSE; 1.2273 +`ifdef CFG_USER_ENABLED 1.2274 + x_result_sel_user_x <= `FALSE; 1.2275 +`endif 1.2276 + x_result_sel_add_x <= `FALSE; 1.2277 + m_result_sel_compare_x <= `FALSE; 1.2278 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.2279 + m_result_sel_shift_x <= `FALSE; 1.2280 +`endif 1.2281 + w_result_sel_load_x <= `FALSE; 1.2282 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.2283 + w_result_sel_mul_x <= `FALSE; 1.2284 +`endif 1.2285 + x_bypass_enable_x <= `FALSE; 1.2286 + m_bypass_enable_x <= `FALSE; 1.2287 + write_enable_x <= `FALSE; 1.2288 + write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.2289 + csr_x <= {`LM32_CSR_WIDTH{1'b0}}; 1.2290 + load_x <= `FALSE; 1.2291 + store_x <= `FALSE; 1.2292 + size_x <= {`LM32_SIZE_WIDTH{1'b0}}; 1.2293 + sign_extend_x <= `FALSE; 1.2294 + adder_op_x <= `FALSE; 1.2295 + adder_op_x_n <= `FALSE; 1.2296 + logic_op_x <= 4'h0; 1.2297 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.2298 + direction_x <= `FALSE; 1.2299 +`endif 1.2300 +`ifdef CFG_ROTATE_ENABLED 1.2301 + rotate_x <= `FALSE; 1.2302 + 1.2303 +`endif 1.2304 + branch_x <= `FALSE; 1.2305 + branch_predict_x <= `FALSE; 1.2306 + branch_predict_taken_x <= `FALSE; 1.2307 + condition_x <= `LM32_CONDITION_U1; 1.2308 +`ifdef CFG_DEBUG_ENABLED 1.2309 + break_x <= `FALSE; 1.2310 +`endif 1.2311 + scall_x <= `FALSE; 1.2312 + eret_x <= `FALSE; 1.2313 +`ifdef CFG_DEBUG_ENABLED 1.2314 + bret_x <= `FALSE; 1.2315 +`endif 1.2316 +`ifdef CFG_BUS_ERRORS_ENABLED 1.2317 + bus_error_x <= `FALSE; 1.2318 + data_bus_error_exception_m <= `FALSE; 1.2319 +`endif 1.2320 + csr_write_enable_x <= `FALSE; 1.2321 + operand_m <= {`LM32_WORD_WIDTH{1'b0}}; 1.2322 + branch_target_m <= {`LM32_WORD_WIDTH{1'b0}}; 1.2323 + m_result_sel_compare_m <= `FALSE; 1.2324 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.2325 + m_result_sel_shift_m <= `FALSE; 1.2326 +`endif 1.2327 + w_result_sel_load_m <= `FALSE; 1.2328 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.2329 + w_result_sel_mul_m <= `FALSE; 1.2330 +`endif 1.2331 + m_bypass_enable_m <= `FALSE; 1.2332 + branch_m <= `FALSE; 1.2333 + branch_predict_m <= `FALSE; 1.2334 + branch_predict_taken_m <= `FALSE; 1.2335 + exception_m <= `FALSE; 1.2336 + load_m <= `FALSE; 1.2337 + store_m <= `FALSE; 1.2338 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.2339 + direction_m <= `FALSE; 1.2340 +`endif 1.2341 + write_enable_m <= `FALSE; 1.2342 + write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.2343 + condition_met_m <= `FALSE; 1.2344 +`ifdef CFG_DCACHE_ENABLED 1.2345 + dflush_m <= `FALSE; 1.2346 +`endif 1.2347 +`ifdef CFG_DEBUG_ENABLED 1.2348 + debug_exception_m <= `FALSE; 1.2349 + non_debug_exception_m <= `FALSE; 1.2350 +`endif 1.2351 + operand_w <= {`LM32_WORD_WIDTH{1'b0}}; 1.2352 + w_result_sel_load_w <= `FALSE; 1.2353 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.2354 + w_result_sel_mul_w <= `FALSE; 1.2355 +`endif 1.2356 + write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.2357 + write_enable_w <= `FALSE; 1.2358 +`ifdef CFG_DEBUG_ENABLED 1.2359 + debug_exception_w <= `FALSE; 1.2360 + non_debug_exception_w <= `FALSE; 1.2361 +`else 1.2362 + exception_w <= `FALSE; 1.2363 +`endif 1.2364 +`ifdef CFG_BUS_ERRORS_ENABLED 1.2365 + memop_pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.2366 +`endif 1.2367 + end 1.2368 + else 1.2369 + begin 1.2370 + // D/X stage registers 1.2371 + 1.2372 + if (stall_x == `FALSE) 1.2373 + begin 1.2374 +`ifdef CFG_USER_ENABLED 1.2375 + user_opcode <= user_opcode_d; 1.2376 +`endif 1.2377 + operand_0_x <= d_result_0; 1.2378 + operand_1_x <= d_result_1; 1.2379 + store_operand_x <= bypass_data_1; 1.2380 + branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 1.2381 + x_result_sel_csr_x <= x_result_sel_csr_d; 1.2382 +`ifdef LM32_MC_ARITHMETIC_ENABLED 1.2383 + x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d; 1.2384 +`endif 1.2385 +`ifdef LM32_NO_BARREL_SHIFT 1.2386 + x_result_sel_shift_x <= x_result_sel_shift_d; 1.2387 +`endif 1.2388 +`ifdef CFG_SIGN_EXTEND_ENABLED 1.2389 + x_result_sel_sext_x <= x_result_sel_sext_d; 1.2390 +`endif 1.2391 + x_result_sel_logic_x <= x_result_sel_logic_d; 1.2392 +`ifdef CFG_USER_ENABLED 1.2393 + x_result_sel_user_x <= x_result_sel_user_d; 1.2394 +`endif 1.2395 + x_result_sel_add_x <= x_result_sel_add_d; 1.2396 + m_result_sel_compare_x <= m_result_sel_compare_d; 1.2397 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.2398 + m_result_sel_shift_x <= m_result_sel_shift_d; 1.2399 +`endif 1.2400 + w_result_sel_load_x <= w_result_sel_load_d; 1.2401 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.2402 + w_result_sel_mul_x <= w_result_sel_mul_d; 1.2403 +`endif 1.2404 + x_bypass_enable_x <= x_bypass_enable_d; 1.2405 + m_bypass_enable_x <= m_bypass_enable_d; 1.2406 + load_x <= load_d; 1.2407 + store_x <= store_d; 1.2408 + branch_x <= branch_d; 1.2409 + branch_predict_x <= branch_predict_d; 1.2410 + branch_predict_taken_x <= branch_predict_taken_d; 1.2411 + write_idx_x <= write_idx_d; 1.2412 + csr_x <= csr_d; 1.2413 + size_x <= size_d; 1.2414 + sign_extend_x <= sign_extend_d; 1.2415 + adder_op_x <= adder_op_d; 1.2416 + adder_op_x_n <= ~adder_op_d; 1.2417 + logic_op_x <= logic_op_d; 1.2418 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.2419 + direction_x <= direction_d; 1.2420 +`endif 1.2421 +`ifdef CFG_ROTATE_ENABLED 1.2422 + rotate_x <= rotate_d; 1.2423 +`endif 1.2424 + condition_x <= condition_d; 1.2425 + csr_write_enable_x <= csr_write_enable_d; 1.2426 +`ifdef CFG_DEBUG_ENABLED 1.2427 + break_x <= break_d; 1.2428 +`endif 1.2429 + scall_x <= scall_d; 1.2430 +`ifdef CFG_BUS_ERRORS_ENABLED 1.2431 + bus_error_x <= bus_error_d; 1.2432 +`endif 1.2433 + eret_x <= eret_d; 1.2434 +`ifdef CFG_DEBUG_ENABLED 1.2435 + bret_x <= bret_d; 1.2436 +`endif 1.2437 + write_enable_x <= write_enable_d; 1.2438 + end 1.2439 + 1.2440 + // X/M stage registers 1.2441 + 1.2442 + if (stall_m == `FALSE) 1.2443 + begin 1.2444 + operand_m <= x_result; 1.2445 + m_result_sel_compare_m <= m_result_sel_compare_x; 1.2446 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.2447 + m_result_sel_shift_m <= m_result_sel_shift_x; 1.2448 +`endif 1.2449 + if (exception_x == `TRUE) 1.2450 + begin 1.2451 + w_result_sel_load_m <= `FALSE; 1.2452 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.2453 + w_result_sel_mul_m <= `FALSE; 1.2454 +`endif 1.2455 + end 1.2456 + else 1.2457 + begin 1.2458 + w_result_sel_load_m <= w_result_sel_load_x; 1.2459 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.2460 + w_result_sel_mul_m <= w_result_sel_mul_x; 1.2461 +`endif 1.2462 + end 1.2463 + m_bypass_enable_m <= m_bypass_enable_x; 1.2464 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.2465 + direction_m <= direction_x; 1.2466 +`endif 1.2467 + load_m <= load_x; 1.2468 + store_m <= store_x; 1.2469 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.2470 + branch_m <= branch_x && !branch_taken_x; 1.2471 +`else 1.2472 + branch_m <= branch_x; 1.2473 + branch_predict_m <= branch_predict_x; 1.2474 + branch_predict_taken_m <= branch_predict_taken_x; 1.2475 +`endif 1.2476 +`ifdef CFG_DEBUG_ENABLED 1.2477 + // Data bus errors are generated by the wishbone and are 1.2478 + // made known to the processor only in next cycle (as a 1.2479 + // non-debug exception). A break instruction can be seen 1.2480 + // in same cycle (causing a debug exception). Handle non 1.2481 + // -debug exception first! 1.2482 + if (non_debug_exception_x == `TRUE) 1.2483 + write_idx_m <= `LM32_EA_REG; 1.2484 + else if (debug_exception_x == `TRUE) 1.2485 + write_idx_m <= `LM32_BA_REG; 1.2486 + else 1.2487 + write_idx_m <= write_idx_x; 1.2488 +`else 1.2489 + if (exception_x == `TRUE) 1.2490 + write_idx_m <= `LM32_EA_REG; 1.2491 + else 1.2492 + write_idx_m <= write_idx_x; 1.2493 +`endif 1.2494 + condition_met_m <= condition_met_x; 1.2495 +`ifdef CFG_DEBUG_ENABLED 1.2496 + if (exception_x == `TRUE) 1.2497 + if ((dc_re == `TRUE) 1.2498 + || ((debug_exception_x == `TRUE) 1.2499 + && (non_debug_exception_x == `FALSE))) 1.2500 + branch_target_m <= {deba, eid_x, {3{1'b0}}}; 1.2501 + else 1.2502 + branch_target_m <= {eba, eid_x, {3{1'b0}}}; 1.2503 + else 1.2504 + branch_target_m <= branch_target_x; 1.2505 +`else 1.2506 + branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 1.2507 +`endif 1.2508 +`ifdef CFG_TRACE_ENABLED 1.2509 + eid_m <= eid_x; 1.2510 +`endif 1.2511 +`ifdef CFG_DCACHE_ENABLED 1.2512 + dflush_m <= dflush_x; 1.2513 +`endif 1.2514 + eret_m <= eret_q_x; 1.2515 +`ifdef CFG_DEBUG_ENABLED 1.2516 + bret_m <= bret_q_x; 1.2517 +`endif 1.2518 + write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x; 1.2519 +`ifdef CFG_DEBUG_ENABLED 1.2520 + debug_exception_m <= debug_exception_x; 1.2521 + non_debug_exception_m <= non_debug_exception_x; 1.2522 +`endif 1.2523 + end 1.2524 + 1.2525 + // State changing regs 1.2526 + if (stall_m == `FALSE) 1.2527 + begin 1.2528 + if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 1.2529 + exception_m <= `TRUE; 1.2530 + else 1.2531 + exception_m <= `FALSE; 1.2532 +`ifdef CFG_BUS_ERRORS_ENABLED 1.2533 + data_bus_error_exception_m <= (data_bus_error_exception == `TRUE) 1.2534 +`ifdef CFG_DEBUG_ENABLED 1.2535 + && (reset_exception == `FALSE) 1.2536 +`endif 1.2537 + ; 1.2538 +`endif 1.2539 + end 1.2540 + 1.2541 + // M/W stage registers 1.2542 +`ifdef CFG_BUS_ERRORS_ENABLED 1.2543 + operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 1.2544 +`else 1.2545 + operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 1.2546 +`endif 1.2547 + w_result_sel_load_w <= w_result_sel_load_m; 1.2548 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.2549 + w_result_sel_mul_w <= w_result_sel_mul_m; 1.2550 +`endif 1.2551 + write_idx_w <= write_idx_m; 1.2552 +`ifdef CFG_TRACE_ENABLED 1.2553 + eid_w <= eid_m; 1.2554 + eret_w <= eret_m; 1.2555 +`ifdef CFG_DEBUG_ENABLED 1.2556 + bret_w <= bret_m; 1.2557 +`endif 1.2558 +`endif 1.2559 + write_enable_w <= write_enable_m; 1.2560 +`ifdef CFG_DEBUG_ENABLED 1.2561 + debug_exception_w <= debug_exception_m; 1.2562 + non_debug_exception_w <= non_debug_exception_m; 1.2563 +`else 1.2564 + exception_w <= exception_m; 1.2565 +`endif 1.2566 +`ifdef CFG_BUS_ERRORS_ENABLED 1.2567 + if ( (stall_m == `FALSE) 1.2568 + && ( (load_q_m == `TRUE) 1.2569 + || (store_q_m == `TRUE) 1.2570 + ) 1.2571 + ) 1.2572 + memop_pc_w <= pc_m; 1.2573 +`endif 1.2574 + end 1.2575 +end 1.2576 + 1.2577 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.2578 +// Buffer data read from register file, in case a stall occurs, and watch for 1.2579 +// any writes to the modified registers 1.2580 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.2581 +begin 1.2582 + if (rst_i == `TRUE) 1.2583 + begin 1.2584 + use_buf <= `FALSE; 1.2585 + reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}}; 1.2586 + reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}}; 1.2587 + end 1.2588 + else 1.2589 + begin 1.2590 + if (stall_d == `FALSE) 1.2591 + use_buf <= `FALSE; 1.2592 + else if (use_buf == `FALSE) 1.2593 + begin 1.2594 + reg_data_buf_0 <= reg_data_live_0; 1.2595 + reg_data_buf_1 <= reg_data_live_1; 1.2596 + use_buf <= `TRUE; 1.2597 + end 1.2598 + if (reg_write_enable_q_w == `TRUE) 1.2599 + begin 1.2600 + if (write_idx_w == read_idx_0_d) 1.2601 + reg_data_buf_0 <= w_result; 1.2602 + if (write_idx_w == read_idx_1_d) 1.2603 + reg_data_buf_1 <= w_result; 1.2604 + end 1.2605 + end 1.2606 +end 1.2607 +`endif 1.2608 + 1.2609 +`ifdef LM32_EBR_REGISTER_FILE 1.2610 +`else 1.2611 +// Register file write port 1.2612 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.2613 +begin 1.2614 + if (rst_i == `TRUE) begin 1.2615 + registers[0] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2616 + registers[1] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2617 + registers[2] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2618 + registers[3] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2619 + registers[4] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2620 + registers[5] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2621 + registers[6] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2622 + registers[7] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2623 + registers[8] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2624 + registers[9] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2625 + registers[10] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2626 + registers[11] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2627 + registers[12] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2628 + registers[13] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2629 + registers[14] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2630 + registers[15] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2631 + registers[16] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2632 + registers[17] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2633 + registers[18] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2634 + registers[19] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2635 + registers[20] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2636 + registers[21] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2637 + registers[22] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2638 + registers[23] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2639 + registers[24] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2640 + registers[25] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2641 + registers[26] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2642 + registers[27] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2643 + registers[28] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2644 + registers[29] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2645 + registers[30] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2646 + registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 1.2647 + end 1.2648 + else begin 1.2649 + if (reg_write_enable_q_w == `TRUE) 1.2650 + registers[write_idx_w] <= w_result; 1.2651 + end 1.2652 +end 1.2653 +`endif 1.2654 + 1.2655 +`ifdef CFG_TRACE_ENABLED 1.2656 +// PC tracing logic 1.2657 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.2658 +begin 1.2659 + if (rst_i == `TRUE) 1.2660 + begin 1.2661 + trace_pc_valid <= `FALSE; 1.2662 + trace_pc <= {`LM32_PC_WIDTH{1'b0}}; 1.2663 + trace_exception <= `FALSE; 1.2664 + trace_eid <= `LM32_EID_RESET; 1.2665 + trace_eret <= `FALSE; 1.2666 +`ifdef CFG_DEBUG_ENABLED 1.2667 + trace_bret <= `FALSE; 1.2668 +`endif 1.2669 + pc_c <= `CFG_EBA_RESET/4; 1.2670 + end 1.2671 + else 1.2672 + begin 1.2673 + trace_pc_valid <= `FALSE; 1.2674 + // Has an exception occured 1.2675 +`ifdef CFG_DEBUG_ENABLED 1.2676 + if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE)) 1.2677 +`else 1.2678 + if (exception_q_w == `TRUE) 1.2679 +`endif 1.2680 + begin 1.2681 + trace_exception <= `TRUE; 1.2682 + trace_pc_valid <= `TRUE; 1.2683 + trace_pc <= pc_w; 1.2684 + trace_eid <= eid_w; 1.2685 + end 1.2686 + else 1.2687 + trace_exception <= `FALSE; 1.2688 + 1.2689 + if ((valid_w == `TRUE) && (!kill_w)) 1.2690 + begin 1.2691 + // An instruction is commiting. Determine if it is non-sequential 1.2692 + if (pc_c + 1'b1 != pc_w) 1.2693 + begin 1.2694 + // Non-sequential instruction 1.2695 + trace_pc_valid <= `TRUE; 1.2696 + trace_pc <= pc_w; 1.2697 + end 1.2698 + // Record PC so we can determine if next instruction is sequential or not 1.2699 + pc_c <= pc_w; 1.2700 + // Indicate if it was an eret/bret instruction 1.2701 + trace_eret <= eret_w; 1.2702 +`ifdef CFG_DEBUG_ENABLED 1.2703 + trace_bret <= bret_w; 1.2704 +`endif 1.2705 + end 1.2706 + else 1.2707 + begin 1.2708 + trace_eret <= `FALSE; 1.2709 +`ifdef CFG_DEBUG_ENABLED 1.2710 + trace_bret <= `FALSE; 1.2711 +`endif 1.2712 + end 1.2713 + end 1.2714 +end 1.2715 +`endif 1.2716 + 1.2717 +///////////////////////////////////////////////////// 1.2718 +// Behavioural Logic 1.2719 +///////////////////////////////////////////////////// 1.2720 + 1.2721 +// synthesis translate_off 1.2722 + 1.2723 +// Reset register 0. Only needed for simulation. 1.2724 +initial 1.2725 +begin 1.2726 +`ifdef LM32_EBR_REGISTER_FILE 1.2727 + reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}}; 1.2728 + reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}}; 1.2729 +`else 1.2730 + registers[0] = {`LM32_WORD_WIDTH{1'b0}}; 1.2731 +`endif 1.2732 +end 1.2733 + 1.2734 +// synthesis translate_on 1.2735 + 1.2736 +endmodule