1.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_include.v 1.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 +++ b/lm32_include.v Sun Apr 04 20:40:03 2010 +0100 1.4 @@ -0,0 +1,329 @@ 1.5 +// ============================================================================= 1.6 +// COPYRIGHT NOTICE 1.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 +// ALL RIGHTS RESERVED 1.9 +// This confidential and proprietary software may be used only as authorised by 1.10 +// a licensing agreement from Lattice Semiconductor Corporation. 1.11 +// The entire notice above must be reproduced on all authorized copies and 1.12 +// copies may only be made to the extent permitted by a licensing agreement from 1.13 +// Lattice Semiconductor Corporation. 1.14 +// 1.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 +// U.S.A email: techsupport@latticesemi.com 1.19 +// =============================================================================/ 1.20 +// FILE DETAILS 1.21 +// Project : LatticeMico32 1.22 +// File : lm32_include.v 1.23 +// Title : CPU global macros 1.24 +// Version : 6.1.17 1.25 +// : Initial Release 1.26 +// Version : 7.0SP2, 3.0 1.27 +// : No Change 1.28 +// Version : 3.1 1.29 +// : No Change 1.30 +// Version : 3.2 1.31 +// : No Change 1.32 +// Version : 3.3 1.33 +// : Support for extended configuration register 1.34 +// ============================================================================= 1.35 + 1.36 +`ifdef LM32_INCLUDE_V 1.37 +`else 1.38 +`define LM32_INCLUDE_V 1.39 + 1.40 +// Configuration options 1.41 +`include "system_conf.v" 1.42 + 1.43 +`ifdef TRUE 1.44 +`else 1.45 +`define TRUE 1'b1 1.46 +`define FALSE 1'b0 1.47 +`define TRUE_N 1'b0 1.48 +`define FALSE_N 1'b1 1.49 +`endif 1.50 + 1.51 +// Wishbone configuration 1.52 +`define CFG_IWB_ENABLED 1.53 +`define CFG_DWB_ENABLED 1.54 + 1.55 +// Data-path width 1.56 +`define LM32_WORD_WIDTH 32 1.57 +`define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0 1.58 +`define LM32_SHIFT_WIDTH 5 1.59 +`define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0 1.60 +`define LM32_BYTE_SELECT_WIDTH 4 1.61 +`define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0 1.62 + 1.63 +// Register file size 1.64 +`define LM32_REGISTERS 32 1.65 +`define LM32_REG_IDX_WIDTH 5 1.66 +`define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0 1.67 + 1.68 +// Standard register numbers 1.69 +`define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29 1.70 +`define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30 1.71 +`define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31 1.72 + 1.73 +// Range of Program Counter. Two LSBs are always 0. 1.74 +// `ifdef CFG_ICACHE_ENABLED 1.75 +// `define LM32_PC_WIDTH (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2) 1.76 +// `else 1.77 +// `ifdef CFG_IWB_ENABLED 1.78 +`define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2) 1.79 +// `else 1.80 +// `define LM32_PC_WIDTH `LM32_IROM_ADDRESS_WIDTH 1.81 +// `endif 1.82 +// `endif 1.83 +`define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2 1.84 + 1.85 +// Range of an instruction 1.86 +`define LM32_INSTRUCTION_WIDTH 32 1.87 +`define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0 1.88 + 1.89 +// Adder operation 1.90 +`define LM32_ADDER_OP_ADD 1'b0 1.91 +`define LM32_ADDER_OP_SUBTRACT 1'b1 1.92 + 1.93 +// Shift direction 1.94 +`define LM32_SHIFT_OP_RIGHT 1'b0 1.95 +`define LM32_SHIFT_OP_LEFT 1'b1 1.96 + 1.97 +// Currently always enabled 1.98 +`define CFG_BUS_ERRORS_ENABLED 1.99 + 1.100 +// Derive macro that indicates whether we have single-stepping or not 1.101 +`ifdef CFG_ROM_DEBUG_ENABLED 1.102 +`define LM32_SINGLE_STEP_ENABLED 1.103 +`else 1.104 +`ifdef CFG_HW_DEBUG_ENABLED 1.105 +`define LM32_SINGLE_STEP_ENABLED 1.106 +`endif 1.107 +`endif 1.108 + 1.109 +// Derive macro that indicates whether JTAG interface is required 1.110 +`ifdef CFG_JTAG_UART_ENABLED 1.111 +`define LM32_JTAG_ENABLED 1.112 +`else 1.113 +`ifdef CFG_DEBUG_ENABLED 1.114 +`define LM32_JTAG_ENABLED 1.115 +`else 1.116 +`endif 1.117 +`endif 1.118 + 1.119 +// Derive macro that indicates whether we have a barrel-shifter or not 1.120 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.121 +`define LM32_BARREL_SHIFT_ENABLED 1.122 +`else // CFG_PL_BARREL_SHIFT_ENABLED 1.123 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.124 +`define LM32_BARREL_SHIFT_ENABLED 1.125 +`else 1.126 +`define LM32_NO_BARREL_SHIFT 1.127 +`endif 1.128 +`endif // CFG_PL_BARREL_SHIFT_ENABLED 1.129 + 1.130 +// Derive macro that indicates whether we have a multiplier or not 1.131 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.132 +`define LM32_MULTIPLY_ENABLED 1.133 +`else 1.134 +`ifdef CFG_MC_MULTIPLY_ENABLED 1.135 +`define LM32_MULTIPLY_ENABLED 1.136 +`endif 1.137 +`endif 1.138 + 1.139 +// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required 1.140 +`ifdef CFG_MC_DIVIDE_ENABLED 1.141 +`define LM32_MC_ARITHMETIC_ENABLED 1.142 +`endif 1.143 +`ifdef CFG_MC_MULTIPLY_ENABLED 1.144 +`define LM32_MC_ARITHMETIC_ENABLED 1.145 +`endif 1.146 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.147 +`define LM32_MC_ARITHMETIC_ENABLED 1.148 +`endif 1.149 + 1.150 +// Derive macro that indicates if we are using an EBR register file 1.151 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.152 +`define LM32_EBR_REGISTER_FILE 1.153 +`endif 1.154 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 1.155 +`define LM32_EBR_REGISTER_FILE 1.156 +`endif 1.157 + 1.158 +// Revision number 1.159 +`define LM32_REVISION 6'h02 1.160 + 1.161 +// Logical operations - Function encoded directly in instruction 1.162 +`define LM32_LOGIC_OP_RNG 3:0 1.163 + 1.164 +// Conditions for conditional branches 1.165 +`define LM32_CONDITION_WIDTH 3 1.166 +`define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0 1.167 +`define LM32_CONDITION_E 3'b001 1.168 +`define LM32_CONDITION_G 3'b010 1.169 +`define LM32_CONDITION_GE 3'b011 1.170 +`define LM32_CONDITION_GEU 3'b100 1.171 +`define LM32_CONDITION_GU 3'b101 1.172 +`define LM32_CONDITION_NE 3'b111 1.173 +`define LM32_CONDITION_U1 3'b000 1.174 +`define LM32_CONDITION_U2 3'b110 1.175 + 1.176 +// Size of load or store instruction - Encoding corresponds to opcode 1.177 +`define LM32_SIZE_WIDTH 2 1.178 +`define LM32_SIZE_RNG 1:0 1.179 +`define LM32_SIZE_BYTE 2'b00 1.180 +`define LM32_SIZE_HWORD 2'b11 1.181 +`define LM32_SIZE_WORD 2'b10 1.182 +`define LM32_ADDRESS_LSBS_WIDTH 2 1.183 + 1.184 +// Width and range of a CSR index 1.185 +`ifdef CFG_DEBUG_ENABLED 1.186 +`define LM32_CSR_WIDTH 5 1.187 +`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 1.188 +`else 1.189 +`ifdef CFG_JTAG_ENABLED 1.190 +`define LM32_CSR_WIDTH 4 1.191 +`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 1.192 +`else 1.193 +`define LM32_CSR_WIDTH 3 1.194 +`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 1.195 +`endif 1.196 +`endif 1.197 + 1.198 +// CSR indices 1.199 +`define LM32_CSR_IE `LM32_CSR_WIDTH'h0 1.200 +`define LM32_CSR_IM `LM32_CSR_WIDTH'h1 1.201 +`define LM32_CSR_IP `LM32_CSR_WIDTH'h2 1.202 +`define LM32_CSR_ICC `LM32_CSR_WIDTH'h3 1.203 +`define LM32_CSR_DCC `LM32_CSR_WIDTH'h4 1.204 +`define LM32_CSR_CC `LM32_CSR_WIDTH'h5 1.205 +`define LM32_CSR_CFG `LM32_CSR_WIDTH'h6 1.206 +`define LM32_CSR_EBA `LM32_CSR_WIDTH'h7 1.207 +`ifdef CFG_DEBUG_ENABLED 1.208 +`define LM32_CSR_DC `LM32_CSR_WIDTH'h8 1.209 +`define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9 1.210 +`endif 1.211 +`define LM32_CSR_CFG2 `LM32_CSR_WIDTH'ha 1.212 +`ifdef CFG_JTAG_ENABLED 1.213 +`define LM32_CSR_JTX `LM32_CSR_WIDTH'he 1.214 +`define LM32_CSR_JRX `LM32_CSR_WIDTH'hf 1.215 +`endif 1.216 +`ifdef CFG_DEBUG_ENABLED 1.217 +`define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10 1.218 +`define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11 1.219 +`define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12 1.220 +`define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13 1.221 +`define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18 1.222 +`define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19 1.223 +`define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a 1.224 +`define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b 1.225 +`endif 1.226 + 1.227 +// Values for WPC CSR 1.228 +`define LM32_WPC_C_RNG 1:0 1.229 +`define LM32_WPC_C_DISABLED 2'b00 1.230 +`define LM32_WPC_C_READ 2'b01 1.231 +`define LM32_WPC_C_WRITE 2'b10 1.232 +`define LM32_WPC_C_READ_WRITE 2'b11 1.233 + 1.234 +// Exception IDs 1.235 +`define LM32_EID_WIDTH 3 1.236 +`define LM32_EID_RNG (`LM32_EID_WIDTH-1):0 1.237 +`define LM32_EID_RESET 3'h0 1.238 +`define LM32_EID_BREAKPOINT 3'd1 1.239 +`define LM32_EID_INST_BUS_ERROR 3'h2 1.240 +`define LM32_EID_WATCHPOINT 3'd3 1.241 +`define LM32_EID_DATA_BUS_ERROR 3'h4 1.242 +`define LM32_EID_DIVIDE_BY_ZERO 3'h5 1.243 +`define LM32_EID_INTERRUPT 3'h6 1.244 +`define LM32_EID_SCALL 3'h7 1.245 + 1.246 +// Pipeline result selection mux controls 1.247 + 1.248 +`define LM32_D_RESULT_SEL_0_RNG 0:0 1.249 +`define LM32_D_RESULT_SEL_0_REG_0 1'b0 1.250 +`define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1 1.251 + 1.252 +`define LM32_D_RESULT_SEL_1_RNG 1:0 1.253 +`define LM32_D_RESULT_SEL_1_ZERO 2'b00 1.254 +`define LM32_D_RESULT_SEL_1_REG_1 2'b01 1.255 +`define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10 1.256 + 1.257 +`define LM32_USER_OPCODE_WIDTH 11 1.258 +`define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0 1.259 + 1.260 +// Derive a macro to indicate if either of the caches are implemented 1.261 +`ifdef CFG_ICACHE_ENABLED 1.262 +`define LM32_CACHE_ENABLED 1.263 +`else 1.264 +`ifdef CFG_DCACHE_ENABLED 1.265 +`define LM32_CACHE_ENABLED 1.266 +`endif 1.267 +`endif 1.268 + 1.269 +///////////////////////////////////////////////////// 1.270 +// Interrupts 1.271 +///////////////////////////////////////////////////// 1.272 + 1.273 +// Always enable interrupts 1.274 +`define CFG_INTERRUPTS_ENABLED 1.275 + 1.276 +// Currently this is fixed to 32 and should not be changed 1.277 +`define CFG_INTERRUPTS 32 1.278 +`define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS 1.279 +`define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0 1.280 + 1.281 +///////////////////////////////////////////////////// 1.282 +// General 1.283 +///////////////////////////////////////////////////// 1.284 + 1.285 +// Sub-word range types 1.286 +`define LM32_BYTE_WIDTH 8 1.287 +`define LM32_BYTE_RNG 7:0 1.288 +`define LM32_HWORD_WIDTH 16 1.289 +`define LM32_HWORD_RNG 15:0 1.290 + 1.291 +// Word sub-byte indicies 1.292 +`define LM32_BYTE_0_RNG 7:0 1.293 +`define LM32_BYTE_1_RNG 15:8 1.294 +`define LM32_BYTE_2_RNG 23:16 1.295 +`define LM32_BYTE_3_RNG 31:24 1.296 + 1.297 +// Word sub-halfword indices 1.298 +`define LM32_HWORD_0_RNG 15:0 1.299 +`define LM32_HWORD_1_RNG 31:16 1.300 + 1.301 +// Use an asynchronous reset 1.302 +// To use a synchronous reset, define this macro as nothing 1.303 +`define CFG_RESET_SENSITIVITY 1.304 + 1.305 +// V.T. Srce 1.306 +`define SRCE 1.307 + 1.308 +// Whether to include context registers for debug exceptions 1.309 +// in addition to standard exception handling registers 1.310 +// Bizarre - Removing this increases LUT count! 1.311 +`define CFG_DEBUG_EXCEPTIONS_ENABLED 1.312 + 1.313 +// Wishbone defines 1.314 +// Refer to Wishbone System-on-Chip Interconnection Architecture 1.315 +// These should probably be moved to a Wishbone common file 1.316 + 1.317 +// Wishbone cycle types 1.318 +`define LM32_CTYPE_WIDTH 3 1.319 +`define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0 1.320 +`define LM32_CTYPE_CLASSIC 3'b000 1.321 +`define LM32_CTYPE_CONSTANT 3'b001 1.322 +`define LM32_CTYPE_INCREMENTING 3'b010 1.323 +`define LM32_CTYPE_END 3'b111 1.324 + 1.325 +// Wishbone burst types 1.326 +`define LM32_BTYPE_WIDTH 2 1.327 +`define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0 1.328 +`define LM32_BTYPE_LINEAR 2'b00 1.329 +`define LM32_BTYPE_4_BEAT 2'b01 1.330 +`define LM32_BTYPE_8_BEAT 2'b10 1.331 +`define LM32_BTYPE_16_BEAT 2'b11 1.332 + 1.333 +`endif