1.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_instruction_unit.v 1.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 +++ b/lm32_instruction_unit.v Sun Apr 04 20:40:03 2010 +0100 1.4 @@ -0,0 +1,841 @@ 1.5 +// ============================================================================= 1.6 +// COPYRIGHT NOTICE 1.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 +// ALL RIGHTS RESERVED 1.9 +// This confidential and proprietary software may be used only as authorised by 1.10 +// a licensing agreement from Lattice Semiconductor Corporation. 1.11 +// The entire notice above must be reproduced on all authorized copies and 1.12 +// copies may only be made to the extent permitted by a licensing agreement from 1.13 +// Lattice Semiconductor Corporation. 1.14 +// 1.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 +// U.S.A email: techsupport@latticesemi.com 1.19 +// =============================================================================/ 1.20 +// FILE DETAILS 1.21 +// Project : LatticeMico32 1.22 +// File : lm32_instruction_unit.v 1.23 +// Title : Instruction unit 1.24 +// Dependencies : lm32_include.v 1.25 +// Version : 6.1.17 1.26 +// : Initial Release 1.27 +// Version : 7.0SP2, 3.0 1.28 +// : No Change 1.29 +// Version : 3.1 1.30 +// : Support for static branch prediction is added. Fetching of 1.31 +// : instructions can also be altered by branches predicted in D 1.32 +// : stage of pipeline, and mispredicted branches in the X and M 1.33 +// : stages of the pipeline. 1.34 +// Version : 3.2 1.35 +// : EBRs use SYNC resets instead of ASYNC resets. 1.36 +// Version : 3.3 1.37 +// : Support for a non-cacheable Instruction Memory that has a 1.38 +// : single-cycle access latency. This memory can be accessed by 1.39 +// : data port of LM32 (so that debugger has access to it). 1.40 +// Version : 3.4 1.41 +// : No change 1.42 +// Version : 3.5 1.43 +// : Bug fix: Inline memory is correctly generated if it is not a 1.44 +// : power-of-two. 1.45 +// : Bug fix: Fixed a bug that caused LM32 (configured without 1.46 +// : instruction cache) to lock up in to an infinite loop due to a 1.47 +// : instruction bus error when EBA was set to instruction inline 1.48 +// : memory. 1.49 +// ============================================================================= 1.50 + 1.51 +`include "lm32_include.v" 1.52 + 1.53 +///////////////////////////////////////////////////// 1.54 +// Module interface 1.55 +///////////////////////////////////////////////////// 1.56 + 1.57 +module lm32_instruction_unit ( 1.58 + // ----- Inputs ------- 1.59 + clk_i, 1.60 + rst_i, 1.61 + // From pipeline 1.62 + stall_a, 1.63 + stall_f, 1.64 + stall_d, 1.65 + stall_x, 1.66 + stall_m, 1.67 + valid_f, 1.68 + valid_d, 1.69 + kill_f, 1.70 + branch_predict_taken_d, 1.71 + branch_predict_address_d, 1.72 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.73 + branch_taken_x, 1.74 + branch_target_x, 1.75 +`endif 1.76 + exception_m, 1.77 + branch_taken_m, 1.78 + branch_mispredict_taken_m, 1.79 + branch_target_m, 1.80 +`ifdef CFG_ICACHE_ENABLED 1.81 + iflush, 1.82 +`endif 1.83 +`ifdef CFG_DCACHE_ENABLED 1.84 + dcache_restart_request, 1.85 + dcache_refill_request, 1.86 + dcache_refilling, 1.87 +`endif 1.88 +`ifdef CFG_IROM_ENABLED 1.89 + irom_store_data_m, 1.90 + irom_address_xm, 1.91 + irom_we_xm, 1.92 +`endif 1.93 +`ifdef CFG_IWB_ENABLED 1.94 + // From Wishbone 1.95 + i_dat_i, 1.96 + i_ack_i, 1.97 + i_err_i, 1.98 + i_rty_i, 1.99 +`endif 1.100 +`ifdef CFG_HW_DEBUG_ENABLED 1.101 + jtag_read_enable, 1.102 + jtag_write_enable, 1.103 + jtag_write_data, 1.104 + jtag_address, 1.105 +`endif 1.106 + // ----- Outputs ------- 1.107 + // To pipeline 1.108 + pc_f, 1.109 + pc_d, 1.110 + pc_x, 1.111 + pc_m, 1.112 + pc_w, 1.113 +`ifdef CFG_ICACHE_ENABLED 1.114 + icache_stall_request, 1.115 + icache_restart_request, 1.116 + icache_refill_request, 1.117 + icache_refilling, 1.118 +`endif 1.119 +`ifdef CFG_IROM_ENABLED 1.120 + irom_data_m, 1.121 +`endif 1.122 +`ifdef CFG_IWB_ENABLED 1.123 + // To Wishbone 1.124 + i_dat_o, 1.125 + i_adr_o, 1.126 + i_cyc_o, 1.127 + i_sel_o, 1.128 + i_stb_o, 1.129 + i_we_o, 1.130 + i_cti_o, 1.131 + i_lock_o, 1.132 + i_bte_o, 1.133 +`endif 1.134 +`ifdef CFG_HW_DEBUG_ENABLED 1.135 + jtag_read_data, 1.136 + jtag_access_complete, 1.137 +`endif 1.138 +`ifdef CFG_BUS_ERRORS_ENABLED 1.139 + bus_error_d, 1.140 +`endif 1.141 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.142 + instruction_f, 1.143 +`endif 1.144 + instruction_d 1.145 + ); 1.146 + 1.147 +///////////////////////////////////////////////////// 1.148 +// Parameters 1.149 +///////////////////////////////////////////////////// 1.150 + 1.151 +parameter associativity = 1; // Associativity of the cache (Number of ways) 1.152 +parameter sets = 512; // Number of sets 1.153 +parameter bytes_per_line = 16; // Number of bytes per cache line 1.154 +parameter base_address = 0; // Base address of cachable memory 1.155 +parameter limit = 0; // Limit (highest address) of cachable memory 1.156 + 1.157 +// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 1.158 +localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2; 1.159 +localparam addr_offset_lsb = 2; 1.160 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 1.161 + 1.162 +///////////////////////////////////////////////////// 1.163 +// Inputs 1.164 +///////////////////////////////////////////////////// 1.165 + 1.166 +input clk_i; // Clock 1.167 +input rst_i; // Reset 1.168 + 1.169 +input stall_a; // Stall A stage instruction 1.170 +input stall_f; // Stall F stage instruction 1.171 +input stall_d; // Stall D stage instruction 1.172 +input stall_x; // Stall X stage instruction 1.173 +input stall_m; // Stall M stage instruction 1.174 +input valid_f; // Instruction in F stage is valid 1.175 +input valid_d; // Instruction in D stage is valid 1.176 +input kill_f; // Kill instruction in F stage 1.177 + 1.178 +input branch_predict_taken_d; // Branch is predicted taken in D stage 1.179 +input [`LM32_PC_RNG] branch_predict_address_d; // Branch target address 1.180 + 1.181 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.182 +input branch_taken_x; // Branch instruction in X stage is taken 1.183 +input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction 1.184 +`endif 1.185 +input exception_m; 1.186 +input branch_taken_m; // Branch instruction in M stage is taken 1.187 +input branch_mispredict_taken_m; // Branch instruction in M stage is mispredicted as taken 1.188 +input [`LM32_PC_RNG] branch_target_m; // Target PC of M stage branch instruction 1.189 + 1.190 +`ifdef CFG_ICACHE_ENABLED 1.191 +input iflush; // Flush instruction cache 1.192 +`endif 1.193 +`ifdef CFG_DCACHE_ENABLED 1.194 +input dcache_restart_request; // Restart instruction that caused a data cache miss 1.195 +input dcache_refill_request; // Request to refill data cache 1.196 +input dcache_refilling; 1.197 +`endif 1.198 + 1.199 +`ifdef CFG_IROM_ENABLED 1.200 +input [`LM32_WORD_RNG] irom_store_data_m; // Data from load-store unit 1.201 +input [`LM32_WORD_RNG] irom_address_xm; // Address from load-store unit 1.202 +input irom_we_xm; // Indicates if memory operation is load or store 1.203 +`endif 1.204 + 1.205 +`ifdef CFG_IWB_ENABLED 1.206 +input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data 1.207 +input i_ack_i; // Instruction Wishbone interface acknowledgement 1.208 +input i_err_i; // Instruction Wishbone interface error 1.209 +input i_rty_i; // Instruction Wishbone interface retry 1.210 +`endif 1.211 + 1.212 +`ifdef CFG_HW_DEBUG_ENABLED 1.213 +input jtag_read_enable; // JTAG read memory request 1.214 +input jtag_write_enable; // JTAG write memory request 1.215 +input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data 1.216 +input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address 1.217 +`endif 1.218 + 1.219 +///////////////////////////////////////////////////// 1.220 +// Outputs 1.221 +///////////////////////////////////////////////////// 1.222 + 1.223 +output [`LM32_PC_RNG] pc_f; // F stage PC 1.224 +reg [`LM32_PC_RNG] pc_f; 1.225 +output [`LM32_PC_RNG] pc_d; // D stage PC 1.226 +reg [`LM32_PC_RNG] pc_d; 1.227 +output [`LM32_PC_RNG] pc_x; // X stage PC 1.228 +reg [`LM32_PC_RNG] pc_x; 1.229 +output [`LM32_PC_RNG] pc_m; // M stage PC 1.230 +reg [`LM32_PC_RNG] pc_m; 1.231 +output [`LM32_PC_RNG] pc_w; // W stage PC 1.232 +reg [`LM32_PC_RNG] pc_w; 1.233 + 1.234 +`ifdef CFG_ICACHE_ENABLED 1.235 +output icache_stall_request; // Instruction cache stall request 1.236 +wire icache_stall_request; 1.237 +output icache_restart_request; // Request to restart instruction that cached instruction cache miss 1.238 +wire icache_restart_request; 1.239 +output icache_refill_request; // Instruction cache refill request 1.240 +wire icache_refill_request; 1.241 +output icache_refilling; // Indicates the icache is refilling 1.242 +wire icache_refilling; 1.243 +`endif 1.244 + 1.245 +`ifdef CFG_IROM_ENABLED 1.246 +output [`LM32_WORD_RNG] irom_data_m; // Data to load-store unit on load 1.247 +wire [`LM32_WORD_RNG] irom_data_m; 1.248 +`endif 1.249 + 1.250 +`ifdef CFG_IWB_ENABLED 1.251 +output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data 1.252 +`ifdef CFG_HW_DEBUG_ENABLED 1.253 +reg [`LM32_WORD_RNG] i_dat_o; 1.254 +`else 1.255 +wire [`LM32_WORD_RNG] i_dat_o; 1.256 +`endif 1.257 +output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address 1.258 +reg [`LM32_WORD_RNG] i_adr_o; 1.259 +output i_cyc_o; // Instruction Wishbone interface cycle 1.260 +reg i_cyc_o; 1.261 +output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select 1.262 +`ifdef CFG_HW_DEBUG_ENABLED 1.263 +reg [`LM32_BYTE_SELECT_RNG] i_sel_o; 1.264 +`else 1.265 +wire [`LM32_BYTE_SELECT_RNG] i_sel_o; 1.266 +`endif 1.267 +output i_stb_o; // Instruction Wishbone interface strobe 1.268 +reg i_stb_o; 1.269 +output i_we_o; // Instruction Wishbone interface write enable 1.270 +`ifdef CFG_HW_DEBUG_ENABLED 1.271 +reg i_we_o; 1.272 +`else 1.273 +wire i_we_o; 1.274 +`endif 1.275 +output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type 1.276 +reg [`LM32_CTYPE_RNG] i_cti_o; 1.277 +output i_lock_o; // Instruction Wishbone interface lock bus 1.278 +reg i_lock_o; 1.279 +output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type 1.280 +wire [`LM32_BTYPE_RNG] i_bte_o; 1.281 +`endif 1.282 + 1.283 +`ifdef CFG_HW_DEBUG_ENABLED 1.284 +output [`LM32_BYTE_RNG] jtag_read_data; // Data read for JTAG interface 1.285 +reg [`LM32_BYTE_RNG] jtag_read_data; 1.286 +output jtag_access_complete; // Requested memory access by JTAG interface is complete 1.287 +wire jtag_access_complete; 1.288 +`endif 1.289 + 1.290 +`ifdef CFG_BUS_ERRORS_ENABLED 1.291 +output bus_error_d; // Indicates a bus error occured while fetching the instruction 1.292 +reg bus_error_d; 1.293 +`endif 1.294 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.295 +output [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction (only to have register indices extracted from) 1.296 +wire [`LM32_INSTRUCTION_RNG] instruction_f; 1.297 +`endif 1.298 +output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded 1.299 +reg [`LM32_INSTRUCTION_RNG] instruction_d; 1.300 + 1.301 +///////////////////////////////////////////////////// 1.302 +// Internal nets and registers 1.303 +///////////////////////////////////////////////////// 1.304 + 1.305 +reg [`LM32_PC_RNG] pc_a; // A stage PC 1.306 + 1.307 +`ifdef LM32_CACHE_ENABLED 1.308 +reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss 1.309 +`endif 1.310 + 1.311 +`ifdef CFG_ICACHE_ENABLED 1.312 +wire icache_read_enable_f; // Indicates if instruction cache miss is valid 1.313 +wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss 1.314 +reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache 1.315 +reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone 1.316 +wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache 1.317 +wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type 1.318 +wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type 1.319 +wire last_word; // Indicates if this is the last word in the cache line 1.320 +wire [`LM32_PC_RNG] first_address; // First cache refill address 1.321 +`else 1.322 +`ifdef CFG_IWB_ENABLED 1.323 +reg [`LM32_INSTRUCTION_RNG] wb_data_f; // Instruction fetched from Wishbone 1.324 +`endif 1.325 +`endif 1.326 +`ifdef CFG_IROM_ENABLED 1.327 +wire irom_select_a; // Indicates if A stage PC maps to a ROM address 1.328 +reg irom_select_f; // Indicates if F stage PC maps to a ROM address 1.329 +wire [`LM32_INSTRUCTION_RNG] irom_data_f; // Instruction fetched from ROM 1.330 +`endif 1.331 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.332 +`else 1.333 +wire [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction 1.334 +`endif 1.335 +`ifdef CFG_BUS_ERRORS_ENABLED 1.336 +reg bus_error_f; // Indicates if a bus error occured while fetching the instruction in the F stage 1.337 +`endif 1.338 + 1.339 +`ifdef CFG_HW_DEBUG_ENABLED 1.340 +reg jtag_access; // Indicates if a JTAG WB access is in progress 1.341 +`endif 1.342 + 1.343 +///////////////////////////////////////////////////// 1.344 +// Functions 1.345 +///////////////////////////////////////////////////// 1.346 + 1.347 +`include "lm32_functions.v" 1.348 + 1.349 +///////////////////////////////////////////////////// 1.350 +// Instantiations 1.351 +///////////////////////////////////////////////////// 1.352 + 1.353 +// Instruction ROM 1.354 +`ifdef CFG_IROM_ENABLED 1.355 + pmi_ram_dp_true 1.356 + #( 1.357 + // ----- Parameters ------- 1.358 + .pmi_family (`LATTICE_FAMILY), 1.359 + 1.360 + //.pmi_addr_depth_a (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 1.361 + //.pmi_addr_width_a ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 1.362 + //.pmi_data_width_a (`LM32_WORD_WIDTH), 1.363 + //.pmi_addr_depth_b (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 1.364 + //.pmi_addr_width_b ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 1.365 + //.pmi_data_width_b (`LM32_WORD_WIDTH), 1.366 + 1.367 + .pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1), 1.368 + .pmi_addr_width_a (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), 1.369 + .pmi_data_width_a (`LM32_WORD_WIDTH), 1.370 + .pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1), 1.371 + .pmi_addr_width_b (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), 1.372 + .pmi_data_width_b (`LM32_WORD_WIDTH), 1.373 + 1.374 + .pmi_regmode_a ("noreg"), 1.375 + .pmi_regmode_b ("noreg"), 1.376 + .pmi_gsr ("enable"), 1.377 + .pmi_resetmode ("sync"), 1.378 + .pmi_init_file (`CFG_IROM_INIT_FILE), 1.379 + .pmi_init_file_format (`CFG_IROM_INIT_FILE_FORMAT), 1.380 + .module_type ("pmi_ram_dp_true") 1.381 + ) 1.382 + ram ( 1.383 + // ----- Inputs ------- 1.384 + .ClockA (clk_i), 1.385 + .ClockB (clk_i), 1.386 + .ResetA (rst_i), 1.387 + .ResetB (rst_i), 1.388 + .DataInA ({32{1'b0}}), 1.389 + .DataInB (irom_store_data_m), 1.390 + .AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.391 + .AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.392 + .ClockEnA (!stall_a), 1.393 + .ClockEnB (!stall_x || !stall_m), 1.394 + .WrA (`FALSE), 1.395 + .WrB (irom_we_xm), 1.396 + // ----- Outputs ------- 1.397 + .QA (irom_data_f), 1.398 + .QB (irom_data_m) 1.399 + ); 1.400 +`endif 1.401 + 1.402 +`ifdef CFG_ICACHE_ENABLED 1.403 +// Instruction cache 1.404 +lm32_icache #( 1.405 + .associativity (associativity), 1.406 + .sets (sets), 1.407 + .bytes_per_line (bytes_per_line), 1.408 + .base_address (base_address), 1.409 + .limit (limit) 1.410 + ) icache ( 1.411 + // ----- Inputs ----- 1.412 + .clk_i (clk_i), 1.413 + .rst_i (rst_i), 1.414 + .stall_a (stall_a), 1.415 + .stall_f (stall_f), 1.416 + .branch_predict_taken_d (branch_predict_taken_d), 1.417 + .valid_d (valid_d), 1.418 + .address_a (pc_a), 1.419 + .address_f (pc_f), 1.420 + .read_enable_f (icache_read_enable_f), 1.421 + .refill_ready (icache_refill_ready), 1.422 + .refill_data (icache_refill_data), 1.423 + .iflush (iflush), 1.424 + // ----- Outputs ----- 1.425 + .stall_request (icache_stall_request), 1.426 + .restart_request (icache_restart_request), 1.427 + .refill_request (icache_refill_request), 1.428 + .refill_address (icache_refill_address), 1.429 + .refilling (icache_refilling), 1.430 + .inst (icache_data_f) 1.431 + ); 1.432 +`endif 1.433 + 1.434 +///////////////////////////////////////////////////// 1.435 +// Combinational Logic 1.436 +///////////////////////////////////////////////////// 1.437 + 1.438 +`ifdef CFG_ICACHE_ENABLED 1.439 +// Generate signal that indicates when instruction cache misses are valid 1.440 +assign icache_read_enable_f = (valid_f == `TRUE) 1.441 + && (kill_f == `FALSE) 1.442 +`ifdef CFG_DCACHE_ENABLED 1.443 + && (dcache_restart_request == `FALSE) 1.444 +`endif 1.445 +`ifdef CFG_IROM_ENABLED 1.446 + && (irom_select_f == `FALSE) 1.447 +`endif 1.448 + ; 1.449 +`endif 1.450 + 1.451 +// Compute address of next instruction to fetch 1.452 +always @(*) 1.453 +begin 1.454 + // The request from the latest pipeline stage must take priority 1.455 +`ifdef CFG_DCACHE_ENABLED 1.456 + if (dcache_restart_request == `TRUE) 1.457 + pc_a = restart_address; 1.458 + else 1.459 +`endif 1.460 + if (branch_taken_m == `TRUE) 1.461 + if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE)) 1.462 + pc_a = pc_x; 1.463 + else 1.464 + pc_a = branch_target_m; 1.465 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.466 + else if (branch_taken_x == `TRUE) 1.467 + pc_a = branch_target_x; 1.468 +`endif 1.469 + else 1.470 + if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) ) 1.471 + pc_a = branch_predict_address_d; 1.472 + else 1.473 +`ifdef CFG_ICACHE_ENABLED 1.474 + if (icache_restart_request == `TRUE) 1.475 + pc_a = restart_address; 1.476 + else 1.477 +`endif 1.478 + pc_a = pc_f + 1'b1; 1.479 +end 1.480 + 1.481 +// Select where instruction should be fetched from 1.482 +`ifdef CFG_IROM_ENABLED 1.483 +assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT); 1.484 +`endif 1.485 + 1.486 +// Select instruction from selected source 1.487 +`ifdef CFG_ICACHE_ENABLED 1.488 +`ifdef CFG_IROM_ENABLED 1.489 +assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f; 1.490 +`else 1.491 +assign instruction_f = icache_data_f; 1.492 +`endif 1.493 +`else 1.494 +`ifdef CFG_IROM_ENABLED 1.495 +`ifdef CFG_IWB_ENABLED 1.496 +assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f; 1.497 +`else 1.498 +assign instruction_f = irom_data_f; 1.499 +`endif 1.500 +`else 1.501 +assign instruction_f = wb_data_f; 1.502 +`endif 1.503 +`endif 1.504 + 1.505 +// Unused/constant Wishbone signals 1.506 +`ifdef CFG_IWB_ENABLED 1.507 +`ifdef CFG_HW_DEBUG_ENABLED 1.508 +`else 1.509 +assign i_dat_o = 32'd0; 1.510 +assign i_we_o = `FALSE; 1.511 +assign i_sel_o = 4'b1111; 1.512 +`endif 1.513 +assign i_bte_o = `LM32_BTYPE_LINEAR; 1.514 +`endif 1.515 + 1.516 +`ifdef CFG_ICACHE_ENABLED 1.517 +// Determine parameters for next cache refill Wishbone access 1.518 +generate 1.519 + case (bytes_per_line) 1.520 + 4: 1.521 + begin 1.522 +assign first_cycle_type = `LM32_CTYPE_END; 1.523 +assign next_cycle_type = `LM32_CTYPE_END; 1.524 +assign last_word = `TRUE; 1.525 +assign first_address = icache_refill_address; 1.526 + end 1.527 + 8: 1.528 + begin 1.529 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 1.530 +assign next_cycle_type = `LM32_CTYPE_END; 1.531 +assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1; 1.532 +assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; 1.533 + end 1.534 + 16: 1.535 + begin 1.536 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 1.537 +assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING; 1.538 +assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11; 1.539 +assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; 1.540 + end 1.541 + endcase 1.542 +endgenerate 1.543 +`endif 1.544 + 1.545 +///////////////////////////////////////////////////// 1.546 +// Sequential Logic 1.547 +///////////////////////////////////////////////////// 1.548 + 1.549 +// PC 1.550 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.551 +begin 1.552 + if (rst_i == `TRUE) 1.553 + begin 1.554 + pc_f <= (`CFG_EBA_RESET-4)/4; 1.555 + pc_d <= {`LM32_PC_WIDTH{1'b0}}; 1.556 + pc_x <= {`LM32_PC_WIDTH{1'b0}}; 1.557 + pc_m <= {`LM32_PC_WIDTH{1'b0}}; 1.558 + pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.559 + end 1.560 + else 1.561 + begin 1.562 + if (stall_f == `FALSE) 1.563 + pc_f <= pc_a; 1.564 + if (stall_d == `FALSE) 1.565 + pc_d <= pc_f; 1.566 + if (stall_x == `FALSE) 1.567 + pc_x <= pc_d; 1.568 + if (stall_m == `FALSE) 1.569 + pc_m <= pc_x; 1.570 + pc_w <= pc_m; 1.571 + end 1.572 +end 1.573 + 1.574 +`ifdef LM32_CACHE_ENABLED 1.575 +// Address to restart from after a cache miss has been handled 1.576 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.577 +begin 1.578 + if (rst_i == `TRUE) 1.579 + restart_address <= {`LM32_PC_WIDTH{1'b0}}; 1.580 + else 1.581 + begin 1.582 +`ifdef CFG_DCACHE_ENABLED 1.583 +`ifdef CFG_ICACHE_ENABLED 1.584 + // D-cache restart address must take priority, otherwise instructions will be lost 1.585 + if (dcache_refill_request == `TRUE) 1.586 + restart_address <= pc_w; 1.587 + else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request)) 1.588 + restart_address <= icache_refill_address; 1.589 +`else 1.590 + if (dcache_refill_request == `TRUE) 1.591 + restart_address <= pc_w; 1.592 +`endif 1.593 +`else 1.594 +`ifdef CFG_ICACHE_ENABLED 1.595 + if (icache_refill_request == `TRUE) 1.596 + restart_address <= icache_refill_address; 1.597 +`endif 1.598 +`endif 1.599 + end 1.600 +end 1.601 +`endif 1.602 + 1.603 +// Record where instruction was fetched from 1.604 +`ifdef CFG_IROM_ENABLED 1.605 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.606 +begin 1.607 + if (rst_i == `TRUE) 1.608 + irom_select_f <= `FALSE; 1.609 + else 1.610 + begin 1.611 + if (stall_f == `FALSE) 1.612 + irom_select_f <= irom_select_a; 1.613 + end 1.614 +end 1.615 +`endif 1.616 + 1.617 +`ifdef CFG_HW_DEBUG_ENABLED 1.618 +assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE); 1.619 +always @(*) 1.620 +begin 1.621 + case (jtag_address[1:0]) 1.622 + 2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG]; 1.623 + 2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG]; 1.624 + 2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG]; 1.625 + 2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG]; 1.626 + endcase 1.627 +end 1.628 +`endif 1.629 + 1.630 +`ifdef CFG_IWB_ENABLED 1.631 +// Instruction Wishbone interface 1.632 +`ifdef CFG_ICACHE_ENABLED 1.633 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.634 +begin 1.635 + if (rst_i == `TRUE) 1.636 + begin 1.637 + i_cyc_o <= `FALSE; 1.638 + i_stb_o <= `FALSE; 1.639 + i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 1.640 + i_cti_o <= `LM32_CTYPE_END; 1.641 + i_lock_o <= `FALSE; 1.642 + icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.643 + icache_refill_ready <= `FALSE; 1.644 +`ifdef CFG_BUS_ERRORS_ENABLED 1.645 + bus_error_f <= `FALSE; 1.646 +`endif 1.647 +`ifdef CFG_HW_DEBUG_ENABLED 1.648 + i_we_o <= `FALSE; 1.649 + i_sel_o <= 4'b1111; 1.650 + jtag_access <= `FALSE; 1.651 +`endif 1.652 + end 1.653 + else 1.654 + begin 1.655 + icache_refill_ready <= `FALSE; 1.656 + // Is a cycle in progress? 1.657 + if (i_cyc_o == `TRUE) 1.658 + begin 1.659 + // Has cycle completed? 1.660 + if ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 1.661 + begin 1.662 +`ifdef CFG_HW_DEBUG_ENABLED 1.663 + if (jtag_access == `TRUE) 1.664 + begin 1.665 + i_cyc_o <= `FALSE; 1.666 + i_stb_o <= `FALSE; 1.667 + i_we_o <= `FALSE; 1.668 + jtag_access <= `FALSE; 1.669 + end 1.670 + else 1.671 +`endif 1.672 + begin 1.673 + if (last_word == `TRUE) 1.674 + begin 1.675 + // Cache line fill complete 1.676 + i_cyc_o <= `FALSE; 1.677 + i_stb_o <= `FALSE; 1.678 + i_lock_o <= `FALSE; 1.679 + end 1.680 + // Fetch next word in cache line 1.681 + i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 1.682 + i_cti_o <= next_cycle_type; 1.683 + // Write fetched data into instruction cache 1.684 + icache_refill_ready <= `TRUE; 1.685 + icache_refill_data <= i_dat_i; 1.686 + end 1.687 + end 1.688 +`ifdef CFG_BUS_ERRORS_ENABLED 1.689 + if (i_err_i == `TRUE) 1.690 + begin 1.691 + bus_error_f <= `TRUE; 1.692 + $display ("Instruction bus error. Address: %x", i_adr_o); 1.693 + end 1.694 +`endif 1.695 + end 1.696 + else 1.697 + begin 1.698 + if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE)) 1.699 + begin 1.700 + // Read first word of cache line 1.701 +`ifdef CFG_HW_DEBUG_ENABLED 1.702 + i_sel_o <= 4'b1111; 1.703 +`endif 1.704 + i_adr_o <= {first_address, 2'b00}; 1.705 + i_cyc_o <= `TRUE; 1.706 + i_stb_o <= `TRUE; 1.707 + i_cti_o <= first_cycle_type; 1.708 + //i_lock_o <= `TRUE; 1.709 +`ifdef CFG_BUS_ERRORS_ENABLED 1.710 + bus_error_f <= `FALSE; 1.711 +`endif 1.712 + end 1.713 +`ifdef CFG_HW_DEBUG_ENABLED 1.714 + else 1.715 + begin 1.716 + if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE)) 1.717 + begin 1.718 + case (jtag_address[1:0]) 1.719 + 2'b00: i_sel_o <= 4'b1000; 1.720 + 2'b01: i_sel_o <= 4'b0100; 1.721 + 2'b10: i_sel_o <= 4'b0010; 1.722 + 2'b11: i_sel_o <= 4'b0001; 1.723 + endcase 1.724 + i_adr_o <= jtag_address; 1.725 + i_dat_o <= {4{jtag_write_data}}; 1.726 + i_cyc_o <= `TRUE; 1.727 + i_stb_o <= `TRUE; 1.728 + i_we_o <= jtag_write_enable; 1.729 + i_cti_o <= `LM32_CTYPE_END; 1.730 + jtag_access <= `TRUE; 1.731 + end 1.732 + end 1.733 +`endif 1.734 +`ifdef CFG_BUS_ERRORS_ENABLED 1.735 + // Clear bus error when exception taken, otherwise they would be 1.736 + // continually generated if exception handler is cached 1.737 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.738 + if (branch_taken_x == `TRUE) 1.739 + bus_error_f <= `FALSE; 1.740 +`endif 1.741 + if (branch_taken_m == `TRUE) 1.742 + bus_error_f <= `FALSE; 1.743 +`endif 1.744 + end 1.745 + end 1.746 +end 1.747 +`else 1.748 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.749 +begin 1.750 + if (rst_i == `TRUE) 1.751 + begin 1.752 + i_cyc_o <= `FALSE; 1.753 + i_stb_o <= `FALSE; 1.754 + i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 1.755 + i_cti_o <= `LM32_CTYPE_END; 1.756 + i_lock_o <= `FALSE; 1.757 + wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.758 +`ifdef CFG_BUS_ERRORS_ENABLED 1.759 + bus_error_f <= `FALSE; 1.760 +`endif 1.761 + end 1.762 + else 1.763 + begin 1.764 + // Is a cycle in progress? 1.765 + if (i_cyc_o == `TRUE) 1.766 + begin 1.767 + // Has cycle completed? 1.768 + if((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 1.769 + begin 1.770 + // Cycle complete 1.771 + i_cyc_o <= `FALSE; 1.772 + i_stb_o <= `FALSE; 1.773 + // Register fetched instruction 1.774 + wb_data_f <= i_dat_i; 1.775 + end 1.776 +`ifdef CFG_BUS_ERRORS_ENABLED 1.777 + if (i_err_i == `TRUE) 1.778 + begin 1.779 + bus_error_f <= `TRUE; 1.780 + $display ("Instruction bus error. Address: %x", i_adr_o); 1.781 + end 1.782 +`endif 1.783 + end 1.784 + else 1.785 + begin 1.786 + // Wait for an instruction fetch from an external address 1.787 + if ( (stall_a == `FALSE) 1.788 +`ifdef CFG_IROM_ENABLED 1.789 + && (irom_select_a == `FALSE) 1.790 +`endif 1.791 + ) 1.792 + begin 1.793 + // Fetch instruction 1.794 +`ifdef CFG_HW_DEBUG_ENABLED 1.795 + i_sel_o <= 4'b1111; 1.796 +`endif 1.797 + i_adr_o <= {pc_a, 2'b00}; 1.798 + i_cyc_o <= `TRUE; 1.799 + i_stb_o <= `TRUE; 1.800 +`ifdef CFG_BUS_ERRORS_ENABLED 1.801 + bus_error_f <= `FALSE; 1.802 +`endif 1.803 + end 1.804 + else 1.805 + begin 1.806 + if ( (stall_a == `FALSE) 1.807 +`ifdef CFG_IROM_ENABLED 1.808 + && (irom_select_a == `TRUE) 1.809 +`endif 1.810 + ) 1.811 + begin 1.812 +`ifdef CFG_BUS_ERRORS_ENABLED 1.813 + bus_error_f <= `FALSE; 1.814 +`endif 1.815 + end 1.816 + end 1.817 + end 1.818 + end 1.819 +end 1.820 +`endif 1.821 +`endif 1.822 + 1.823 +// Instruction register 1.824 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.825 +begin 1.826 + if (rst_i == `TRUE) 1.827 + begin 1.828 + instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.829 +`ifdef CFG_BUS_ERRORS_ENABLED 1.830 + bus_error_d <= `FALSE; 1.831 +`endif 1.832 + end 1.833 + else 1.834 + begin 1.835 + if (stall_d == `FALSE) 1.836 + begin 1.837 + instruction_d <= instruction_f; 1.838 +`ifdef CFG_BUS_ERRORS_ENABLED 1.839 + bus_error_d <= bus_error_f; 1.840 +`endif 1.841 + end 1.842 + end 1.843 +end 1.844 + 1.845 +endmodule