1.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_monitor.v 1.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 +++ b/lm32_monitor.v Sun Apr 04 20:40:03 2010 +0100 1.4 @@ -0,0 +1,173 @@ 1.5 +// ============================================================================= 1.6 +// COPYRIGHT NOTICE 1.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 +// ALL RIGHTS RESERVED 1.9 +// This confidential and proprietary software may be used only as authorised by 1.10 +// a licensing agreement from Lattice Semiconductor Corporation. 1.11 +// The entire notice above must be reproduced on all authorized copies and 1.12 +// copies may only be made to the extent permitted by a licensing agreement from 1.13 +// Lattice Semiconductor Corporation. 1.14 +// 1.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 +// U.S.A email: techsupport@latticesemi.com 1.19 +// =============================================================================/ 1.20 +// FILE DETAILS 1.21 +// Project : LatticeMico32 1.22 +// File : lm32_monitor.v 1.23 +// Title : Debug monitor memory Wishbone interface 1.24 +// Version : 6.1.17 1.25 +// : Initial Release 1.26 +// Version : 7.0SP2, 3.0 1.27 +// : No Change 1.28 +// Version : 3.3 1.29 +// : Removed port mismatch in instantiation of module 1.30 +// : lm32_monitor_ram. 1.31 +// ============================================================================= 1.32 + 1.33 +`include "system_conf.v" 1.34 +`include "lm32_include.v" 1.35 + 1.36 +///////////////////////////////////////////////////// 1.37 +// Module interface 1.38 +///////////////////////////////////////////////////// 1.39 + 1.40 +module lm32_monitor ( 1.41 + // ----- Inputs ------- 1.42 + clk_i, 1.43 + rst_i, 1.44 + MON_ADR_I, 1.45 + MON_CYC_I, 1.46 + MON_DAT_I, 1.47 + MON_SEL_I, 1.48 + MON_STB_I, 1.49 + MON_WE_I, 1.50 + MON_LOCK_I, 1.51 + MON_CTI_I, 1.52 + MON_BTE_I, 1.53 + // ----- Outputs ------- 1.54 + MON_ACK_O, 1.55 + MON_RTY_O, 1.56 + MON_DAT_O, 1.57 + MON_ERR_O 1.58 + ); 1.59 + 1.60 +///////////////////////////////////////////////////// 1.61 +// Inputs 1.62 +///////////////////////////////////////////////////// 1.63 + 1.64 +input clk_i; // Wishbone clock 1.65 +input rst_i; // Wishbone reset 1.66 +input [`LM32_WORD_RNG] MON_ADR_I; // Wishbone address 1.67 +input MON_STB_I; // Wishbone strobe 1.68 +input MON_CYC_I; // Wishbone cycle 1.69 +input [`LM32_WORD_RNG] MON_DAT_I; // Wishbone write data 1.70 +input [`LM32_BYTE_SELECT_RNG] MON_SEL_I; // Wishbone byte select 1.71 +input MON_WE_I; // Wishbone write enable 1.72 +input MON_LOCK_I; // Wishbone locked transfer 1.73 +input [`LM32_CTYPE_RNG] MON_CTI_I; // Wishbone cycle type 1.74 +input [`LM32_BTYPE_RNG] MON_BTE_I; // Wishbone burst type 1.75 + 1.76 +///////////////////////////////////////////////////// 1.77 +// Outputs 1.78 +///////////////////////////////////////////////////// 1.79 + 1.80 +output MON_ACK_O; // Wishbone acknowlege 1.81 +reg MON_ACK_O; 1.82 +output [`LM32_WORD_RNG] MON_DAT_O; // Wishbone data output 1.83 +reg [`LM32_WORD_RNG] MON_DAT_O; 1.84 +output MON_RTY_O; // Wishbone retry 1.85 +wire MON_RTY_O; 1.86 +output MON_ERR_O; // Wishbone error 1.87 +wire MON_ERR_O; 1.88 + 1.89 +///////////////////////////////////////////////////// 1.90 +// Internal nets and registers 1.91 +///////////////////////////////////////////////////// 1.92 + 1.93 +reg [1:0] state; // Current state of FSM 1.94 +wire [`LM32_WORD_RNG] data, dataB; // Data read from RAM 1.95 +reg write_enable; // RAM write enable 1.96 +reg [`LM32_WORD_RNG] write_data; // RAM write data 1.97 + 1.98 +///////////////////////////////////////////////////// 1.99 +// Instantiations 1.100 +///////////////////////////////////////////////////// 1.101 + 1.102 +lm32_monitor_ram ram ( 1.103 + // ----- Inputs ------- 1.104 + .ClockA (clk_i), 1.105 + .ClockB (clk_i), 1.106 + .ResetA (rst_i), 1.107 + .ResetB (rst_i), 1.108 + .ClockEnA (`TRUE), 1.109 + .ClockEnB (`FALSE), 1.110 + .AddressA (MON_ADR_I[10:2]), 1.111 + .AddressB (9'b0), 1.112 + .DataInA (write_data), 1.113 + .DataInB (32'b0), 1.114 + .WrA (write_enable), 1.115 + .WrB (`FALSE), 1.116 + // ----- Outputs ------- 1.117 + .QA (data), 1.118 + .QB (dataB) 1.119 + ); 1.120 + 1.121 +///////////////////////////////////////////////////// 1.122 +// Combinational Logic 1.123 +///////////////////////////////////////////////////// 1.124 + 1.125 +assign MON_RTY_O = `FALSE; 1.126 +assign MON_ERR_O = `FALSE; 1.127 + 1.128 +///////////////////////////////////////////////////// 1.129 +// Sequential Logic 1.130 +///////////////////////////////////////////////////// 1.131 + 1.132 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.133 +begin 1.134 + if (rst_i == `TRUE) 1.135 + begin 1.136 + write_enable <= `FALSE; 1.137 + MON_ACK_O <= `FALSE; 1.138 + MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 1.139 + state <= 2'b00; 1.140 + end 1.141 + else 1.142 + begin 1.143 + case (state) 1.144 + 2'b00: 1.145 + begin 1.146 + // Wait for a Wishbone access 1.147 + if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE)) 1.148 + state <= 2'b01; 1.149 + end 1.150 + 2'b01: 1.151 + begin 1.152 + // Output read data to Wishbone 1.153 + MON_ACK_O <= `TRUE; 1.154 + MON_DAT_O <= data; 1.155 + // Sub-word writes are performed using read-modify-write 1.156 + // as the Lattice EBRs don't support byte enables 1.157 + if (MON_WE_I == `TRUE) 1.158 + write_enable <= `TRUE; 1.159 + write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0]; 1.160 + write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8]; 1.161 + write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16]; 1.162 + write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24]; 1.163 + state <= 2'b10; 1.164 + end 1.165 + 2'b10: 1.166 + begin 1.167 + // Wishbone access occurs in this cycle 1.168 + write_enable <= `FALSE; 1.169 + MON_ACK_O <= `FALSE; 1.170 + MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 1.171 + state <= 2'b00; 1.172 + end 1.173 + endcase 1.174 + end 1.175 +end 1.176 + 1.177 +endmodule