1.1 diff -r 000000000000 -r cd0b58aa6f83 spiprog.v 1.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 +++ b/spiprog.v Sun Apr 04 20:40:03 2010 +0100 1.4 @@ -0,0 +1,193 @@ 1.5 +// ============================================================================= 1.6 +// COPYRIGHT NOTICE 1.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 +// ALL RIGHTS RESERVED 1.9 +// This confidential and proprietary software may be used only as authorised by 1.10 +// a licensing agreement from Lattice Semiconductor Corporation. 1.11 +// The entire notice above must be reproduced on all authorized copies and 1.12 +// copies may only be made to the extent permitted by a licensing agreement from 1.13 +// Lattice Semiconductor Corporation. 1.14 +// 1.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 +// U.S.A email: techsupport@latticesemi.com 1.19 +// =============================================================================/ 1.20 +// FILE DETAILS 1.21 +// Project : LatticeMico32 1.22 +// File : SPIPROG.v 1.23 +// This module contains the ER2 regsiters of SPI Serial FLASH programmer IP 1.24 +// core. There are only three ER2 registers, one control register and two 1.25 +// data registers, in this IP core. The control register is a 8-bit wide 1.26 +// register for selecting which data register will be accessed when the 1.27 +// Control/Data# bit in ER1 register is low. Data register 0 is a readonly 1.28 +// ID register. It is composed of three register fields -- an 8-bit 1.29 +// "implementer", a 16-bit "IP_functionality", and a 12-bit "revision". 1.30 +// Data register 1 is a variable length register for sending commands to or 1.31 +// receiving readback data from the SPI Serial FLASH device. 1.32 +// Dependencies : None 1.33 +// Version : 6.1.17 1.34 +// 1. Reduced the the ID register (DR0) length from 36 bits to 8 bits. 1.35 +// 2. Same as TYPEA and TYPEB modules, use falling edge clock 1.36 +// for all TCK Flip-Flops. 1.37 +// 3. Added 7 delay Flip-Flops so that the DR1 readback data from 1.38 +// SPI Serial FLASH is in the byte boundary. 1.39 +// Version : 7.0SP2, 3.0 1.40 +// : No Change 1.41 +// Version : 3.1 1.42 +// : No Change 1.43 +// ============================================================================= 1.44 +//--------------------------------------------------------------------------- 1.45 +// 1.46 +//Name : SPIPROG.v 1.47 +// 1.48 +//Description: 1.49 +// 1.50 +// This module contains the ER2 regsiters of SPI Serial FLASH programmer IP 1.51 +// core. There are only three ER2 registers, one control register and two 1.52 +// data registers, in this IP core. The control register is a 8-bit wide 1.53 +// register for selecting which data register will be accessed when the 1.54 +// Control/Data# bit in ER1 register is low. Data register 0 is a readonly 1.55 +// ID register. It is composed of three register fields -- an 8-bit 1.56 +// "implementer", a 16-bit "IP_functionality", and a 12-bit "revision". 1.57 +// Data register 1 is a variable length register for sending commands to or 1.58 +// receiving readback data from the SPI Serial FLASH device. 1.59 +// 1.60 +//$Log: spiprog.vhd,v $ 1.61 +//Revision 1.2 2004-09-09 11:43:26-07 jhsin 1.62 +//1. Reduced the the ID register (DR0) length from 36 bits to 8 bits. 1.63 +//2. Same as TYPEA and TYPEB modules, use falling edge clock 1.64 +// for all TCK Flip-Flops. 1.65 +// 1.66 +//Revision 1.1 2004-08-12 13:22:05-07 jhsin 1.67 +//Added 7 delay Flip-Flops so that the DR1 readback data from SPI Serial FLASH is in the byte boundary. 1.68 +// 1.69 +//Revision 1.0 2004-08-03 18:35:56-07 jhsin 1.70 +//Initial revision 1.71 +// 1.72 +// 1.73 + 1.74 +module SPIPROG (input JTCK , 1.75 + input JTDI , 1.76 + output JTDO2 , 1.77 + input JSHIFT , 1.78 + input JUPDATE , 1.79 + input JRSTN , 1.80 + input JCE2 , 1.81 + input SPIPROG_ENABLE , 1.82 + input CONTROL_DATAN , 1.83 + output SPI_C , 1.84 + output SPI_D , 1.85 + output SPI_SN , 1.86 + input SPI_Q); 1.87 + 1.88 + wire er2Cr_enable ; 1.89 + wire er2Dr0_enable; 1.90 + wire er2Dr1_enable; 1.91 + 1.92 + wire tdo_er2Cr ; 1.93 + wire tdo_er2Dr0; 1.94 + wire tdo_er2Dr1; 1.95 + 1.96 + wire [7:0] encodedDrSelBits ; 1.97 + wire [8:0] er2CrTdiBit ; 1.98 + wire [8:0] er2Dr0TdiBit ; 1.99 + 1.100 + wire captureDrER2; 1.101 + reg spi_s ; 1.102 + reg [6:0] spi_q_dly; 1.103 + 1.104 + wire [7:0] ip_functionality_id; 1.105 + 1.106 + genvar i; 1.107 + 1.108 + // ------ Control Register 0 ------ 1.109 + 1.110 + assign er2Cr_enable = JCE2 & SPIPROG_ENABLE & CONTROL_DATAN; 1.111 + 1.112 + assign tdo_er2Cr = er2CrTdiBit[0]; 1.113 + 1.114 + // CR_BIT0_BIT7 1.115 + generate 1.116 + for(i=0; i<=7; i=i+1) 1.117 + begin:CR_BIT0_BIT7 1.118 + TYPEA BIT_N (.CLK (JTCK), 1.119 + .RESET_N (JRSTN), 1.120 + .CLKEN (er2Cr_enable), 1.121 + .TDI (er2CrTdiBit[i + 1]), 1.122 + .TDO (er2CrTdiBit[i]), 1.123 + .DATA_OUT (encodedDrSelBits[i]), 1.124 + .DATA_IN (encodedDrSelBits[i]), 1.125 + .CAPTURE_DR (captureDrER2), 1.126 + .UPDATE_DR (JUPDATE)); 1.127 + end 1.128 + endgenerate // CR_BIT0_BIT7 1.129 + 1.130 + assign er2CrTdiBit[8] = JTDI; 1.131 + 1.132 +// ------ Data Register 0 ------ 1.133 + assign er2Dr0_enable = (JCE2 & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000000)) ? 1'b1 : 1'b0; 1.134 + 1.135 + assign tdo_er2Dr0 = er2Dr0TdiBit[0]; 1.136 + 1.137 + assign ip_functionality_id = 8'b00000001; //-- SPI Serial FLASH Programmer (0x01) 1.138 + 1.139 +// DR0_BIT0_BIT7 1.140 + generate 1.141 + for(i=0; i<=7; i=i+1) 1.142 + begin:DR0_BIT0_BIT7 1.143 + TYPEB BIT_N (.CLK (JTCK), 1.144 + .RESET_N (JRSTN), 1.145 + .CLKEN (er2Dr0_enable), 1.146 + .TDI (er2Dr0TdiBit[i + 1]), 1.147 + .TDO (er2Dr0TdiBit[i]), 1.148 + .DATA_IN (ip_functionality_id[i]), 1.149 + .CAPTURE_DR (captureDrER2)); 1.150 + end 1.151 + endgenerate // DR0_BIT0_BIT7 1.152 + 1.153 + assign er2Dr0TdiBit[8] = JTDI; 1.154 + 1.155 +// ------ Data Register 1 ------ 1.156 + 1.157 + assign er2Dr1_enable = (JCE2 & JSHIFT & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000001)) ? 1'b1 : 1'b0; 1.158 + 1.159 + assign SPI_C = ~ (JTCK & er2Dr1_enable & spi_s); 1.160 + 1.161 + assign SPI_D = JTDI & er2Dr1_enable; 1.162 + 1.163 + // SPI_S_Proc 1.164 + always @(negedge JTCK or negedge JRSTN) 1.165 + begin 1.166 + if (~JRSTN) 1.167 + spi_s <= 1'b0; 1.168 + else 1.169 + if (JUPDATE) 1.170 + spi_s <= 1'b0; 1.171 + else 1.172 + spi_s <= er2Dr1_enable; 1.173 + end 1.174 + 1.175 + assign SPI_SN = ~spi_s; 1.176 + 1.177 + // SPI_Q_Proc 1.178 + always @(negedge JTCK or negedge JRSTN) 1.179 + begin 1.180 + if (~JRSTN) 1.181 + spi_q_dly <= 'b0; 1.182 + else 1.183 + if (er2Dr1_enable) 1.184 + spi_q_dly <= {spi_q_dly[5:0],SPI_Q}; 1.185 + end 1.186 + 1.187 + assign tdo_er2Dr1 = spi_q_dly[6]; 1.188 + 1.189 + // ------ JTDO2 MUX ------ 1.190 + 1.191 + assign JTDO2 = CONTROL_DATAN ? tdo_er2Cr : 1.192 + (encodedDrSelBits == 8'b00000000) ? tdo_er2Dr0 : 1.193 + (encodedDrSelBits == 8'b00000001) ? tdo_er2Dr1 : 1'b0; 1.194 + 1.195 + assign captureDrER2 = ~JSHIFT & JCE2; 1.196 + 1.197 +endmodule