1.1 diff -r 73de224304c1 -r d6c693415d59 lm32_instruction_unit.v 1.2 --- a/lm32_instruction_unit.v Sat Aug 06 00:02:46 2011 +0100 1.3 +++ b/lm32_instruction_unit.v Sat Aug 06 01:26:56 2011 +0100 1.4 @@ -587,31 +587,31 @@ 1.5 `ifdef CFG_DEBUG_ENABLED 1.6 `ifdef CFG_ALTERNATE_EBA 1.7 if (at_debug == `TRUE) 1.8 - pc_f <= #1 (`CFG_DEBA_RESET-4)/4; 1.9 + pc_f <= (`CFG_DEBA_RESET-4)/4; 1.10 else 1.11 - pc_f <= #1 (`CFG_EBA_RESET-4)/4; 1.12 + pc_f <= (`CFG_EBA_RESET-4)/4; 1.13 `else 1.14 - pc_f <= #1 (`CFG_EBA_RESET-4)/4; 1.15 + pc_f <= (`CFG_EBA_RESET-4)/4; 1.16 `endif 1.17 `else 1.18 - pc_f <= #1 (`CFG_EBA_RESET-4)/4; 1.19 + pc_f <= (`CFG_EBA_RESET-4)/4; 1.20 `endif 1.21 - pc_d <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.22 - pc_x <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.23 - pc_m <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.24 - pc_w <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.25 + pc_d <= {`LM32_PC_WIDTH{1'b0}}; 1.26 + pc_x <= {`LM32_PC_WIDTH{1'b0}}; 1.27 + pc_m <= {`LM32_PC_WIDTH{1'b0}}; 1.28 + pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.29 end 1.30 else 1.31 begin 1.32 if (stall_f == `FALSE) 1.33 - pc_f <= #1 pc_a; 1.34 + pc_f <= pc_a; 1.35 if (stall_d == `FALSE) 1.36 - pc_d <= #1 pc_f; 1.37 + pc_d <= pc_f; 1.38 if (stall_x == `FALSE) 1.39 - pc_x <= #1 pc_d; 1.40 + pc_x <= pc_d; 1.41 if (stall_m == `FALSE) 1.42 - pc_m <= #1 pc_x; 1.43 - pc_w <= #1 pc_m; 1.44 + pc_m <= pc_x; 1.45 + pc_w <= pc_m; 1.46 end 1.47 end 1.48 1.49 @@ -620,24 +620,24 @@ 1.50 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.51 begin 1.52 if (rst_i == `TRUE) 1.53 - restart_address <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.54 + restart_address <= {`LM32_PC_WIDTH{1'b0}}; 1.55 else 1.56 begin 1.57 `ifdef CFG_DCACHE_ENABLED 1.58 `ifdef CFG_ICACHE_ENABLED 1.59 // D-cache restart address must take priority, otherwise instructions will be lost 1.60 if (dcache_refill_request == `TRUE) 1.61 - restart_address <= #1 pc_w; 1.62 + restart_address <= pc_w; 1.63 else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request)) 1.64 - restart_address <= #1 icache_refill_address; 1.65 + restart_address <= icache_refill_address; 1.66 `else 1.67 if (dcache_refill_request == `TRUE) 1.68 - restart_address <= #1 pc_w; 1.69 + restart_address <= pc_w; 1.70 `endif 1.71 `else 1.72 `ifdef CFG_ICACHE_ENABLED 1.73 if (icache_refill_request == `TRUE) 1.74 - restart_address <= #1 icache_refill_address; 1.75 + restart_address <= icache_refill_address; 1.76 `endif 1.77 `endif 1.78 end 1.79 @@ -649,11 +649,11 @@ 1.80 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.81 begin 1.82 if (rst_i == `TRUE) 1.83 - irom_select_f <= #1 `FALSE; 1.84 + irom_select_f <= `FALSE; 1.85 else 1.86 begin 1.87 if (stall_f == `FALSE) 1.88 - irom_select_f <= #1 irom_select_a; 1.89 + irom_select_f <= irom_select_a; 1.90 end 1.91 end 1.92 `endif 1.93 @@ -678,25 +678,25 @@ 1.94 begin 1.95 if (rst_i == `TRUE) 1.96 begin 1.97 - i_cyc_o <= #1 `FALSE; 1.98 - i_stb_o <= #1 `FALSE; 1.99 - i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.100 - i_cti_o <= #1 `LM32_CTYPE_END; 1.101 - i_lock_o <= #1 `FALSE; 1.102 - icache_refill_data <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.103 - icache_refill_ready <= #1 `FALSE; 1.104 + i_cyc_o <= `FALSE; 1.105 + i_stb_o <= `FALSE; 1.106 + i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 1.107 + i_cti_o <= `LM32_CTYPE_END; 1.108 + i_lock_o <= `FALSE; 1.109 + icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.110 + icache_refill_ready <= `FALSE; 1.111 `ifdef CFG_BUS_ERRORS_ENABLED 1.112 - bus_error_f <= #1 `FALSE; 1.113 + bus_error_f <= `FALSE; 1.114 `endif 1.115 `ifdef CFG_HW_DEBUG_ENABLED 1.116 - i_we_o <= #1 `FALSE; 1.117 - i_sel_o <= #1 4'b1111; 1.118 - jtag_access <= #1 `FALSE; 1.119 + i_we_o <= `FALSE; 1.120 + i_sel_o <= 4'b1111; 1.121 + jtag_access <= `FALSE; 1.122 `endif 1.123 end 1.124 else 1.125 begin 1.126 - icache_refill_ready <= #1 `FALSE; 1.127 + icache_refill_ready <= `FALSE; 1.128 // Is a cycle in progress? 1.129 if (i_cyc_o == `TRUE) 1.130 begin 1.131 @@ -706,10 +706,10 @@ 1.132 `ifdef CFG_HW_DEBUG_ENABLED 1.133 if (jtag_access == `TRUE) 1.134 begin 1.135 - i_cyc_o <= #1 `FALSE; 1.136 - i_stb_o <= #1 `FALSE; 1.137 - i_we_o <= #1 `FALSE; 1.138 - jtag_access <= #1 `FALSE; 1.139 + i_cyc_o <= `FALSE; 1.140 + i_stb_o <= `FALSE; 1.141 + i_we_o <= `FALSE; 1.142 + jtag_access <= `FALSE; 1.143 end 1.144 else 1.145 `endif 1.146 @@ -717,22 +717,22 @@ 1.147 if (last_word == `TRUE) 1.148 begin 1.149 // Cache line fill complete 1.150 - i_cyc_o <= #1 `FALSE; 1.151 - i_stb_o <= #1 `FALSE; 1.152 - i_lock_o <= #1 `FALSE; 1.153 + i_cyc_o <= `FALSE; 1.154 + i_stb_o <= `FALSE; 1.155 + i_lock_o <= `FALSE; 1.156 end 1.157 // Fetch next word in cache line 1.158 - i_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 1.159 - i_cti_o <= #1 next_cycle_type; 1.160 + i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 1.161 + i_cti_o <= next_cycle_type; 1.162 // Write fetched data into instruction cache 1.163 - icache_refill_ready <= #1 `TRUE; 1.164 - icache_refill_data <= #1 i_dat_i; 1.165 + icache_refill_ready <= `TRUE; 1.166 + icache_refill_data <= i_dat_i; 1.167 end 1.168 end 1.169 `ifdef CFG_BUS_ERRORS_ENABLED 1.170 if (i_err_i == `TRUE) 1.171 begin 1.172 - bus_error_f <= #1 `TRUE; 1.173 + bus_error_f <= `TRUE; 1.174 $display ("Instruction bus error. Address: %x", i_adr_o); 1.175 end 1.176 `endif 1.177 @@ -743,15 +743,15 @@ 1.178 begin 1.179 // Read first word of cache line 1.180 `ifdef CFG_HW_DEBUG_ENABLED 1.181 - i_sel_o <= #1 4'b1111; 1.182 + i_sel_o <= 4'b1111; 1.183 `endif 1.184 - i_adr_o <= #1 {first_address, 2'b00}; 1.185 - i_cyc_o <= #1 `TRUE; 1.186 - i_stb_o <= #1 `TRUE; 1.187 - i_cti_o <= #1 first_cycle_type; 1.188 - //i_lock_o <= #1 `TRUE; 1.189 + i_adr_o <= {first_address, 2'b00}; 1.190 + i_cyc_o <= `TRUE; 1.191 + i_stb_o <= `TRUE; 1.192 + i_cti_o <= first_cycle_type; 1.193 + //i_lock_o <= `TRUE; 1.194 `ifdef CFG_BUS_ERRORS_ENABLED 1.195 - bus_error_f <= #1 `FALSE; 1.196 + bus_error_f <= `FALSE; 1.197 `endif 1.198 end 1.199 `ifdef CFG_HW_DEBUG_ENABLED 1.200 @@ -760,18 +760,18 @@ 1.201 if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE)) 1.202 begin 1.203 case (jtag_address[1:0]) 1.204 - 2'b00: i_sel_o <= #1 4'b1000; 1.205 - 2'b01: i_sel_o <= #1 4'b0100; 1.206 - 2'b10: i_sel_o <= #1 4'b0010; 1.207 - 2'b11: i_sel_o <= #1 4'b0001; 1.208 + 2'b00: i_sel_o <= 4'b1000; 1.209 + 2'b01: i_sel_o <= 4'b0100; 1.210 + 2'b10: i_sel_o <= 4'b0010; 1.211 + 2'b11: i_sel_o <= 4'b0001; 1.212 endcase 1.213 - i_adr_o <= #1 jtag_address; 1.214 - i_dat_o <= #1 {4{jtag_write_data}}; 1.215 - i_cyc_o <= #1 `TRUE; 1.216 - i_stb_o <= #1 `TRUE; 1.217 - i_we_o <= #1 jtag_write_enable; 1.218 - i_cti_o <= #1 `LM32_CTYPE_END; 1.219 - jtag_access <= #1 `TRUE; 1.220 + i_adr_o <= jtag_address; 1.221 + i_dat_o <= {4{jtag_write_data}}; 1.222 + i_cyc_o <= `TRUE; 1.223 + i_stb_o <= `TRUE; 1.224 + i_we_o <= jtag_write_enable; 1.225 + i_cti_o <= `LM32_CTYPE_END; 1.226 + jtag_access <= `TRUE; 1.227 end 1.228 end 1.229 `endif 1.230 @@ -780,10 +780,10 @@ 1.231 // continually generated if exception handler is cached 1.232 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.233 if (branch_taken_x == `TRUE) 1.234 - bus_error_f <= #1 `FALSE; 1.235 + bus_error_f <= `FALSE; 1.236 `endif 1.237 if (branch_taken_m == `TRUE) 1.238 - bus_error_f <= #1 `FALSE; 1.239 + bus_error_f <= `FALSE; 1.240 `endif 1.241 end 1.242 end 1.243 @@ -793,14 +793,14 @@ 1.244 begin 1.245 if (rst_i == `TRUE) 1.246 begin 1.247 - i_cyc_o <= #1 `FALSE; 1.248 - i_stb_o <= #1 `FALSE; 1.249 - i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.250 - i_cti_o <= #1 `LM32_CTYPE_END; 1.251 - i_lock_o <= #1 `FALSE; 1.252 - wb_data_f <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.253 + i_cyc_o <= `FALSE; 1.254 + i_stb_o <= `FALSE; 1.255 + i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 1.256 + i_cti_o <= `LM32_CTYPE_END; 1.257 + i_lock_o <= `FALSE; 1.258 + wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.259 `ifdef CFG_BUS_ERRORS_ENABLED 1.260 - bus_error_f <= #1 `FALSE; 1.261 + bus_error_f <= `FALSE; 1.262 `endif 1.263 end 1.264 else 1.265 @@ -812,15 +812,15 @@ 1.266 if((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 1.267 begin 1.268 // Cycle complete 1.269 - i_cyc_o <= #1 `FALSE; 1.270 - i_stb_o <= #1 `FALSE; 1.271 + i_cyc_o <= `FALSE; 1.272 + i_stb_o <= `FALSE; 1.273 // Register fetched instruction 1.274 - wb_data_f <= #1 i_dat_i; 1.275 + wb_data_f <= i_dat_i; 1.276 end 1.277 `ifdef CFG_BUS_ERRORS_ENABLED 1.278 if (i_err_i == `TRUE) 1.279 begin 1.280 - bus_error_f <= #1 `TRUE; 1.281 + bus_error_f <= `TRUE; 1.282 $display ("Instruction bus error. Address: %x", i_adr_o); 1.283 end 1.284 `endif 1.285 @@ -836,13 +836,13 @@ 1.286 begin 1.287 // Fetch instruction 1.288 `ifdef CFG_HW_DEBUG_ENABLED 1.289 - i_sel_o <= #1 4'b1111; 1.290 + i_sel_o <= 4'b1111; 1.291 `endif 1.292 - i_adr_o <= #1 {pc_a, 2'b00}; 1.293 - i_cyc_o <= #1 `TRUE; 1.294 - i_stb_o <= #1 `TRUE; 1.295 + i_adr_o <= {pc_a, 2'b00}; 1.296 + i_cyc_o <= `TRUE; 1.297 + i_stb_o <= `TRUE; 1.298 `ifdef CFG_BUS_ERRORS_ENABLED 1.299 - bus_error_f <= #1 `FALSE; 1.300 + bus_error_f <= `FALSE; 1.301 `endif 1.302 end 1.303 else 1.304 @@ -854,7 +854,7 @@ 1.305 ) 1.306 begin 1.307 `ifdef CFG_BUS_ERRORS_ENABLED 1.308 - bus_error_f <= #1 `FALSE; 1.309 + bus_error_f <= `FALSE; 1.310 `endif 1.311 end 1.312 end 1.313 @@ -869,18 +869,18 @@ 1.314 begin 1.315 if (rst_i == `TRUE) 1.316 begin 1.317 - instruction_d <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.318 + instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.319 `ifdef CFG_BUS_ERRORS_ENABLED 1.320 - bus_error_d <= #1 `FALSE; 1.321 + bus_error_d <= `FALSE; 1.322 `endif 1.323 end 1.324 else 1.325 begin 1.326 if (stall_d == `FALSE) 1.327 begin 1.328 - instruction_d <= #1 instruction_f; 1.329 + instruction_d <= instruction_f; 1.330 `ifdef CFG_BUS_ERRORS_ENABLED 1.331 - bus_error_d <= #1 bus_error_f; 1.332 + bus_error_d <= bus_error_f; 1.333 `endif 1.334 end 1.335 end