Disable Lattice-specific stuff by default

To build on Lattice platforms, `define PLATFORM_LATTICE in lm32_include.v.
Otherwise, non-optimal "platform independent" HDL will be used.
This means LM32 can now be built for non-Lattice FPGAs.

     1.1 diff -r ae6035050124 -r a61bb364ae1f lm32_addsub.v
     1.2 --- a/lm32_addsub.v	Sun Apr 04 20:42:58 2010 +0100
     1.3 +++ b/lm32_addsub.v	Sun Apr 04 20:52:32 2010 +0100
     1.4 @@ -64,13 +64,17 @@
     1.5  // Instantiations
     1.6  ///////////////////////////////////////////////////// 
     1.7  
     1.8 +// Only use Lattice specific constructs when compiling with ispLEVER
     1.9 +`ifdef PLATFORM_LATTICE
    1.10         generate
    1.11  	  if (`LATTICE_FAMILY == "SC" || `LATTICE_FAMILY == "SCM") begin
    1.12 +`endif
    1.13  	     wire [32:0] tmp_addResult = DataA + DataB + Cin;
    1.14  	     wire [32:0] tmp_subResult = DataA - DataB - !Cin;   
    1.15     
    1.16  	     assign  Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
    1.17  	     assign  Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
    1.18 +`ifdef PLATFORM_LATTICE
    1.19  	  end else begin
    1.20  	    pmi_addsub #(// ----- Parameters -------
    1.21  			 .pmi_data_width     (32),
    1.22 @@ -89,5 +93,6 @@
    1.23  			 .Overflow           ());
    1.24  	  end
    1.25         endgenerate 
    1.26 +`endif
    1.27  
    1.28  endmodule

     2.1 diff -r ae6035050124 -r a61bb364ae1f lm32_dcache.v
     2.2 --- a/lm32_dcache.v	Sun Apr 04 20:42:58 2010 +0100
     2.3 +++ b/lm32_dcache.v	Sun Apr 04 20:52:32 2010 +0100
     2.4 @@ -196,14 +196,16 @@
     2.5  		    // ----- Parameters -------
     2.6  		    .data_width (32),
     2.7  		    .address_width (`LM32_DC_DMEM_ADDR_WIDTH),
     2.8 -`ifdef CFG_DCACHE_DAT_USE_DP_TRUE
     2.9 +`ifdef PLATFORM_LATTICE
    2.10 + `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
    2.11  		    .RAM_IMPLEMENTATION ("EBR"),
    2.12  		    .RAM_TYPE ("RAM_DP_TRUE")
    2.13 -`else
    2.14 - `ifdef CFG_DCACHE_DAT_USE_SLICE
    2.15 + `else
    2.16 +  `ifdef CFG_DCACHE_DAT_USE_SLICE
    2.17  		    .RAM_IMPLEMENTATION ("SLICE")
    2.18 - `else
    2.19 +  `else
    2.20  		    .RAM_IMPLEMENTATION ("AUTO")
    2.21 +  `endif
    2.22   `endif
    2.23  `endif
    2.24  		    ) way_0_data_ram 

     3.1 diff -r ae6035050124 -r a61bb364ae1f lm32_icache.v
     3.2 --- a/lm32_icache.v	Sun Apr 04 20:42:58 2010 +0100
     3.3 +++ b/lm32_icache.v	Sun Apr 04 20:52:32 2010 +0100
     3.4 @@ -199,18 +199,20 @@
     3.5  	       // ----- Parameters -------
     3.6  	       .data_width                 (32),
     3.7  	       .address_width              (`LM32_IC_DMEM_ADDR_WIDTH),
     3.8 -`ifdef CFG_ICACHE_DAT_USE_DP_TRUE
     3.9 +`ifdef PLATFORM_LATTICE
    3.10 + `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
    3.11  	       .RAM_IMPLEMENTATION         ("EBR"),
    3.12  	       .RAM_TYPE                   ("RAM_DP_TRUE")
    3.13 -`else
    3.14 - `ifdef CFG_ICACHE_DAT_USE_DP
    3.15 + `else
    3.16 +  `ifdef CFG_ICACHE_DAT_USE_DP
    3.17  	       .RAM_IMPLEMENTATION         ("EBR"),
    3.18  	       .RAM_TYPE                   ("RAM_DP")
    3.19 - `else
    3.20 -  `ifdef CFG_ICACHE_DAT_USE_SLICE
    3.21 +  `else
    3.22 +   `ifdef CFG_ICACHE_DAT_USE_SLICE
    3.23  	       .RAM_IMPLEMENTATION         ("SLICE")
    3.24 -  `else
    3.25 +   `else
    3.26  	       .RAM_IMPLEMENTATION         ("AUTO")
    3.27 +   `endif
    3.28    `endif
    3.29   `endif
    3.30  `endif

     4.1 diff -r ae6035050124 -r a61bb364ae1f lm32_ram.v
     4.2 --- a/lm32_ram.v	Sun Apr 04 20:42:58 2010 +0100
     4.3 +++ b/lm32_ram.v	Sun Apr 04 20:52:32 2010 +0100
     4.4 @@ -58,10 +58,12 @@
     4.5      ----------------------------------------------------------------------*/
     4.6     parameter data_width = 1;               // Width of the data ports
     4.7     parameter address_width = 1;            // Width of the address ports
     4.8 +`ifdef PLATFORM_LATTICE
     4.9     parameter RAM_IMPLEMENTATION = "AUTO";  // Implement memory in EBRs, else
    4.10                                             // let synthesis tool select best 
    4.11                                             // possible solution (EBR or LUT)
    4.12     parameter RAM_TYPE = "RAM_DP";          // Type of EBR to be used
    4.13 +`endif
    4.14     
    4.15     /*----------------------------------------------------------------------
    4.16      Inputs
    4.17 @@ -82,7 +84,8 @@
    4.18      ----------------------------------------------------------------------*/
    4.19     output [data_width-1:0] read_data;      // Data read from specified addess
    4.20     wire   [data_width-1:0] read_data;
    4.21 -   
    4.22 +
    4.23 +`ifdef PLATFORM_LATTICE
    4.24     generate
    4.25        
    4.26        if ( RAM_IMPLEMENTATION == "EBR" )
    4.27 @@ -257,6 +260,7 @@
    4.28        
    4.29  	else 
    4.30  	  begin
    4.31 +`endif
    4.32  	     /*----------------------------------------------------------------------
    4.33  	      Internal nets and registers
    4.34  	      ----------------------------------------------------------------------*/
    4.35 @@ -282,8 +286,9 @@
    4.36  	       if (enable_read)
    4.37  		 ra <= read_address;
    4.38  	     
    4.39 +`ifdef PLATFORM_LATTICE
    4.40  	  end
    4.41  
    4.42     endgenerate
    4.43 -
    4.44 +`endif
    4.45  endmodule
lm32_addsub.v		file \| annotate \| diff \| revisions
lm32_dcache.v		file \| annotate \| diff \| revisions
lm32_icache.v		file \| annotate \| diff \| revisions
lm32_ram.v		file \| annotate \| diff \| revisions