Fri, 13 Aug 2010 10:43:05 +0100
Initial commit, DMAC version 3.1
| philpem@0 | 1 | // ============================================================================= |
| philpem@0 | 2 | // COPYRIGHT NOTICE |
| philpem@0 | 3 | // Copyright 2006 (c) Lattice Semiconductor Corporation |
| philpem@0 | 4 | // ALL RIGHTS RESERVED |
| philpem@0 | 5 | // This confidential and proprietary software may be used only as authorised by |
| philpem@0 | 6 | // a licensing agreement from Lattice Semiconductor Corporation. |
| philpem@0 | 7 | // The entire notice above must be reproduced on all authorized copies and |
| philpem@0 | 8 | // copies may only be made to the extent permitted by a licensing agreement from |
| philpem@0 | 9 | // Lattice Semiconductor Corporation. |
| philpem@0 | 10 | // |
| philpem@0 | 11 | // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) |
| philpem@0 | 12 | // 5555 NE Moore Court 408-826-6000 (other locations) |
| philpem@0 | 13 | // Hillsboro, OR 97124 web : http://www.latticesemi.com/ |
| philpem@0 | 14 | // U.S.A email: techsupport@latticesemi.com |
| philpem@0 | 15 | // =============================================================================/ |
| philpem@0 | 16 | // FILE DETAILS |
| philpem@0 | 17 | // Project : LM32 DMA Component |
| philpem@0 | 18 | // File : wb_dma_ctrl.v |
| philpem@0 | 19 | // Title : DMA controller top file |
| philpem@0 | 20 | // Dependencies : None |
| philpem@0 | 21 | // Version : 7.0 |
| philpem@0 | 22 | // : Initial Release |
| philpem@0 | 23 | // Version : 7.0SP2, 3.0 |
| philpem@0 | 24 | // 1. Read and Write channel of DMA controller are working in parallel, |
| philpem@0 | 25 | // due to that now as soon as FIFO is not empty write channel of the DMA |
| philpem@0 | 26 | // controller start writing data to the slave. |
| philpem@0 | 27 | // 2. Burst Size supported by DMA controller is increased to support bigger |
| philpem@0 | 28 | // burst (from current value of 4 and 8 to 16 and 32). Now 4 different type |
| philpem@0 | 29 | // of burst sizes are supported by the DMA controller 4, 8, 16 and 32. |
| philpem@0 | 30 | // For this Burst Size field of the control register is increased to 2 bits. |
| philpem@0 | 31 | // 3. Glitch is removed on the S_ACK_O signal. |
| philpem@0 | 32 | // Version : 3.1 |
| philpem@0 | 33 | // : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec |
| philpem@0 | 34 | // : which defines alignement of bytes in sub-word transfers. |
| philpem@0 | 35 | // ============================================================================= |
| philpem@0 | 36 | |
| philpem@0 | 37 | `ifndef WB_DMA_CTRL_FILE |
| philpem@0 | 38 | `define WB_DMA_CTRL_FILE |
| philpem@0 | 39 | `include "system_conf.v" |
| philpem@0 | 40 | module wb_dma_ctrl #(parameter LENGTH_WIDTH = 16, |
| philpem@0 | 41 | parameter FIFO_IMPLEMENTATION = "EBR") |
| philpem@0 | 42 | ( |
| philpem@0 | 43 | //master read port |
| philpem@0 | 44 | MA_ADR_O, //32bits |
| philpem@0 | 45 | MA_WE_O, |
| philpem@0 | 46 | MA_SEL_O, //4bits |
| philpem@0 | 47 | MA_STB_O, |
| philpem@0 | 48 | MA_CYC_O, |
| philpem@0 | 49 | MA_LOCK_O, |
| philpem@0 | 50 | MA_CTI_O, |
| philpem@0 | 51 | MA_BTE_O, |
| philpem@0 | 52 | MA_DAT_I, //32bits |
| philpem@0 | 53 | MA_DAT_O, //32bits |
| philpem@0 | 54 | MA_ACK_I, |
| philpem@0 | 55 | MA_ERR_I, |
| philpem@0 | 56 | MA_RTY_I, |
| philpem@0 | 57 | //master write port |
| philpem@0 | 58 | MB_ADR_O, //32bits |
| philpem@0 | 59 | MB_DAT_O, //32bits |
| philpem@0 | 60 | MB_WE_O, |
| philpem@0 | 61 | MB_SEL_O, //4bits |
| philpem@0 | 62 | MB_STB_O, |
| philpem@0 | 63 | MB_CYC_O, |
| philpem@0 | 64 | MB_LOCK_O, |
| philpem@0 | 65 | MB_CTI_O, |
| philpem@0 | 66 | MB_BTE_O, |
| philpem@0 | 67 | MB_DAT_I, //32bits |
| philpem@0 | 68 | MB_ACK_I, |
| philpem@0 | 69 | MB_ERR_I, |
| philpem@0 | 70 | MB_RTY_I, |
| philpem@0 | 71 | //slave port |
| philpem@0 | 72 | S_ADR_I, //32bits |
| philpem@0 | 73 | S_DAT_I, //32bits |
| philpem@0 | 74 | S_WE_I, |
| philpem@0 | 75 | S_STB_I, |
| philpem@0 | 76 | S_CYC_I, |
| philpem@0 | 77 | S_SEL_I, |
| philpem@0 | 78 | S_LOCK_I, |
| philpem@0 | 79 | S_CTI_I, |
| philpem@0 | 80 | S_BTE_I, |
| philpem@0 | 81 | S_DAT_O, //32bits |
| philpem@0 | 82 | S_ACK_O, |
| philpem@0 | 83 | S_ERR_O, |
| philpem@0 | 84 | S_RTY_O, |
| philpem@0 | 85 | S_INT_O, |
| philpem@0 | 86 | //system clock and reset |
| philpem@0 | 87 | CLK_I, |
| philpem@0 | 88 | RST_I |
| philpem@0 | 89 | ); |
| philpem@0 | 90 | //master read port |
| philpem@0 | 91 | output [31:0] MA_ADR_O; //32bits |
| philpem@0 | 92 | output MA_WE_O; |
| philpem@0 | 93 | output [3:0] MA_SEL_O; //4bits |
| philpem@0 | 94 | output MA_STB_O; |
| philpem@0 | 95 | output MA_CYC_O; |
| philpem@0 | 96 | output MA_LOCK_O; |
| philpem@0 | 97 | output [2:0] MA_CTI_O; |
| philpem@0 | 98 | output [1:0] MA_BTE_O; |
| philpem@0 | 99 | output [31:0] MA_DAT_O; //32bits |
| philpem@0 | 100 | input [31:0] MA_DAT_I; //32bits |
| philpem@0 | 101 | input MA_ACK_I; |
| philpem@0 | 102 | input MA_ERR_I; |
| philpem@0 | 103 | input MA_RTY_I; |
| philpem@0 | 104 | //master write port |
| philpem@0 | 105 | output [31:0] MB_ADR_O; //32bits |
| philpem@0 | 106 | output [31:0] MB_DAT_O; //32bits |
| philpem@0 | 107 | output MB_WE_O; |
| philpem@0 | 108 | output [3:0] MB_SEL_O; //4bits |
| philpem@0 | 109 | output MB_STB_O; |
| philpem@0 | 110 | output MB_CYC_O; |
| philpem@0 | 111 | output [2:0] MB_CTI_O; |
| philpem@0 | 112 | output MB_LOCK_O; |
| philpem@0 | 113 | output [1:0] MB_BTE_O; |
| philpem@0 | 114 | input [31:0] MB_DAT_I; //32bits |
| philpem@0 | 115 | input MB_ACK_I; |
| philpem@0 | 116 | input MB_ERR_I; |
| philpem@0 | 117 | input MB_RTY_I; |
| philpem@0 | 118 | //slave port |
| philpem@0 | 119 | input [31:0] S_ADR_I; //32bits |
| philpem@0 | 120 | input [31:0] S_DAT_I; //32bits |
| philpem@0 | 121 | input S_WE_I; |
| philpem@0 | 122 | input S_STB_I; |
| philpem@0 | 123 | input S_CYC_I; |
| philpem@0 | 124 | input [2:0] S_CTI_I; |
| philpem@0 | 125 | input [1:0] S_BTE_I; |
| philpem@0 | 126 | input [3:0] S_SEL_I; |
| philpem@0 | 127 | input S_LOCK_I; |
| philpem@0 | 128 | output [31:0] S_DAT_O; //32bits |
| philpem@0 | 129 | output S_ACK_O; |
| philpem@0 | 130 | output S_ERR_O; |
| philpem@0 | 131 | output S_RTY_O; |
| philpem@0 | 132 | output S_INT_O; |
| philpem@0 | 133 | //system clock and reset |
| philpem@0 | 134 | input CLK_I; |
| philpem@0 | 135 | input RST_I; |
| philpem@0 | 136 | |
| philpem@0 | 137 | wire [31:0] MA_DAT_O = 0; |
| philpem@0 | 138 | wire [1:0] MA_BTE_O = 0; |
| philpem@0 | 139 | wire MA_LOCK_O; |
| philpem@0 | 140 | |
| philpem@0 | 141 | wire [1:0] MB_BTE_O = 0; |
| philpem@0 | 142 | wire MB_LOCK_O; |
| philpem@0 | 143 | |
| philpem@0 | 144 | wire S_ERR_O = 0; |
| philpem@0 | 145 | wire S_RTY_O = 0; |
| philpem@0 | 146 | |
| philpem@0 | 147 | wire [LENGTH_WIDTH-1:0] data_length;//read back data |
| philpem@0 | 148 | wire [2:0] incr_unit; |
| philpem@0 | 149 | wire [31:0] reg_00_data; |
| philpem@0 | 150 | wire [31:0] reg_04_data; |
| philpem@0 | 151 | wire [3:0] M_SEL_O; |
| philpem@0 | 152 | |
| philpem@0 | 153 | //slave port:master write/read data to/from register file. |
| philpem@0 | 154 | SLAVE_REG #(.LENGTH_WIDTH(LENGTH_WIDTH), |
| philpem@0 | 155 | .FIFO_IMPLEMENTATION(FIFO_IMPLEMENTATION)) SLAVE_REG( |
| philpem@0 | 156 | .S_ADR_I (S_ADR_I ), |
| philpem@0 | 157 | .S_DAT_I (S_DAT_I ), |
| philpem@0 | 158 | .S_WE_I (S_WE_I ), |
| philpem@0 | 159 | .S_STB_I (S_STB_I ), |
| philpem@0 | 160 | .S_CYC_I (S_CYC_I ), |
| philpem@0 | 161 | .S_CTI_I (S_CTI_I ), |
| philpem@0 | 162 | .S_DAT_O (S_DAT_O ), |
| philpem@0 | 163 | .S_ACK_O (S_ACK_O ), |
| philpem@0 | 164 | .S_INT_O (S_INT_O ), |
| philpem@0 | 165 | //Master Addr |
| philpem@0 | 166 | .M_SEL_O (M_SEL_O ), |
| philpem@0 | 167 | // .MA_SEL_O (MA_SEL_O ), |
| philpem@0 | 168 | // .MB_SEL_O (MB_SEL_O ), |
| philpem@0 | 169 | //internal signals |
| philpem@0 | 170 | .reg_start (reg_start ), |
| philpem@0 | 171 | .reg_status (reg_status ), |
| philpem@0 | 172 | .reg_interrupt (reg_interrupt ), |
| philpem@0 | 173 | .reg_busy (reg_busy ), |
| philpem@0 | 174 | .data_length (data_length ), |
| philpem@0 | 175 | .reg_cntlg (reg_cntlg ), |
| philpem@0 | 176 | .reg_bt2 (reg_bt2 ), |
| philpem@0 | 177 | .reg_bt1 (reg_bt1 ), |
| philpem@0 | 178 | .reg_bt0 (reg_bt0 ), |
| philpem@0 | 179 | .reg_s_con (reg_s_con ), |
| philpem@0 | 180 | .reg_d_con (reg_d_con ), |
| philpem@0 | 181 | .incr_unit (incr_unit ), |
| philpem@0 | 182 | .reg_00_data (reg_00_data ), |
| philpem@0 | 183 | .reg_04_data (reg_04_data ), |
| philpem@0 | 184 | //system clock and reset |
| philpem@0 | 185 | .CLK_I (CLK_I ), |
| philpem@0 | 186 | .RST_I (RST_I ) |
| philpem@0 | 187 | ); |
| philpem@0 | 188 | |
| philpem@0 | 189 | //Master control |
| philpem@0 | 190 | MASTER_CTRL #(.LENGTH_WIDTH(LENGTH_WIDTH), |
| philpem@0 | 191 | .FIFO_IMPLEMENTATION(FIFO_IMPLEMENTATION)) MASTER_CTRL( |
| philpem@0 | 192 | //master read port |
| philpem@0 | 193 | .MA_ADR_O (MA_ADR_O ), |
| philpem@0 | 194 | .MA_SEL_O (MA_SEL_O ), |
| philpem@0 | 195 | .MA_WE_O (MA_WE_O ), |
| philpem@0 | 196 | .MA_STB_O (MA_STB_O ), |
| philpem@0 | 197 | .MA_CYC_O (MA_CYC_O ), |
| philpem@0 | 198 | .MA_CTI_O (MA_CTI_O ), |
| philpem@0 | 199 | .MA_LOCK_O (MA_LOCK_O ), |
| philpem@0 | 200 | .MA_DAT_I (MA_DAT_I ), //32bits |
| philpem@0 | 201 | .MA_ACK_I (MA_ACK_I ), |
| philpem@0 | 202 | .MA_ERR_I (MA_ERR_I ), |
| philpem@0 | 203 | .MA_RTY_I (MA_RTY_I ), |
| philpem@0 | 204 | //master write port |
| philpem@0 | 205 | .MB_ADR_O (MB_ADR_O ), |
| philpem@0 | 206 | .MB_SEL_O (MB_SEL_O ), |
| philpem@0 | 207 | .MB_DAT_O (MB_DAT_O ), //32bits |
| philpem@0 | 208 | .MB_WE_O (MB_WE_O ), |
| philpem@0 | 209 | .MB_STB_O (MB_STB_O ), |
| philpem@0 | 210 | .MB_CYC_O (MB_CYC_O ), |
| philpem@0 | 211 | .MB_CTI_O (MB_CTI_O ), |
| philpem@0 | 212 | .MB_LOCK_O (MB_LOCK_O ), |
| philpem@0 | 213 | .MB_ACK_I (MB_ACK_I ), |
| philpem@0 | 214 | .MB_ERR_I (MB_ERR_I ), |
| philpem@0 | 215 | .MB_RTY_I (MB_RTY_I ), |
| philpem@0 | 216 | //register interface |
| philpem@0 | 217 | .M_SEL_O (M_SEL_O ), |
| philpem@0 | 218 | .reg_start (reg_start ), |
| philpem@0 | 219 | .reg_status (reg_status ), |
| philpem@0 | 220 | .reg_interrupt (reg_interrupt ), |
| philpem@0 | 221 | .reg_busy (reg_busy ), |
| philpem@0 | 222 | .data_length (data_length ), |
| philpem@0 | 223 | .reg_cntlg (reg_cntlg ), |
| philpem@0 | 224 | .reg_bt2 (reg_bt2 ), |
| philpem@0 | 225 | .reg_bt1 (reg_bt1 ), |
| philpem@0 | 226 | .reg_bt0 (reg_bt0 ), |
| philpem@0 | 227 | .reg_s_con (reg_s_con ), |
| philpem@0 | 228 | .reg_d_con (reg_d_con ), |
| philpem@0 | 229 | .incr_unit (incr_unit ), |
| philpem@0 | 230 | .reg_00_data (reg_00_data ), |
| philpem@0 | 231 | .reg_04_data (reg_04_data ), |
| philpem@0 | 232 | //system clock and reset |
| philpem@0 | 233 | .CLK_I (CLK_I ), |
| philpem@0 | 234 | .RST_I (RST_I ) |
| philpem@0 | 235 | ); |
| philpem@0 | 236 | endmodule // WB_DMA_CTRL |
| philpem@0 | 237 | `endif // WB_DMA_CTRL_FILE |