Fri, 13 Aug 2010 10:43:05 +0100
Initial commit, DMAC version 3.1
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LM32 DMA Component
18 // File : wb_dma_ctrl.v
19 // Title : DMA controller top file
20 // Dependencies : None
21 // Version : 7.0
22 // : Initial Release
23 // Version : 7.0SP2, 3.0
24 // 1. Read and Write channel of DMA controller are working in parallel,
25 // due to that now as soon as FIFO is not empty write channel of the DMA
26 // controller start writing data to the slave.
27 // 2. Burst Size supported by DMA controller is increased to support bigger
28 // burst (from current value of 4 and 8 to 16 and 32). Now 4 different type
29 // of burst sizes are supported by the DMA controller 4, 8, 16 and 32.
30 // For this Burst Size field of the control register is increased to 2 bits.
31 // 3. Glitch is removed on the S_ACK_O signal.
32 // Version : 3.1
33 // : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec
34 // : which defines alignement of bytes in sub-word transfers.
35 // =============================================================================
37 `ifndef WB_DMA_CTRL_FILE
38 `define WB_DMA_CTRL_FILE
39 `include "system_conf.v"
40 module wb_dma_ctrl #(parameter LENGTH_WIDTH = 16,
41 parameter FIFO_IMPLEMENTATION = "EBR")
42 (
43 //master read port
44 MA_ADR_O, //32bits
45 MA_WE_O,
46 MA_SEL_O, //4bits
47 MA_STB_O,
48 MA_CYC_O,
49 MA_LOCK_O,
50 MA_CTI_O,
51 MA_BTE_O,
52 MA_DAT_I, //32bits
53 MA_DAT_O, //32bits
54 MA_ACK_I,
55 MA_ERR_I,
56 MA_RTY_I,
57 //master write port
58 MB_ADR_O, //32bits
59 MB_DAT_O, //32bits
60 MB_WE_O,
61 MB_SEL_O, //4bits
62 MB_STB_O,
63 MB_CYC_O,
64 MB_LOCK_O,
65 MB_CTI_O,
66 MB_BTE_O,
67 MB_DAT_I, //32bits
68 MB_ACK_I,
69 MB_ERR_I,
70 MB_RTY_I,
71 //slave port
72 S_ADR_I, //32bits
73 S_DAT_I, //32bits
74 S_WE_I,
75 S_STB_I,
76 S_CYC_I,
77 S_SEL_I,
78 S_LOCK_I,
79 S_CTI_I,
80 S_BTE_I,
81 S_DAT_O, //32bits
82 S_ACK_O,
83 S_ERR_O,
84 S_RTY_O,
85 S_INT_O,
86 //system clock and reset
87 CLK_I,
88 RST_I
89 );
90 //master read port
91 output [31:0] MA_ADR_O; //32bits
92 output MA_WE_O;
93 output [3:0] MA_SEL_O; //4bits
94 output MA_STB_O;
95 output MA_CYC_O;
96 output MA_LOCK_O;
97 output [2:0] MA_CTI_O;
98 output [1:0] MA_BTE_O;
99 output [31:0] MA_DAT_O; //32bits
100 input [31:0] MA_DAT_I; //32bits
101 input MA_ACK_I;
102 input MA_ERR_I;
103 input MA_RTY_I;
104 //master write port
105 output [31:0] MB_ADR_O; //32bits
106 output [31:0] MB_DAT_O; //32bits
107 output MB_WE_O;
108 output [3:0] MB_SEL_O; //4bits
109 output MB_STB_O;
110 output MB_CYC_O;
111 output [2:0] MB_CTI_O;
112 output MB_LOCK_O;
113 output [1:0] MB_BTE_O;
114 input [31:0] MB_DAT_I; //32bits
115 input MB_ACK_I;
116 input MB_ERR_I;
117 input MB_RTY_I;
118 //slave port
119 input [31:0] S_ADR_I; //32bits
120 input [31:0] S_DAT_I; //32bits
121 input S_WE_I;
122 input S_STB_I;
123 input S_CYC_I;
124 input [2:0] S_CTI_I;
125 input [1:0] S_BTE_I;
126 input [3:0] S_SEL_I;
127 input S_LOCK_I;
128 output [31:0] S_DAT_O; //32bits
129 output S_ACK_O;
130 output S_ERR_O;
131 output S_RTY_O;
132 output S_INT_O;
133 //system clock and reset
134 input CLK_I;
135 input RST_I;
137 wire [31:0] MA_DAT_O = 0;
138 wire [1:0] MA_BTE_O = 0;
139 wire MA_LOCK_O;
141 wire [1:0] MB_BTE_O = 0;
142 wire MB_LOCK_O;
144 wire S_ERR_O = 0;
145 wire S_RTY_O = 0;
147 wire [LENGTH_WIDTH-1:0] data_length;//read back data
148 wire [2:0] incr_unit;
149 wire [31:0] reg_00_data;
150 wire [31:0] reg_04_data;
151 wire [3:0] M_SEL_O;
153 //slave port:master write/read data to/from register file.
154 SLAVE_REG #(.LENGTH_WIDTH(LENGTH_WIDTH),
155 .FIFO_IMPLEMENTATION(FIFO_IMPLEMENTATION)) SLAVE_REG(
156 .S_ADR_I (S_ADR_I ),
157 .S_DAT_I (S_DAT_I ),
158 .S_WE_I (S_WE_I ),
159 .S_STB_I (S_STB_I ),
160 .S_CYC_I (S_CYC_I ),
161 .S_CTI_I (S_CTI_I ),
162 .S_DAT_O (S_DAT_O ),
163 .S_ACK_O (S_ACK_O ),
164 .S_INT_O (S_INT_O ),
165 //Master Addr
166 .M_SEL_O (M_SEL_O ),
167 // .MA_SEL_O (MA_SEL_O ),
168 // .MB_SEL_O (MB_SEL_O ),
169 //internal signals
170 .reg_start (reg_start ),
171 .reg_status (reg_status ),
172 .reg_interrupt (reg_interrupt ),
173 .reg_busy (reg_busy ),
174 .data_length (data_length ),
175 .reg_cntlg (reg_cntlg ),
176 .reg_bt2 (reg_bt2 ),
177 .reg_bt1 (reg_bt1 ),
178 .reg_bt0 (reg_bt0 ),
179 .reg_s_con (reg_s_con ),
180 .reg_d_con (reg_d_con ),
181 .incr_unit (incr_unit ),
182 .reg_00_data (reg_00_data ),
183 .reg_04_data (reg_04_data ),
184 //system clock and reset
185 .CLK_I (CLK_I ),
186 .RST_I (RST_I )
187 );
189 //Master control
190 MASTER_CTRL #(.LENGTH_WIDTH(LENGTH_WIDTH),
191 .FIFO_IMPLEMENTATION(FIFO_IMPLEMENTATION)) MASTER_CTRL(
192 //master read port
193 .MA_ADR_O (MA_ADR_O ),
194 .MA_SEL_O (MA_SEL_O ),
195 .MA_WE_O (MA_WE_O ),
196 .MA_STB_O (MA_STB_O ),
197 .MA_CYC_O (MA_CYC_O ),
198 .MA_CTI_O (MA_CTI_O ),
199 .MA_LOCK_O (MA_LOCK_O ),
200 .MA_DAT_I (MA_DAT_I ), //32bits
201 .MA_ACK_I (MA_ACK_I ),
202 .MA_ERR_I (MA_ERR_I ),
203 .MA_RTY_I (MA_RTY_I ),
204 //master write port
205 .MB_ADR_O (MB_ADR_O ),
206 .MB_SEL_O (MB_SEL_O ),
207 .MB_DAT_O (MB_DAT_O ), //32bits
208 .MB_WE_O (MB_WE_O ),
209 .MB_STB_O (MB_STB_O ),
210 .MB_CYC_O (MB_CYC_O ),
211 .MB_CTI_O (MB_CTI_O ),
212 .MB_LOCK_O (MB_LOCK_O ),
213 .MB_ACK_I (MB_ACK_I ),
214 .MB_ERR_I (MB_ERR_I ),
215 .MB_RTY_I (MB_RTY_I ),
216 //register interface
217 .M_SEL_O (M_SEL_O ),
218 .reg_start (reg_start ),
219 .reg_status (reg_status ),
220 .reg_interrupt (reg_interrupt ),
221 .reg_busy (reg_busy ),
222 .data_length (data_length ),
223 .reg_cntlg (reg_cntlg ),
224 .reg_bt2 (reg_bt2 ),
225 .reg_bt1 (reg_bt1 ),
226 .reg_bt0 (reg_bt0 ),
227 .reg_s_con (reg_s_con ),
228 .reg_d_con (reg_d_con ),
229 .incr_unit (incr_unit ),
230 .reg_00_data (reg_00_data ),
231 .reg_04_data (reg_04_data ),
232 //system clock and reset
233 .CLK_I (CLK_I ),
234 .RST_I (RST_I )
235 );
236 endmodule // WB_DMA_CTRL
237 `endif // WB_DMA_CTRL_FILE