Sat, 06 Aug 2011 01:48:48 +0100
Update to LM32 DMA v3.3
+// Version : 3.2
+// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and
+// : Read/Write Ports can be independently configured.
+// : 2. Support for "retry" on receipt of a WISHBONE RTY. This
+// : retry results in the current burst or classic cycle
+// : being issued again after a retry timeout.
+// : 3. Support for "error" on receipt of a WISHBONE ERR. This
+// : results in the current dma transfer being terminated
+// : and the error is updated within the STATUS CSR.
+// : 4. Support for burst size of 64.
+// :
+// Version : 3.3
+// : Support for MachXO2 added. The MachXO2 only has a FIFO
+// : with separate read/write clocks.
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 // ------------------------------------------------------------------
4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5 // ALL RIGHTS RESERVED
6 // ------------------------------------------------------------------
7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 //
10 // Permission:
11 //
12 // Lattice Semiconductor grants permission to use this code
13 // pursuant to the terms of the Lattice Semiconductor Corporation
14 // Open Source License Agreement.
15 //
16 // Disclaimer:
17 //
18 // Lattice Semiconductor provides no warranty regarding the use or
19 // functionality of this code. It is the user's responsibility to
20 // verify the user’s design for consistency and functionality through
21 // the use of formal verification methods.
22 //
23 // --------------------------------------------------------------------
24 //
25 // Lattice Semiconductor Corporation
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36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LM32 DMA Component
39 // File : wb_dma_ctrl.v
40 // Title : DMA controller top file
41 // Dependencies : None
42 // :
43 // Version : 7.0
44 // : Initial Release
45 // :
46 // Version : 7.0SP2, 3.0
47 // : 1. Read and Write channel of DMA controller are working in
48 // : parallel, due to that now as soon as FIFO is not empty
49 // : write channel of the DMA controller start writing data
50 // : to the slave.
51 // : 2. Burst Size supported by DMA controller is increased to
52 // : support bigger burst (from current value of 4 and 8 to
53 // : 16 and 32). Now 4 different type of burst sizes are
54 // : supported by the DMA controller 4, 8, 16 and 32. For
55 // : this Burst Size field of the control register is
56 // : increased to 2 bits.
57 // : 3. Glitch is removed on the S_ACK_O signal.
58 // :
59 // Version : 3.1
60 // : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec
61 // : which defines alignement of bytes in sub-word transfers.
62 // :
63 // Version : 3.2
64 // : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and
65 // : Read/Write Ports can be independently configured.
66 // : 2. Support for "retry" on receipt of a WISHBONE RTY. This
67 // : retry results in the current burst or classic cycle
68 // : being issued again after a retry timeout.
69 // : 3. Support for "error" on receipt of a WISHBONE ERR. This
70 // : results in the current dma transfer being terminated
71 // : and the error is updated within the STATUS CSR.
72 // : 4. Support for burst size of 64.
73 // =============================================================================
75 `ifndef WB_DMA_CTRL_FILE
76 `define WB_DMA_CTRL_FILE
77 `include "system_conf.v"
78 module wb_dma_ctrl
79 #(parameter S_WB_DAT_WIDTH = 32,
80 parameter S_WB_ADR_WIDTH = 32,
81 parameter MA_WB_DAT_WIDTH = 32,
82 parameter MA_WB_ADR_WIDTH = 32,
83 parameter MB_WB_DAT_WIDTH = 32,
84 parameter MB_WB_ADR_WIDTH = 32,
85 parameter RETRY_TIMEOUT = 16,
86 parameter FIFO_IMPLEMENTATION = "EBR")
87 (
88 // master read port
89 output [MA_WB_ADR_WIDTH-1:0] MA_ADR_O,
90 output MA_WE_O,
91 output [MA_WB_DAT_WIDTH/8-1:0] MA_SEL_O,
92 output MA_STB_O,
93 output MA_CYC_O,
94 output MA_LOCK_O,
95 output [2:0] MA_CTI_O,
96 output [1:0] MA_BTE_O,
97 output [MA_WB_DAT_WIDTH-1:0] MA_DAT_O,
98 input [MA_WB_DAT_WIDTH-1:0] MA_DAT_I,
99 input MA_ACK_I,
100 input MA_ERR_I,
101 input MA_RTY_I,
102 // master write port
103 output [MB_WB_ADR_WIDTH-1:0] MB_ADR_O,
104 output [MB_WB_DAT_WIDTH-1:0] MB_DAT_O,
105 output MB_WE_O,
106 output [MB_WB_DAT_WIDTH/8-1:0] MB_SEL_O,
107 output MB_STB_O,
108 output MB_CYC_O,
109 output MB_LOCK_O,
110 output [2:0] MB_CTI_O,
111 output [1:0] MB_BTE_O,
112 input [MB_WB_DAT_WIDTH-1:0] MB_DAT_I,
113 input MB_ACK_I,
114 input MB_ERR_I,
115 input MB_RTY_I,
116 // slave port
117 input [S_WB_ADR_WIDTH-1:0] S_ADR_I,
118 input [S_WB_DAT_WIDTH-1:0] S_DAT_I,
119 input S_WE_I,
120 input S_STB_I,
121 input S_CYC_I,
122 input [S_WB_DAT_WIDTH/8-1:0] S_SEL_I,
123 input S_LOCK_I,
124 input [2:0] S_CTI_I,
125 input [1:0] S_BTE_I,
126 output [S_WB_DAT_WIDTH-1:0] S_DAT_O,
127 output S_ACK_O,
128 output S_ERR_O,
129 output S_RTY_O,
130 output S_INT_O,
131 // system clock and reset
132 input CLK_I,
133 input RST_I
134 );
136 assign MA_BTE_O = 0;
137 assign MB_BTE_O = 0;
138 assign S_ERR_O = 0;
139 assign S_RTY_O = 0;
141 wire [31:0] reg_00_data;
142 wire [31:0] reg_04_data;
143 wire [31:0] reg_08_data;
144 wire [7:0] reg_rdelay;
146 // slave port:master write/read data to/from register file.
147 SLAVE_REG
148 #(.S_WB_DAT_WIDTH (S_WB_DAT_WIDTH),
149 .S_WB_ADR_WIDTH (S_WB_ADR_WIDTH),
150 .FIFO_IMPLEMENTATION (FIFO_IMPLEMENTATION)
151 )
152 SLAVE_REG
153 (
154 .S_ADR_I (S_ADR_I ),
155 .S_DAT_I (S_DAT_I ),
156 .S_SEL_I (S_SEL_I ),
157 .S_WE_I (S_WE_I ),
158 .S_STB_I (S_STB_I ),
159 .S_CYC_I (S_CYC_I ),
160 .S_CTI_I (S_CTI_I ),
161 .S_DAT_O (S_DAT_O ),
162 .S_ACK_O (S_ACK_O ),
163 .S_INT_O (S_INT_O ),
164 // internal signals
165 .reg_start (reg_start ),
166 .reg_status (reg_status ),
167 .reg_interrupt (reg_interrupt ),
168 .reg_busy (reg_busy ),
169 .reg_bt3 (reg_bt3 ),
170 .reg_bt2 (reg_bt2 ),
171 .reg_bt1 (reg_bt1 ),
172 .reg_bt0 (reg_bt0 ),
173 .reg_s_con (reg_s_con ),
174 .reg_d_con (reg_d_con ),
175 .reg_incw (reg_incw ),
176 .reg_inchw (reg_inchw ),
177 .reg_rdelay (reg_rdelay ),
178 .reg_00_data (reg_00_data ),
179 .reg_04_data (reg_04_data ),
180 .reg_08_data (reg_08_data ),
181 // system clock and reset
182 .CLK_I (CLK_I ),
183 .RST_I (RST_I )
184 );
186 // Master control
187 MASTER_CTRL
188 #(.MA_WB_DAT_WIDTH (MA_WB_DAT_WIDTH),
189 .MA_WB_ADR_WIDTH (MA_WB_ADR_WIDTH),
190 .MB_WB_DAT_WIDTH (MB_WB_DAT_WIDTH),
191 .MB_WB_ADR_WIDTH (MB_WB_ADR_WIDTH),
192 .S_WB_DAT_WIDTH (S_WB_DAT_WIDTH),
193 .FIFO_IMPLEMENTATION (FIFO_IMPLEMENTATION)
194 )
195 MASTER_CTRL
196 (
197 // master read port
198 .MA_ADR_O (MA_ADR_O ),
199 .MA_SEL_O (MA_SEL_O ),
200 .MA_DAT_O (MA_DAT_O ),
201 .MA_WE_O (MA_WE_O ),
202 .MA_STB_O (MA_STB_O ),
203 .MA_CYC_O (MA_CYC_O ),
204 .MA_CTI_O (MA_CTI_O ),
205 .MA_LOCK_O (MA_LOCK_O ),
206 .MA_DAT_I (MA_DAT_I ),
207 .MA_ACK_I (MA_ACK_I ),
208 .MA_ERR_I (MA_ERR_I ),
209 .MA_RTY_I (MA_RTY_I ),
210 // master write port
211 .MB_ADR_O (MB_ADR_O ),
212 .MB_SEL_O (MB_SEL_O ),
213 .MB_DAT_O (MB_DAT_O ),
214 .MB_WE_O (MB_WE_O ),
215 .MB_STB_O (MB_STB_O ),
216 .MB_CYC_O (MB_CYC_O ),
217 .MB_CTI_O (MB_CTI_O ),
218 .MB_LOCK_O (MB_LOCK_O ),
219 .MB_ACK_I (MB_ACK_I ),
220 .MB_ERR_I (MB_ERR_I ),
221 .MB_RTY_I (MB_RTY_I ),
222 // register interface
223 .reg_start (reg_start ),
224 .reg_busy (reg_busy ),
225 .reg_status (reg_status ),
226 .reg_interrupt (reg_interrupt ),
227 .reg_bt3 (reg_bt3 ),
228 .reg_bt2 (reg_bt2 ),
229 .reg_bt1 (reg_bt1 ),
230 .reg_bt0 (reg_bt0 ),
231 .reg_s_con (reg_s_con ),
232 .reg_d_con (reg_d_con ),
233 .reg_incw (reg_incw ),
234 .reg_inchw (reg_inchw ),
235 .reg_rdelay (reg_rdelay ),
236 .reg_00_data (reg_00_data ),
237 .reg_04_data (reg_04_data ),
238 .reg_08_data (reg_08_data ),
239 // system clock and reset
240 .CLK_I (CLK_I ),
241 .RST_I (RST_I )
242 );
244 endmodule // WB_DMA_CTRL
245 `endif // WB_DMA_CTRL_FILE