1.1 --- a/rtl/verilog/wb_dma_ctrl.v Fri Aug 13 10:43:05 2010 +0100 1.2 +++ b/rtl/verilog/wb_dma_ctrl.v Sat Aug 06 01:48:48 2011 +0100 1.3 @@ -1,237 +1,245 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 +// ================================================================== 1.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.15 +// ------------------------------------------------------------------ 1.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.17 +// ALL RIGHTS RESERVED 1.18 +// ------------------------------------------------------------------ 1.19 +// 1.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.21 +// 1.22 +// Permission: 1.23 +// 1.24 +// Lattice Semiconductor grants permission to use this code 1.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.26 +// Open Source License Agreement. 1.27 +// 1.28 +// Disclaimer: 1.29 // 1.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.33 -// U.S.A email: techsupport@latticesemi.com 1.34 -// =============================================================================/ 1.35 +// Lattice Semiconductor provides no warranty regarding the use or 1.36 +// functionality of this code. It is the user's responsibility to 1.37 +// verify the user’s design for consistency and functionality through 1.38 +// the use of formal verification methods. 1.39 +// 1.40 +// -------------------------------------------------------------------- 1.41 +// 1.42 +// Lattice Semiconductor Corporation 1.43 +// 5555 NE Moore Court 1.44 +// Hillsboro, OR 97214 1.45 +// U.S.A 1.46 +// 1.47 +// TEL: 1-800-Lattice (USA and Canada) 1.48 +// 503-286-8001 (other locations) 1.49 +// 1.50 +// web: http://www.latticesemi.com/ 1.51 +// email: techsupport@latticesemi.com 1.52 +// 1.53 +// -------------------------------------------------------------------- 1.54 // FILE DETAILS 1.55 // Project : LM32 DMA Component 1.56 // File : wb_dma_ctrl.v 1.57 // Title : DMA controller top file 1.58 // Dependencies : None 1.59 +// : 1.60 // Version : 7.0 1.61 // : Initial Release 1.62 +// : 1.63 // Version : 7.0SP2, 3.0 1.64 -// 1. Read and Write channel of DMA controller are working in parallel, 1.65 -// due to that now as soon as FIFO is not empty write channel of the DMA 1.66 -// controller start writing data to the slave. 1.67 -// 2. Burst Size supported by DMA controller is increased to support bigger 1.68 -// burst (from current value of 4 and 8 to 16 and 32). Now 4 different type 1.69 -// of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 1.70 -// For this Burst Size field of the control register is increased to 2 bits. 1.71 -// 3. Glitch is removed on the S_ACK_O signal. 1.72 +// : 1. Read and Write channel of DMA controller are working in 1.73 +// : parallel, due to that now as soon as FIFO is not empty 1.74 +// : write channel of the DMA controller start writing data 1.75 +// : to the slave. 1.76 +// : 2. Burst Size supported by DMA controller is increased to 1.77 +// : support bigger burst (from current value of 4 and 8 to 1.78 +// : 16 and 32). Now 4 different type of burst sizes are 1.79 +// : supported by the DMA controller 4, 8, 16 and 32. For 1.80 +// : this Burst Size field of the control register is 1.81 +// : increased to 2 bits. 1.82 +// : 3. Glitch is removed on the S_ACK_O signal. 1.83 +// : 1.84 // Version : 3.1 1.85 // : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec 1.86 // : which defines alignement of bytes in sub-word transfers. 1.87 +// : 1.88 +// Version : 3.2 1.89 +// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and 1.90 +// : Read/Write Ports can be independently configured. 1.91 +// : 2. Support for "retry" on receipt of a WISHBONE RTY. This 1.92 +// : retry results in the current burst or classic cycle 1.93 +// : being issued again after a retry timeout. 1.94 +// : 3. Support for "error" on receipt of a WISHBONE ERR. This 1.95 +// : results in the current dma transfer being terminated 1.96 +// : and the error is updated within the STATUS CSR. 1.97 +// : 4. Support for burst size of 64. 1.98 // ============================================================================= 1.99 1.100 `ifndef WB_DMA_CTRL_FILE 1.101 `define WB_DMA_CTRL_FILE 1.102 `include "system_conf.v" 1.103 -module wb_dma_ctrl #(parameter LENGTH_WIDTH = 16, 1.104 - parameter FIFO_IMPLEMENTATION = "EBR") 1.105 -( 1.106 - //master read port 1.107 - MA_ADR_O, //32bits 1.108 - MA_WE_O, 1.109 - MA_SEL_O, //4bits 1.110 - MA_STB_O, 1.111 - MA_CYC_O, 1.112 - MA_LOCK_O, 1.113 - MA_CTI_O, 1.114 - MA_BTE_O, 1.115 - MA_DAT_I, //32bits 1.116 - MA_DAT_O, //32bits 1.117 - MA_ACK_I, 1.118 - MA_ERR_I, 1.119 - MA_RTY_I, 1.120 - //master write port 1.121 - MB_ADR_O, //32bits 1.122 - MB_DAT_O, //32bits 1.123 - MB_WE_O, 1.124 - MB_SEL_O, //4bits 1.125 - MB_STB_O, 1.126 - MB_CYC_O, 1.127 - MB_LOCK_O, 1.128 - MB_CTI_O, 1.129 - MB_BTE_O, 1.130 - MB_DAT_I, //32bits 1.131 - MB_ACK_I, 1.132 - MB_ERR_I, 1.133 - MB_RTY_I, 1.134 - //slave port 1.135 - S_ADR_I, //32bits 1.136 - S_DAT_I, //32bits 1.137 - S_WE_I, 1.138 - S_STB_I, 1.139 - S_CYC_I, 1.140 - S_SEL_I, 1.141 - S_LOCK_I, 1.142 - S_CTI_I, 1.143 - S_BTE_I, 1.144 - S_DAT_O, //32bits 1.145 - S_ACK_O, 1.146 - S_ERR_O, 1.147 - S_RTY_O, 1.148 - S_INT_O, 1.149 - //system clock and reset 1.150 - CLK_I, 1.151 - RST_I 1.152 - ); 1.153 - //master read port 1.154 - output [31:0] MA_ADR_O; //32bits 1.155 - output MA_WE_O; 1.156 - output [3:0] MA_SEL_O; //4bits 1.157 - output MA_STB_O; 1.158 - output MA_CYC_O; 1.159 - output MA_LOCK_O; 1.160 - output [2:0] MA_CTI_O; 1.161 - output [1:0] MA_BTE_O; 1.162 - output [31:0] MA_DAT_O; //32bits 1.163 - input [31:0] MA_DAT_I; //32bits 1.164 - input MA_ACK_I; 1.165 - input MA_ERR_I; 1.166 - input MA_RTY_I; 1.167 - //master write port 1.168 - output [31:0] MB_ADR_O; //32bits 1.169 - output [31:0] MB_DAT_O; //32bits 1.170 - output MB_WE_O; 1.171 - output [3:0] MB_SEL_O; //4bits 1.172 - output MB_STB_O; 1.173 - output MB_CYC_O; 1.174 - output [2:0] MB_CTI_O; 1.175 - output MB_LOCK_O; 1.176 - output [1:0] MB_BTE_O; 1.177 - input [31:0] MB_DAT_I; //32bits 1.178 - input MB_ACK_I; 1.179 - input MB_ERR_I; 1.180 - input MB_RTY_I; 1.181 - //slave port 1.182 - input [31:0] S_ADR_I; //32bits 1.183 - input [31:0] S_DAT_I; //32bits 1.184 - input S_WE_I; 1.185 - input S_STB_I; 1.186 - input S_CYC_I; 1.187 - input [2:0] S_CTI_I; 1.188 - input [1:0] S_BTE_I; 1.189 - input [3:0] S_SEL_I; 1.190 - input S_LOCK_I; 1.191 - output [31:0] S_DAT_O; //32bits 1.192 - output S_ACK_O; 1.193 - output S_ERR_O; 1.194 - output S_RTY_O; 1.195 - output S_INT_O; 1.196 - //system clock and reset 1.197 - input CLK_I; 1.198 - input RST_I; 1.199 - 1.200 - wire [31:0] MA_DAT_O = 0; 1.201 - wire [1:0] MA_BTE_O = 0; 1.202 - wire MA_LOCK_O; 1.203 +module wb_dma_ctrl 1.204 + #(parameter S_WB_DAT_WIDTH = 32, 1.205 + parameter S_WB_ADR_WIDTH = 32, 1.206 + parameter MA_WB_DAT_WIDTH = 32, 1.207 + parameter MA_WB_ADR_WIDTH = 32, 1.208 + parameter MB_WB_DAT_WIDTH = 32, 1.209 + parameter MB_WB_ADR_WIDTH = 32, 1.210 + parameter RETRY_TIMEOUT = 16, 1.211 + parameter FIFO_IMPLEMENTATION = "EBR") 1.212 + ( 1.213 + // master read port 1.214 + output [MA_WB_ADR_WIDTH-1:0] MA_ADR_O, 1.215 + output MA_WE_O, 1.216 + output [MA_WB_DAT_WIDTH/8-1:0] MA_SEL_O, 1.217 + output MA_STB_O, 1.218 + output MA_CYC_O, 1.219 + output MA_LOCK_O, 1.220 + output [2:0] MA_CTI_O, 1.221 + output [1:0] MA_BTE_O, 1.222 + output [MA_WB_DAT_WIDTH-1:0] MA_DAT_O, 1.223 + input [MA_WB_DAT_WIDTH-1:0] MA_DAT_I, 1.224 + input MA_ACK_I, 1.225 + input MA_ERR_I, 1.226 + input MA_RTY_I, 1.227 + // master write port 1.228 + output [MB_WB_ADR_WIDTH-1:0] MB_ADR_O, 1.229 + output [MB_WB_DAT_WIDTH-1:0] MB_DAT_O, 1.230 + output MB_WE_O, 1.231 + output [MB_WB_DAT_WIDTH/8-1:0] MB_SEL_O, 1.232 + output MB_STB_O, 1.233 + output MB_CYC_O, 1.234 + output MB_LOCK_O, 1.235 + output [2:0] MB_CTI_O, 1.236 + output [1:0] MB_BTE_O, 1.237 + input [MB_WB_DAT_WIDTH-1:0] MB_DAT_I, 1.238 + input MB_ACK_I, 1.239 + input MB_ERR_I, 1.240 + input MB_RTY_I, 1.241 + // slave port 1.242 + input [S_WB_ADR_WIDTH-1:0] S_ADR_I, 1.243 + input [S_WB_DAT_WIDTH-1:0] S_DAT_I, 1.244 + input S_WE_I, 1.245 + input S_STB_I, 1.246 + input S_CYC_I, 1.247 + input [S_WB_DAT_WIDTH/8-1:0] S_SEL_I, 1.248 + input S_LOCK_I, 1.249 + input [2:0] S_CTI_I, 1.250 + input [1:0] S_BTE_I, 1.251 + output [S_WB_DAT_WIDTH-1:0] S_DAT_O, 1.252 + output S_ACK_O, 1.253 + output S_ERR_O, 1.254 + output S_RTY_O, 1.255 + output S_INT_O, 1.256 + // system clock and reset 1.257 + input CLK_I, 1.258 + input RST_I 1.259 + ); 1.260 + 1.261 + assign MA_BTE_O = 0; 1.262 + assign MB_BTE_O = 0; 1.263 + assign S_ERR_O = 0; 1.264 + assign S_RTY_O = 0; 1.265 + 1.266 + wire [31:0] reg_00_data; 1.267 + wire [31:0] reg_04_data; 1.268 + wire [31:0] reg_08_data; 1.269 + wire [7:0] reg_rdelay; 1.270 1.271 - wire [1:0] MB_BTE_O = 0; 1.272 - wire MB_LOCK_O; 1.273 - 1.274 - wire S_ERR_O = 0; 1.275 - wire S_RTY_O = 0; 1.276 - 1.277 - wire [LENGTH_WIDTH-1:0] data_length;//read back data 1.278 - wire [2:0] incr_unit; 1.279 - wire [31:0] reg_00_data; 1.280 - wire [31:0] reg_04_data; 1.281 - wire [3:0] M_SEL_O; 1.282 - 1.283 - //slave port:master write/read data to/from register file. 1.284 - SLAVE_REG #(.LENGTH_WIDTH(LENGTH_WIDTH), 1.285 - .FIFO_IMPLEMENTATION(FIFO_IMPLEMENTATION)) SLAVE_REG( 1.286 - .S_ADR_I (S_ADR_I ), 1.287 - .S_DAT_I (S_DAT_I ), 1.288 - .S_WE_I (S_WE_I ), 1.289 - .S_STB_I (S_STB_I ), 1.290 - .S_CYC_I (S_CYC_I ), 1.291 - .S_CTI_I (S_CTI_I ), 1.292 - .S_DAT_O (S_DAT_O ), 1.293 - .S_ACK_O (S_ACK_O ), 1.294 - .S_INT_O (S_INT_O ), 1.295 - //Master Addr 1.296 - .M_SEL_O (M_SEL_O ), 1.297 -// .MA_SEL_O (MA_SEL_O ), 1.298 -// .MB_SEL_O (MB_SEL_O ), 1.299 - //internal signals 1.300 - .reg_start (reg_start ), 1.301 - .reg_status (reg_status ), 1.302 - .reg_interrupt (reg_interrupt ), 1.303 - .reg_busy (reg_busy ), 1.304 - .data_length (data_length ), 1.305 - .reg_cntlg (reg_cntlg ), 1.306 - .reg_bt2 (reg_bt2 ), 1.307 - .reg_bt1 (reg_bt1 ), 1.308 - .reg_bt0 (reg_bt0 ), 1.309 - .reg_s_con (reg_s_con ), 1.310 - .reg_d_con (reg_d_con ), 1.311 - .incr_unit (incr_unit ), 1.312 - .reg_00_data (reg_00_data ), 1.313 - .reg_04_data (reg_04_data ), 1.314 - //system clock and reset 1.315 - .CLK_I (CLK_I ), 1.316 - .RST_I (RST_I ) 1.317 - ); 1.318 + // slave port:master write/read data to/from register file. 1.319 + SLAVE_REG 1.320 + #(.S_WB_DAT_WIDTH (S_WB_DAT_WIDTH), 1.321 + .S_WB_ADR_WIDTH (S_WB_ADR_WIDTH), 1.322 + .FIFO_IMPLEMENTATION (FIFO_IMPLEMENTATION) 1.323 + ) 1.324 + SLAVE_REG 1.325 + ( 1.326 + .S_ADR_I (S_ADR_I ), 1.327 + .S_DAT_I (S_DAT_I ), 1.328 + .S_SEL_I (S_SEL_I ), 1.329 + .S_WE_I (S_WE_I ), 1.330 + .S_STB_I (S_STB_I ), 1.331 + .S_CYC_I (S_CYC_I ), 1.332 + .S_CTI_I (S_CTI_I ), 1.333 + .S_DAT_O (S_DAT_O ), 1.334 + .S_ACK_O (S_ACK_O ), 1.335 + .S_INT_O (S_INT_O ), 1.336 + // internal signals 1.337 + .reg_start (reg_start ), 1.338 + .reg_status (reg_status ), 1.339 + .reg_interrupt (reg_interrupt ), 1.340 + .reg_busy (reg_busy ), 1.341 + .reg_bt3 (reg_bt3 ), 1.342 + .reg_bt2 (reg_bt2 ), 1.343 + .reg_bt1 (reg_bt1 ), 1.344 + .reg_bt0 (reg_bt0 ), 1.345 + .reg_s_con (reg_s_con ), 1.346 + .reg_d_con (reg_d_con ), 1.347 + .reg_incw (reg_incw ), 1.348 + .reg_inchw (reg_inchw ), 1.349 + .reg_rdelay (reg_rdelay ), 1.350 + .reg_00_data (reg_00_data ), 1.351 + .reg_04_data (reg_04_data ), 1.352 + .reg_08_data (reg_08_data ), 1.353 + // system clock and reset 1.354 + .CLK_I (CLK_I ), 1.355 + .RST_I (RST_I ) 1.356 + ); 1.357 1.358 - //Master control 1.359 - MASTER_CTRL #(.LENGTH_WIDTH(LENGTH_WIDTH), 1.360 - .FIFO_IMPLEMENTATION(FIFO_IMPLEMENTATION)) MASTER_CTRL( 1.361 - //master read port 1.362 - .MA_ADR_O (MA_ADR_O ), 1.363 - .MA_SEL_O (MA_SEL_O ), 1.364 - .MA_WE_O (MA_WE_O ), 1.365 - .MA_STB_O (MA_STB_O ), 1.366 - .MA_CYC_O (MA_CYC_O ), 1.367 - .MA_CTI_O (MA_CTI_O ), 1.368 - .MA_LOCK_O (MA_LOCK_O ), 1.369 - .MA_DAT_I (MA_DAT_I ), //32bits 1.370 - .MA_ACK_I (MA_ACK_I ), 1.371 - .MA_ERR_I (MA_ERR_I ), 1.372 - .MA_RTY_I (MA_RTY_I ), 1.373 - //master write port 1.374 - .MB_ADR_O (MB_ADR_O ), 1.375 - .MB_SEL_O (MB_SEL_O ), 1.376 - .MB_DAT_O (MB_DAT_O ), //32bits 1.377 - .MB_WE_O (MB_WE_O ), 1.378 - .MB_STB_O (MB_STB_O ), 1.379 - .MB_CYC_O (MB_CYC_O ), 1.380 - .MB_CTI_O (MB_CTI_O ), 1.381 - .MB_LOCK_O (MB_LOCK_O ), 1.382 - .MB_ACK_I (MB_ACK_I ), 1.383 - .MB_ERR_I (MB_ERR_I ), 1.384 - .MB_RTY_I (MB_RTY_I ), 1.385 - //register interface 1.386 - .M_SEL_O (M_SEL_O ), 1.387 - .reg_start (reg_start ), 1.388 - .reg_status (reg_status ), 1.389 - .reg_interrupt (reg_interrupt ), 1.390 - .reg_busy (reg_busy ), 1.391 - .data_length (data_length ), 1.392 - .reg_cntlg (reg_cntlg ), 1.393 - .reg_bt2 (reg_bt2 ), 1.394 - .reg_bt1 (reg_bt1 ), 1.395 - .reg_bt0 (reg_bt0 ), 1.396 - .reg_s_con (reg_s_con ), 1.397 - .reg_d_con (reg_d_con ), 1.398 - .incr_unit (incr_unit ), 1.399 - .reg_00_data (reg_00_data ), 1.400 - .reg_04_data (reg_04_data ), 1.401 - //system clock and reset 1.402 - .CLK_I (CLK_I ), 1.403 - .RST_I (RST_I ) 1.404 - ); 1.405 + // Master control 1.406 + MASTER_CTRL 1.407 + #(.MA_WB_DAT_WIDTH (MA_WB_DAT_WIDTH), 1.408 + .MA_WB_ADR_WIDTH (MA_WB_ADR_WIDTH), 1.409 + .MB_WB_DAT_WIDTH (MB_WB_DAT_WIDTH), 1.410 + .MB_WB_ADR_WIDTH (MB_WB_ADR_WIDTH), 1.411 + .S_WB_DAT_WIDTH (S_WB_DAT_WIDTH), 1.412 + .FIFO_IMPLEMENTATION (FIFO_IMPLEMENTATION) 1.413 + ) 1.414 + MASTER_CTRL 1.415 + ( 1.416 + // master read port 1.417 + .MA_ADR_O (MA_ADR_O ), 1.418 + .MA_SEL_O (MA_SEL_O ), 1.419 + .MA_DAT_O (MA_DAT_O ), 1.420 + .MA_WE_O (MA_WE_O ), 1.421 + .MA_STB_O (MA_STB_O ), 1.422 + .MA_CYC_O (MA_CYC_O ), 1.423 + .MA_CTI_O (MA_CTI_O ), 1.424 + .MA_LOCK_O (MA_LOCK_O ), 1.425 + .MA_DAT_I (MA_DAT_I ), 1.426 + .MA_ACK_I (MA_ACK_I ), 1.427 + .MA_ERR_I (MA_ERR_I ), 1.428 + .MA_RTY_I (MA_RTY_I ), 1.429 + // master write port 1.430 + .MB_ADR_O (MB_ADR_O ), 1.431 + .MB_SEL_O (MB_SEL_O ), 1.432 + .MB_DAT_O (MB_DAT_O ), 1.433 + .MB_WE_O (MB_WE_O ), 1.434 + .MB_STB_O (MB_STB_O ), 1.435 + .MB_CYC_O (MB_CYC_O ), 1.436 + .MB_CTI_O (MB_CTI_O ), 1.437 + .MB_LOCK_O (MB_LOCK_O ), 1.438 + .MB_ACK_I (MB_ACK_I ), 1.439 + .MB_ERR_I (MB_ERR_I ), 1.440 + .MB_RTY_I (MB_RTY_I ), 1.441 + // register interface 1.442 + .reg_start (reg_start ), 1.443 + .reg_busy (reg_busy ), 1.444 + .reg_status (reg_status ), 1.445 + .reg_interrupt (reg_interrupt ), 1.446 + .reg_bt3 (reg_bt3 ), 1.447 + .reg_bt2 (reg_bt2 ), 1.448 + .reg_bt1 (reg_bt1 ), 1.449 + .reg_bt0 (reg_bt0 ), 1.450 + .reg_s_con (reg_s_con ), 1.451 + .reg_d_con (reg_d_con ), 1.452 + .reg_incw (reg_incw ), 1.453 + .reg_inchw (reg_inchw ), 1.454 + .reg_rdelay (reg_rdelay ), 1.455 + .reg_00_data (reg_00_data ), 1.456 + .reg_04_data (reg_04_data ), 1.457 + .reg_08_data (reg_08_data ), 1.458 + // system clock and reset 1.459 + .CLK_I (CLK_I ), 1.460 + .RST_I (RST_I ) 1.461 + ); 1.462 + 1.463 endmodule // WB_DMA_CTRL 1.464 `endif // WB_DMA_CTRL_FILE