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<h1>LatticeMico DMA Controller &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<a title="View Data Sheet" href="dma.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Data Sheet');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>

<p>The LatticeMico direct memory access controller (DMA) provides a master 
 read port, a master write port, and a slave port to control data transmission. 
 </p>

<p class="whs2"><span style="font-style: italic;"><I>*If the 
 data sheet fails to open, see the note at the bottom of this page.</I></span></p>

<h2>Revision History </h2>

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<tr valign="top" class="whs6">
<td bgcolor="#DEE8F4" width="86px" class="whs7">
<p class=Table
	style="font-weight: bold;">Version</td>
<td bgcolor="#DEE8F4" width="504px" class="whs8">
<p class=Table
	style="font-weight: bold;">Description</td></tr>

<tr valign="top" class="whs6">
<td colspan="1" rowspan="1" width="86px" class="whs9">
<p class=Table
	style="font-weight: normal;">3.3</td>
<td colspan="1" rowspan="1" width="504px" class="whs10">
<p class=Table>Added software support for LatticeMico8.</td></tr>

<tr valign="top" class="whs6">
<td colspan="1" rowspan="1" width="86px" class="whs9">
<p class=Table
	style="font-weight: normal;">3.2 (8.1 SP1)</td>
<td colspan="1" rowspan="1" width="504px" class="whs10">
<p class=Table>The data busses on the three WISHBONE interfaces can be 
 configured to be 8 or 32 bits. Support added for handling WISHBONE RTY 
 (retry) for burst transfers. Support added for handling WISHBONE ERR (error). 
 Register map updated to support 8-bit and 32-bit WISHBONE data bus.</td></tr>

<tr valign="top" class="whs6">
<td colspan="1" rowspan="1" width="86px" class="whs9">
<p class=Table
	style="font-weight: normal;">3.1 (8.0)</td>
<td colspan="1" rowspan="1" width="504px" class="whs10">
<p class=Table>DMA Engine upgraded to comply with Rule 3.100 of Wishbone 
 Specifications, which deal with byte alignment for transfers that are 
 less than the width of Wishbone data bus.</td></tr>

<tr valign="top" class="whs6">
<td colspan="1" rowspan="1" width="86px" class="whs9">
<p class=Table
	style="font-weight: normal;"><span style="font-weight: normal;">3.0 
 (7.0 SP2)</span></td>
<td colspan="1" rowspan="1" width="504px" class="whs10">
<p class=Table>Because the read and write channel worked in parallel, the 
 write channel started writing data to the slave as soon as the FIFO is 
 not empty.</p>
<p class=Table>Increased burst size to support bigger bursts from a current 
 value of 4 and 8 to 16 and 32, respectively. DMA now supports four burst 
 sizes: 4, 8, 16, and 32. The Burst Size field of the control register 
 was increased to 2 bits.</p>
<p class=Table>A glitch was removed on the S_ACK_O signal.</td></tr>

<tr valign="top" class="whs6">
<td colspan="1" rowspan="1" width="86px" class="whs9">
<p class="whs11">1.0</td>
<td colspan="1" rowspan="1" width="504px" class="whs10">
<p class=Table>Initial release.</td></tr>
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&nbsp; 

<h2>Dialog Box Parameters</h2>

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<col>
<col>

<tr valign="top" class="whs13">
<td bgcolor="#DEE8F4" class="whs14">
<p class=Table
	style="font-weight: bold; margin-right: 2px;">Parameter</td>
<td bgcolor="#DEE8F4" class="whs15">
<p class=Table
	style="font-weight: bold;">Description</td></tr>

<tr valign="top" class="whs13">
<td colspan="1" rowspan="1" class="whs16">
<p class=Table
	style="margin-right: 2px;">Instance Name</td>
<td colspan="1" rowspan="1" class="whs17">
<p class=Table>Specifies the name of the DMA controller instance. Alphanumeric 
 values and underscores are supported. The default is dma.</td></tr>

<tr valign="top" class="whs13">
<td colspan="1" rowspan="1" class="whs16">
<p class=Table
	style="margin-right: 2px;">Base Address</td>
<td colspan="1" rowspan="1" class="whs17">
<p class=Table>Specifies the base address for accessing the internal registers. 
 The minimum boundary alignment is 0X80. Supported values are 0X80000000 
 to 0XFFFFFFFF. The default is 0X80000000.</td></tr>

<tr valign="top" class="whs13">
<td colspan="1" rowspan="1" class="whs18">
<p class=Table
	style="margin-right: 2px;">FIFO Implementation</td>
<td colspan="1" rowspan="1" class="whs19">
<p class=Table>Determines whether the FIFO is implemented as an EBR or 
 a LUT. The default is EBR.</td></tr>

<tr valign="top" class="whs13">
<td colspan="1" rowspan="1" class="whs18">
<p class=Table
	style="margin-right: 2px;">Retry Timeout</p>
<p class=table>&nbsp;</td>
<td colspan="1" rowspan="1" class="whs19">
<p class=Table>Specifies the number of WISHBONE clock cycles that the DMA 
 controller must wait after the source or destination asserts the WISHBONE 
 RTY before retrying the same WISHBONE cycle. &nbsp;Supported 
 values are 1 to 255. The default is 16. </p>
<p class=table>&nbsp;</td></tr>

<tr valign="top" class="whs13">
<td colspan="2" rowspan="1" class="whs18">
<p class=Table
	style="font-weight: bold;">WISHBONE Configuration</td>
</tr>

<tr valign="top" class="whs13">
<td colspan="1" rowspan="1" class="whs18">
<p class=Table>Control Port Data Bus Width</td>
<td colspan="1" rowspan="1" class="whs19">
<p class=Table>Configures the control port's WISHBONE data bus to be 8 
 or 32 bits wide.</td></tr>

<tr valign="top" class="whs13">
<td colspan="1" rowspan="1" class="whs18">
<p class=Table>Read/Write Port Data Bus Width</td>
<td colspan="1" rowspan="1" class="whs19">
<p class=Table>Configures the read and write WISHBONE master port data 
 buses to be 8 or 32 bits wide.</td></tr>
</table>

&nbsp; 

<p><span style="font-weight: bold;"><B>Note</B></span>: If the data sheet fails 
 to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs20"> on the Available Components toolbar, and 
 then click the note button.</p>

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