Sat, 06 Aug 2011 01:48:48 +0100
Update to LM32 DMA v3.3
+// Version : 3.2
+// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and
+// : Read/Write Ports can be independently configured.
+// : 2. Support for "retry" on receipt of a WISHBONE RTY. This
+// : retry results in the current burst or classic cycle
+// : being issued again after a retry timeout.
+// : 3. Support for "error" on receipt of a WISHBONE ERR. This
+// : results in the current dma transfer being terminated
+// : and the error is updated within the STATUS CSR.
+// : 4. Support for burst size of 64.
+// :
+// Version : 3.3
+// : Support for MachXO2 added. The MachXO2 only has a FIFO
+// : with separate read/write clocks.
| philpem@0 | 1 | #--------------------------------------------------------- |
| philpem@0 | 2 | # Identify source-paths for this device's driver-sources, |
| philpem@0 | 3 | # compiled when building the library |
| philpem@0 | 4 | #--------------------------------------------------------- |
| philpem@1 | 5 | LIBRARY_C_SRCS += |
| philpem@0 | 6 | LIBRARY_ASM_SRCS += |
| philpem@0 | 7 | |
| philpem@0 | 8 | |
| philpem@0 | 9 |