1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/drivers/device/MicoDMA.h Fri Aug 13 10:43:05 2010 +0100 1.3 @@ -0,0 +1,218 @@ 1.4 +/**************************************************************************** 1.5 +** 1.6 +** Name: MicoDMA.h 1.7 +** 1.8 +** Description: 1.9 +** Declares prototypes of functions for manipulating LatticeMico32 DMA 1.10 +** 1.11 +** Revision: 3.0 1.12 +** 1.13 +** Disclaimer: 1.14 +** 1.15 +** This source code is intended as a design reference which 1.16 +** illustrates how these types of functions can be implemented. It 1.17 +** is the user's responsibility to verify their design for 1.18 +** consistency and functionality through the use of formal 1.19 +** verification methods. Lattice Semiconductor provides no warranty 1.20 +** regarding the use or functionality of this code. 1.21 +** 1.22 +** -------------------------------------------------------------------- 1.23 +** 1.24 +** Lattice Semiconductor Corporation 1.25 +** 5555 NE Moore Court 1.26 +** Hillsboro, OR 97214 1.27 +** U.S.A 1.28 +** 1.29 +** TEL: 1-800-Lattice (USA and Canada) 1.30 +** (503)268-8001 (other locations) 1.31 +** 1.32 +** web: http://www.latticesemi.com 1.33 +** email: techsupport@latticesemi.com 1.34 +** 1.35 +** -------------------------------------------------------------------------- 1.36 +** 1.37 +** Change History (Latest changes on top) 1.38 +** 1.39 +** Ver Date Description 1.40 +** -------------------------------------------------------------------------- 1.41 +** 1.42 +** 3.0 Mar-25-2008 Added Header 1.43 +** 1.44 +**--------------------------------------------------------------------------- 1.45 +*****************************************************************************/ 1.46 + 1.47 +#ifndef MICODMA_H_ 1.48 +#define MICODMA_H_ 1.49 + 1.50 +#include "DDStructs.h" 1.51 + 1.52 +#ifdef __cplusplus 1.53 +extern "C" { 1.54 +#endif 1.55 + 1.56 +/*************************************************************** 1.57 + *************************************************************** 1.58 + * * 1.59 + * DMA PHYSICAL DEVICE SPECIFIC INFORMATION * 1.60 + * * 1.61 + *************************************************************** 1.62 + ***************************************************************/ 1.63 + 1.64 + /* 1.65 + ------------------------------------------------------ 1.66 + - DMA registers specific bit definitions used - 1.67 + - in the driver implementation - 1.68 + ------------------------------------------------------ 1.69 + */ 1.70 + /* CONTROL-REGISTER BIT-MASKS */ 1.71 + #define MICODMA_CONTROL_SADDR_CONSTANT (0x01) 1.72 + #define MICODMA_CONTROL_DADDR_CONSTANT (0x02) 1.73 + #define MICODMA_CONTROL_USHORT_TRANSFER (0x04) 1.74 + #define MICODMA_CONTROL_UINT_TRANSFER (0x08) 1.75 + #define MICODMA_CONTROL_BURST_SIZE (0x30) 1.76 + #define MICODMA_CONTROL_BURST_ENABLE (0x40) 1.77 + 1.78 + /* STATUS-REGISTER BIT-MASKS */ 1.79 + #define MICODMA_STATUS_BUSY (0x01) 1.80 + #define MICODMA_STATUS_IE (0x02) 1.81 + #define MICODMA_STATUS_SUCCESS (0x04) 1.82 + #define MICODMA_STATUS_START (0x08) 1.83 + 1.84 + 1.85 + /* DMA OPERATIONAL CODES (USED INTERNALLY) */ 1.86 + #define MICODMA_STATE_SUCCESS (0x00) 1.87 + #define MICODMA_STATE_PENDING (0x01) 1.88 + #define MICODMA_STATE_ACTIVE (0x02) 1.89 + #define MICODMA_STATE_ERROR (0x03) 1.90 + #define MICODMA_STATE_ABORTED (0x04) 1.91 + 1.92 + 1.93 + /* 1.94 + ------------------------------------------------------ 1.95 + - - 1.96 + - DMA Device Register-map - 1.97 + - - 1.98 + ------------------------------------------------------ 1.99 + */ 1.100 + typedef struct st_MicoDMA{ 1.101 + /* address to read data from */ 1.102 + volatile unsigned int sAddr; 1.103 + 1.104 + /* address to write data to */ 1.105 + volatile unsigned int dAddr; 1.106 + 1.107 + /* dma-length */ 1.108 + volatile unsigned int len; 1.109 + 1.110 + /* control register */ 1.111 + volatile unsigned int control; 1.112 + 1.113 + /* status register */ 1.114 + volatile unsigned int status; 1.115 + }MicoDMA_t; 1.116 + 1.117 + 1.118 + 1.119 +/*************************************************************** 1.120 + *************************************************************** 1.121 + * * 1.122 + * DMA SOFTWARE DRIVER SPECIFIC INFORMATION * 1.123 + * * 1.124 + *************************************************************** 1.125 + ***************************************************************/ 1.126 + 1.127 + /* DMA-TYPE QUALIFIERS */ 1.128 + /* DMA-type enumerator */ 1.129 + typedef enum e_DMAType_t{ 1.130 + DMA_CONSTANT_SRC_ADDR = 0x01, 1.131 + DMA_CONSTANT_DST_ADDR = 0x02, 1.132 + DMA_16BIT_TRANSFER = 0x04, 1.133 + DMA_32BIT_TRANSFER = 0x08, 1.134 + DMA_BURST_SIZE_4 = 0x40, 1.135 + DMA_BURST_SIZE_8 = 0x50, 1.136 + DMA_BURST_SIZE_16 = 0x60, 1.137 + DMA_BURST_SIZE_32 = 0x70, 1.138 + DMA_BURST_SIZE = DMA_BURST_SIZE_8, /* Legacy: replaced by BURST_SIZE_X above */ 1.139 + DMA_BURST_ENABLE = 0x40 /* Legacy: replaced by BURST_SIZE_X above */ 1.140 + 1.141 + }DMAType_t; 1.142 + 1.143 + 1.144 + typedef struct st_DMADesc_t DMADesc_t; 1.145 + 1.146 + /* DMA Completion callback type */ 1.147 + typedef void(*DMACallback_t)(DMADesc_t *desc, unsigned int status); 1.148 + 1.149 + 1.150 + /* DMA Descriptor that defines a DMA operation */ 1.151 + struct st_DMADesc_t{ 1.152 + /* address to read data from */ 1.153 + unsigned int sAddr; 1.154 + 1.155 + /* address to write data to */ 1.156 + unsigned int dAddr; 1.157 + 1.158 + /* length of transfer */ 1.159 + unsigned int length; 1.160 + 1.161 + /* DMA transfer-qualifier */ 1.162 + unsigned int type; 1.163 + 1.164 + /* User-provided private data */ 1.165 + void *priv; 1.166 + 1.167 + /* descriptor state */ 1.168 + unsigned int state; 1.169 + 1.170 + /* used internally by the driver: Stores byte-length */ 1.171 + unsigned int reserved; 1.172 + 1.173 + /* used internally for chaining descriptors */ 1.174 + DMACallback_t onCompletion; 1.175 + DMADesc_t *prev; 1.176 + DMADesc_t *next; 1.177 + }; 1.178 + 1.179 + 1.180 + 1.181 + /* 1.182 + ------------------------------------------------------ 1.183 + - - 1.184 + - FUNCTIONS - 1.185 + - - 1.186 + ------------------------------------------------------ 1.187 + */ 1.188 + 1.189 + 1.190 + /* well-known DMA specific return values */ 1.191 + #define MICODMA_ERR_INVALID_POINTERS (1) 1.192 + #define MICODMA_ERR_DESCRIPTOR_NOT_PENDING (2) 1.193 + #define MICODMA_ERR_DESC_LEN_ERR (3) 1.194 + 1.195 + 1.196 + /* initialization routine */ 1.197 + void MicoDMAInit(MicoDMACtx_t *ctx); 1.198 + 1.199 + /* queue a new descriptor */ 1.200 + unsigned int MicoDMAQueueRequest(MicoDMACtx_t *ctx, DMADesc_t *desc, DMACallback_t callback); 1.201 + 1.202 + /* dequeue an existing queued descriptor */ 1.203 + unsigned int MicoDMADequeueRequest(MicoDMACtx_t *ctx, DMADesc_t *desc, unsigned int callback); 1.204 + 1.205 + /* query status of a descriptor */ 1.206 + unsigned int MicoDMAGetState(DMADesc_t *desc); 1.207 + 1.208 + /* pause DMA operations (after completion of the currently active descr.) */ 1.209 + unsigned int MicoDMAPause(MicoDMACtx_t *ctx); 1.210 + 1.211 + /* resume DMA operations */ 1.212 + unsigned int MicoDMAResume(MicoDMACtx_t *ctx); 1.213 + 1.214 + 1.215 +#ifdef __cplusplus 1.216 +} 1.217 +#endif 1.218 + 1.219 + 1.220 +#endif /*MICODMA_H_*/ 1.221 +