1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/rtl/verilog/master_ctrl.v Fri Aug 13 10:43:05 2010 +0100 1.3 @@ -0,0 +1,1188 @@ 1.4 +// ============================================================================= 1.5 +// COPYRIGHT NOTICE 1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 +// ALL RIGHTS RESERVED 1.8 +// This confidential and proprietary software may be used only as authorised by 1.9 +// a licensing agreement from Lattice Semiconductor Corporation. 1.10 +// The entire notice above must be reproduced on all authorized copies and 1.11 +// copies may only be made to the extent permitted by a licensing agreement from 1.12 +// Lattice Semiconductor Corporation. 1.13 +// 1.14 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.15 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.16 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.17 +// U.S.A email: techsupport@latticesemi.com 1.18 +// =============================================================================/ 1.19 +// FILE DETAILS 1.20 +// Project : LM32 DMA Component 1.21 +// File : master_ctrl.v 1.22 +// Title : DMA Master controller 1.23 +// Dependencies : None 1.24 +// 1.25 +// Version 3.1 1.26 +// 1. Make DMA Engine compliant to Rule 3.100 of Wishbone Spec which defines 1.27 +// alignement of bytes in sub-word transfers. 1.28 +// 2. Removed glitch that did not pause the burst write when the read burst 1.29 +// was paused by the "read slave". 1.30 +// 1.31 +// Version 7.0SP2, 3.0 1.32 +// 1. Read and Write channel of DMA controller are working in parallel, 1.33 +// due to that now as soon as FIFO is not empty write channel of the DMA 1.34 +// controller start writing data to the slave. 1.35 +// 2. Burst Size supported by DMA controller is increased to support bigger 1.36 +// burst (from current value of 4 and 8 to 16 and 32). Now 4 different type 1.37 +// of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 1.38 +// For this Burst Size field of the control register is increased to 2 bits. 1.39 +// 3. Glitch is removed on the S_ACK_O signal. 1.40 +// 1.41 +// Version 7.0 1.42 +// 1. Initial Release 1.43 +// 1.44 +// ============================================================================= 1.45 + 1.46 +`ifndef MASTER_CTRL_FILE 1.47 + `define MASTER_CTRL_FILE 1.48 + `include "system_conf.v" 1.49 +module MASTER_CTRL 1.50 + #(parameter LENGTH_WIDTH = 16, 1.51 + parameter FIFO_IMPLEMENTATION = "EBR") 1.52 + ( 1.53 + //master read port 1.54 + MA_ADR_O, 1.55 + MA_SEL_O, 1.56 + MA_WE_O, 1.57 + MA_STB_O, 1.58 + MA_CYC_O, 1.59 + MA_CTI_O, 1.60 + MA_LOCK_O, 1.61 + MA_DAT_I, //32bits 1.62 + MA_ACK_I, 1.63 + MA_ERR_I, 1.64 + MA_RTY_I, 1.65 + //master write port 1.66 + MB_ADR_O, 1.67 + MB_SEL_O, 1.68 + MB_DAT_O, //32bits 1.69 + MB_WE_O, 1.70 + MB_STB_O, 1.71 + MB_CYC_O, 1.72 + MB_CTI_O, 1.73 + MB_LOCK_O, 1.74 + MB_ACK_I, 1.75 + MB_ERR_I, 1.76 + MB_RTY_I, 1.77 + //register interface 1.78 + M_SEL_O, 1.79 + reg_start, 1.80 + reg_status, 1.81 + reg_interrupt, 1.82 + reg_busy, 1.83 + data_length, 1.84 + reg_cntlg, 1.85 + reg_bt2,reg_bt1,reg_bt0, 1.86 + incr_unit, 1.87 + reg_s_con, 1.88 + reg_d_con, 1.89 + reg_00_data, 1.90 + reg_04_data, 1.91 + //system clock and reset 1.92 + CLK_I, 1.93 + RST_I 1.94 + ); 1.95 + //master read port 1.96 + output [31:0] MA_ADR_O; 1.97 + output [3:0] MA_SEL_O; 1.98 + output MA_WE_O; 1.99 + output MA_STB_O; 1.100 + output MA_CYC_O; 1.101 + output [2:0] MA_CTI_O; 1.102 + output MA_LOCK_O; 1.103 + input [31:0] MA_DAT_I; //32bits 1.104 + input MA_ACK_I; 1.105 + input MA_ERR_I; 1.106 + input MA_RTY_I; 1.107 + //master write port 1.108 + output [31:0] MB_ADR_O; 1.109 + output [3:0] MB_SEL_O; 1.110 + output [31:0] MB_DAT_O; //32bits 1.111 + output MB_WE_O; 1.112 + output MB_STB_O; 1.113 + output MB_CYC_O; 1.114 + output [2:0] MB_CTI_O; 1.115 + output MB_LOCK_O; 1.116 + input MB_ACK_I; 1.117 + input MB_ERR_I; 1.118 + input MB_RTY_I; 1.119 + 1.120 + //register interface 1.121 + input [3:0] M_SEL_O; 1.122 + input reg_start; 1.123 + output reg_status; 1.124 + output reg_interrupt; 1.125 + output reg_busy; 1.126 + input [LENGTH_WIDTH-1:0] data_length; 1.127 + output reg_cntlg; 1.128 + input reg_bt2,reg_bt1,reg_bt0; 1.129 + input [2:0] incr_unit; 1.130 + input reg_s_con; 1.131 + input reg_d_con; 1.132 + input [31:0] reg_00_data; 1.133 + input [31:0] reg_04_data; 1.134 + //system clock and reset 1.135 + input CLK_I; 1.136 + input RST_I; 1.137 + 1.138 + parameter lat_family = `LATTICE_FAMILY; 1.139 + parameter UDLY = 1; 1.140 + //Read FSM States encoding 1.141 + parameter ST_IDLE = 3'b000; 1.142 + parameter ST_READ = 3'b001; 1.143 + parameter ST_RDADDR = 3'b010; 1.144 + parameter ST_RDFIFO = 3'b011; 1.145 + parameter ST_WAIT_WRITE_FINISH = 3'b100; 1.146 + 1.147 + //Write FSM States encoding 1.148 + parameter ST_WRITE_IDLE = 4'b0000; 1.149 + parameter ST_WRITE = 4'b0001; 1.150 + parameter ST_WRADDR = 4'b0010; 1.151 + parameter ST_CNTLNGTH = 4'b0011; 1.152 + parameter ST_JUSTICE = 4'b0100; 1.153 + parameter ST_FIFO_EMPTY = 4'b0101; 1.154 + parameter ST_WRITE_WAIT = 4'b0110; 1.155 + parameter ST_FIFO_AEMPTY = 4'b1010; 1.156 + parameter ST_FIFO_RESUME = 4'b1000; 1.157 + 1.158 + // FSM for normal data transfer 1.159 + parameter ST_IDLE1 = 3'b000; 1.160 + parameter ST_READ1 = 3'b001; 1.161 + parameter ST_WRITE1 = 3'b010; 1.162 + parameter ST_RDADDR1 = 3'b011; 1.163 + parameter ST_WRADDR1 = 3'b100; 1.164 + parameter ST_CNTLNGTH1 = 3'b101; 1.165 + parameter ST_JUSTICE1 = 3'b110; 1.166 + parameter ST_RDFIFO1 = 3'b111; 1.167 + reg [2:0] status; 1.168 + reg var_length; 1.169 + 1.170 + 1.171 + //fifo status 1.172 + 1.173 + reg [2:0] status1; 1.174 + reg [3:0] status2; 1.175 + reg var_length2; 1.176 + reg var_length1; 1.177 + reg MA_STB_O; 1.178 + reg MB_STB_O; 1.179 + reg MA_CYC_O; 1.180 + reg MB_CYC_O; 1.181 + reg [2:0] MA_CTI_O; 1.182 + reg [2:0] MB_CTI_O; 1.183 + wire MA_WE_O = 1'b0; 1.184 + wire MB_WE_O = 1'b1; 1.185 + reg [31:0] MA_ADR_O; 1.186 + reg [31:0] MB_ADR_O; 1.187 + reg [3:0] MA_SEL_O; 1.188 + reg [3:0] MB_SEL_O; 1.189 + wire MA_LOCK_O = 0; //reg_bt2 ? (status1 == ST_READ) && (!(MA_CTI_O == 3'h7)) : 1'b0; 1.190 + wire MB_LOCK_O = 0; //reg_bt2 ? (status2 == ST_WRITE) && (!(MB_CTI_O == 3'h7)) : 1'b0; 1.191 + 1.192 + wire reg_busy = reg_bt2 ? !(status1 == ST_IDLE) : !(status == ST_IDLE1); 1.193 + wire reg_interrupt; 1.194 + wire reg_status; 1.195 + 1.196 + wire reg_cntlg; 1.197 + reg start_flag; 1.198 + reg [5:0] burst_size; 1.199 + reg [5:0] burst_cnt; 1.200 + reg fifo_wr; 1.201 + reg fifo_rd; 1.202 + reg [31:0] fifo_din; 1.203 + wire [31:0] fifo_dout; 1.204 + wire fifo_empty; 1.205 + wire fifo_aempty; 1.206 + reg fifo_clear; 1.207 + reg [31:0] first_data; 1.208 + reg first_data_flag; 1.209 + wire [31:0] MB_DAT_O = first_data_flag ? first_data : fifo_dout; 1.210 + reg latch_start; 1.211 + 1.212 + reg reg_status1, reg_status2; 1.213 + reg reg_interrupt1, reg_interrupt2; 1.214 + reg end_of_transfer; 1.215 + reg burst_completed; 1.216 + reg donot_start_again; 1.217 + reg [5:0] burst_size2; 1.218 + reg [5:0] burst_cnt2; 1.219 + 1.220 + reg reg_cntlg_burst, reg_cntlg_normal; 1.221 + reg reg_status_normal, reg_interrupt_normal; 1.222 + reg direct_data; 1.223 + 1.224 + always @(posedge CLK_I or posedge RST_I) 1.225 + if(RST_I) 1.226 + begin 1.227 + first_data <= #UDLY 'h0; 1.228 + first_data_flag <= #UDLY 1'b0; 1.229 + end 1.230 + else if((start_flag || direct_data) & !reg_bt2 & MA_ACK_I) 1.231 + begin 1.232 + first_data <= #UDLY MA_DAT_I; 1.233 + first_data_flag <= #UDLY 1'b1; 1.234 + end 1.235 + else if(first_data_flag & MB_ACK_I) 1.236 + begin 1.237 + first_data_flag <= #UDLY 1'b0; 1.238 + end 1.239 + 1.240 + assign reg_status = reg_bt2 ? (reg_status1 | reg_status2) : reg_status_normal; 1.241 + assign reg_interrupt = reg_bt2 ? (reg_interrupt1 | reg_interrupt2) : reg_interrupt_normal; 1.242 + assign reg_cntlg = reg_bt2 ? reg_cntlg_burst : reg_cntlg_normal; 1.243 + 1.244 + 1.245 + //FSM 1.246 + always @(posedge CLK_I or posedge RST_I) 1.247 + if(RST_I) 1.248 + begin 1.249 + status1 <= #UDLY ST_IDLE; 1.250 + var_length1 <= #UDLY 1'b0; 1.251 + MA_ADR_O <= #UDLY 32'h0; 1.252 + MA_SEL_O <= #UDLY 4'b1111; 1.253 + MA_CYC_O <= #UDLY 1'b0; 1.254 + MA_CTI_O <= #UDLY 3'h0; 1.255 + MA_STB_O <= #UDLY 1'b0; 1.256 + reg_status1 <= #UDLY 1'b0; 1.257 + reg_interrupt1 <= #UDLY 1'b0; 1.258 + start_flag <= #UDLY 1'b0; 1.259 + burst_size <= #UDLY 5'h0; 1.260 + burst_cnt <= #UDLY 5'h0; 1.261 + fifo_clear <= #UDLY 1'b0; 1.262 + latch_start <= #UDLY 1'b0; 1.263 + fifo_wr <= #UDLY 1'b0; 1.264 + 1.265 + status2 <= #UDLY ST_WRITE_IDLE; 1.266 + MB_ADR_O <= #UDLY 32'h0; 1.267 + MB_SEL_O <= #UDLY 4'b1111; 1.268 + MB_CYC_O <= #UDLY 1'b0; 1.269 + MB_CTI_O <= #UDLY 3'h0; 1.270 + MB_STB_O <= #UDLY 1'b0; 1.271 + reg_status2 <= #UDLY 1'b0; 1.272 + reg_interrupt2 <= #UDLY 1'b0; 1.273 + reg_cntlg_burst <= #UDLY 1'b0; 1.274 + burst_size2 <= #UDLY 5'h0; 1.275 + burst_cnt2 <= #UDLY 5'h0; 1.276 + fifo_rd <= #UDLY 1'b0; 1.277 + end_of_transfer <= #UDLY 1'b0; 1.278 + var_length2 <= #UDLY 1'b0; 1.279 + burst_completed <= #UDLY 1'b0; 1.280 + donot_start_again <= #UDLY 1'b0; 1.281 + 1.282 + status <= #UDLY ST_IDLE1; 1.283 + var_length <= #UDLY 1'b0; 1.284 + reg_status_normal <= #UDLY 1'b0; 1.285 + reg_interrupt_normal <= #UDLY 1'b0; 1.286 + reg_cntlg_normal <= #UDLY 1'b0; 1.287 + direct_data <= #UDLY 1'b0; 1.288 + end 1.289 + else 1.290 + begin 1.291 + if (reg_bt2) begin 1.292 + // Read Burst 1.293 + if ((MB_RTY_I && (!(|data_length))) || (MB_ERR_I && (status2 == ST_WRITE))) 1.294 + begin 1.295 + status1 <= #UDLY ST_IDLE; 1.296 + end 1.297 + else 1.298 + begin 1.299 + case(status1) 1.300 + ST_IDLE: 1.301 + begin 1.302 + if(fifo_wr) 1.303 + fifo_wr <= #UDLY 1'b0; 1.304 + if(MA_ACK_I) 1.305 + begin 1.306 + MA_CYC_O <= #UDLY 1'b0; 1.307 + MA_STB_O <= #UDLY 1'b0; 1.308 + MA_CTI_O <= #UDLY 3'h0; 1.309 + end 1.310 + if(reg_start | latch_start) 1.311 + begin 1.312 + if(fifo_empty) 1.313 + begin 1.314 + if(latch_start) 1.315 + latch_start <= #UDLY 1'b0; 1.316 + status1 <= #UDLY ST_READ; 1.317 + MA_CYC_O <= #UDLY 1'b1; 1.318 + MA_STB_O <= #UDLY 1'b1; 1.319 + MA_ADR_O <= #UDLY reg_00_data; 1.320 + case (reg_00_data[1:0]) 1.321 + 2'b01: MA_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 1.322 + 2'b10: MA_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 1.323 + 2'b11: MA_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 1.324 + default: 1.325 + MA_SEL_O <= #UDLY M_SEL_O; 1.326 + endcase 1.327 + set_cti_a; 1.328 + start_flag <= #UDLY 1'b1; 1.329 + if(!(|data_length)) 1.330 + var_length1 <= #UDLY 1'b1; 1.331 + else 1.332 + var_length1 <= #UDLY 1'b0; 1.333 + burst_size <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.334 + burst_cnt <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.335 + end 1.336 + else 1.337 + status1 <= #UDLY ST_RDFIFO; 1.338 + end 1.339 + else 1.340 + status1 <= #UDLY ST_IDLE; 1.341 + reg_interrupt1 <= #UDLY 1'b0; 1.342 + end 1.343 + 1.344 + ST_WAIT_WRITE_FINISH: 1.345 + begin 1.346 + fifo_wr <= #UDLY 1'b0; 1.347 + if (status2 == ST_WRITE) 1.348 + start_flag <= #UDLY 1'b0; 1.349 + if(end_of_transfer) 1.350 + begin 1.351 + if(!reg_s_con) 1.352 + MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.353 + if (incr_unit == 3'b001) 1.354 + MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.355 + else 1.356 + if (incr_unit == 3'b010) 1.357 + MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.358 + 1.359 + status1 <= #UDLY ST_RDADDR; 1.360 + burst_cnt <= #UDLY burst_size; 1.361 + end 1.362 + else 1.363 + begin 1.364 + if(burst_completed) 1.365 + status1 <= #UDLY ST_IDLE; 1.366 + end 1.367 + end 1.368 + 1.369 + ST_RDFIFO: 1.370 + begin 1.371 + if(fifo_empty) 1.372 + begin 1.373 + status1 <= #UDLY ST_IDLE; 1.374 + fifo_clear <= #UDLY 1'b0; 1.375 + latch_start <= #UDLY 1'b1; 1.376 + end 1.377 + else 1.378 + fifo_clear <= #UDLY !fifo_clear; 1.379 + end 1.380 + 1.381 + ST_RDADDR: 1.382 + begin 1.383 + MA_CYC_O <= #UDLY 1'b1; 1.384 + MA_STB_O <= #UDLY 1'b1; 1.385 + set_cti_a; 1.386 + status1 <= #UDLY ST_READ; 1.387 + end 1.388 + 1.389 + ST_READ: 1.390 + begin 1.391 + write_fifo; 1.392 + if(MA_ACK_I) 1.393 + begin 1.394 + if(start_flag) 1.395 + begin 1.396 + if(burst_cnt == 0) 1.397 + begin 1.398 + MA_CYC_O <= #UDLY 1'b0; 1.399 + MA_STB_O <= #UDLY 1'b0; 1.400 + MA_CTI_O <= #UDLY 3'h0; 1.401 + status1 <= #UDLY ST_WAIT_WRITE_FINISH; 1.402 + end 1.403 + else 1.404 + begin 1.405 + if(burst_cnt == 1) 1.406 + MA_CTI_O <= #UDLY 3'h7; 1.407 + burst_cnt <= #UDLY burst_cnt - 1; 1.408 + if(!reg_s_con) 1.409 + MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.410 + if (incr_unit == 3'b001) 1.411 + MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.412 + else 1.413 + if (incr_unit == 3'b010) 1.414 + MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.415 + end 1.416 + end 1.417 + else 1.418 + begin 1.419 + if(burst_cnt == 0) 1.420 + begin 1.421 + MA_CYC_O <= #UDLY 1'b0; 1.422 + MA_STB_O <= #UDLY 1'b0; 1.423 + MA_CTI_O <= #UDLY 3'h0; 1.424 + status1 <= #UDLY ST_WAIT_WRITE_FINISH; 1.425 + end 1.426 + else 1.427 + begin 1.428 + if(burst_cnt == 1) 1.429 + MA_CTI_O <= #UDLY 3'h7; 1.430 + if(!reg_s_con) 1.431 + MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.432 + if (incr_unit == 3'b001) 1.433 + MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.434 + else 1.435 + if (incr_unit == 3'b010) 1.436 + MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.437 + burst_cnt <= #UDLY burst_cnt - 1; 1.438 + end 1.439 + end 1.440 + end 1.441 + else if(MA_RTY_I) 1.442 + begin 1.443 + if(var_length1) 1.444 + begin 1.445 + MA_CYC_O <= #UDLY 1'b0; 1.446 + MA_STB_O <= #UDLY 1'b0; 1.447 + MA_CTI_O <= #UDLY 3'h0; 1.448 + status1 <= #UDLY ST_IDLE; 1.449 + reg_status1 <= #UDLY 1'b0; 1.450 + reg_interrupt1 <= #UDLY 1'b1; 1.451 + start_flag <= #UDLY 1'b0; 1.452 + end 1.453 + end 1.454 + else if(MA_ERR_I) 1.455 + begin 1.456 + MA_CYC_O <= #UDLY 1'b0; 1.457 + MA_STB_O <= #UDLY 1'b0; 1.458 + MA_CTI_O <= #UDLY 3'h0; 1.459 + status1 <= #UDLY ST_IDLE; 1.460 + reg_status1 <= #UDLY 1'b1; 1.461 + reg_interrupt1 <= #UDLY 1'b1; 1.462 + start_flag <= #UDLY 1'b0; 1.463 + end 1.464 + end 1.465 + 1.466 + default: 1.467 + begin 1.468 + status1 <= #UDLY ST_IDLE; 1.469 + var_length1 <= #UDLY 1'b0; 1.470 + MA_ADR_O <= #UDLY 32'h0; 1.471 + MA_SEL_O <= #UDLY 4'b1111; 1.472 + MA_CYC_O <= #UDLY 1'b0; 1.473 + MA_CTI_O <= #UDLY 3'h0; 1.474 + MA_STB_O <= #UDLY 1'b0; 1.475 + reg_status1 <= #UDLY 1'b0; 1.476 + reg_interrupt1 <= #UDLY 1'b0; 1.477 + start_flag <= #UDLY 1'b0; 1.478 + burst_size <= #UDLY 5'h0; 1.479 + burst_cnt <= #UDLY 5'h0; 1.480 + fifo_clear <= #UDLY 1'b0; 1.481 + latch_start <= #UDLY 1'b0; 1.482 + fifo_wr <= #UDLY 1'b0; 1.483 + end 1.484 + endcase 1.485 + end 1.486 + // Write Burst 1.487 + if ((MA_RTY_I && (!(|data_length))) || (MA_ERR_I && (status1 == ST_READ))) 1.488 + begin 1.489 + status2 <= #UDLY ST_WRITE_IDLE; 1.490 + donot_start_again <= #UDLY 1'b1; 1.491 + end 1.492 + else 1.493 + begin 1.494 + case(status2) 1.495 + ST_WRITE_IDLE: 1.496 + begin 1.497 + if(reg_start) 1.498 + begin 1.499 + MB_ADR_O <= #UDLY reg_04_data; 1.500 + case (reg_04_data[1:0]) 1.501 + 2'b01: MB_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 1.502 + 2'b10: MB_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 1.503 + 2'b11: MB_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 1.504 + default: 1.505 + MB_SEL_O <= #UDLY M_SEL_O; 1.506 + endcase 1.507 + if(!(|data_length)) 1.508 + var_length2 <= #UDLY 1'b1; 1.509 + else 1.510 + var_length2 <= #UDLY 1'b0; 1.511 + burst_size2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.512 + burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.513 + if(!fifo_empty) 1.514 + status2 <= #UDLY ST_FIFO_EMPTY; 1.515 + else 1.516 + donot_start_again <= #UDLY 1'b0; 1.517 + end 1.518 + if(fifo_empty) 1.519 + begin 1.520 + if(MB_ACK_I) 1.521 + begin 1.522 + MB_CYC_O <= #UDLY 1'b0; 1.523 + MB_STB_O <= #UDLY 1'b0; 1.524 + MB_CTI_O <= #UDLY 3'h0; 1.525 + fifo_rd <= #UDLY 1'b0; 1.526 + end 1.527 + burst_cnt2 <= #UDLY 5'h0; 1.528 + end 1.529 + else 1.530 + begin 1.531 + if(donot_start_again) 1.532 + begin 1.533 + if(MB_ACK_I) 1.534 + begin 1.535 + if(!reg_d_con) 1.536 + MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.537 + if (incr_unit == 3'b001) 1.538 + MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.539 + else 1.540 + if (incr_unit == 3'b010) 1.541 + MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.542 + end 1.543 + end 1.544 + end 1.545 + 1.546 + if(!fifo_empty && !donot_start_again) 1.547 + begin 1.548 + if(start_flag) 1.549 + begin 1.550 + set_cti_b; 1.551 + status2 <= #UDLY ST_WRITE_WAIT; 1.552 + read_fifo; 1.553 + burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.554 + end 1.555 + else 1.556 + begin 1.557 + if(!reg_d_con) 1.558 + MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.559 + if (incr_unit == 3'b001) 1.560 + MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.561 + else 1.562 + if (incr_unit == 3'b010) 1.563 + MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.564 + status2 <= #UDLY ST_WRADDR; 1.565 + read_fifo; 1.566 + burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.567 + end 1.568 + end 1.569 + end_of_transfer <= #UDLY 1'b0; 1.570 + burst_completed <= #UDLY 1'b0; 1.571 + reg_interrupt2 <= #UDLY 1'b0; 1.572 + end 1.573 + 1.574 + ST_FIFO_EMPTY: 1.575 + begin 1.576 + if(fifo_empty) 1.577 + begin 1.578 + status2 <= #UDLY ST_WRITE_IDLE; 1.579 + donot_start_again <= #UDLY 1'b0; 1.580 + end 1.581 + end 1.582 + 1.583 + ST_WRADDR: 1.584 + begin 1.585 + burst_cnt2 <= #UDLY burst_size2; 1.586 + MB_CYC_O <= #UDLY 1'b1; 1.587 + MB_STB_O <= #UDLY 1'b1; 1.588 + 1.589 + if (fifo_aempty && (burst_size2 > 5'h2)) 1.590 + begin 1.591 + MB_CTI_O <= #UDLY 3'b000; 1.592 + status2 <= #UDLY ST_FIFO_AEMPTY; 1.593 + fifo_rd <= #UDLY 1'b0; 1.594 + end 1.595 + else 1.596 + begin 1.597 + set_cti_b; 1.598 + status2 <= #UDLY ST_WRITE; 1.599 + end 1.600 + end 1.601 + 1.602 + ST_WRITE_WAIT: 1.603 + begin 1.604 + MB_CYC_O <= #UDLY 1'b1; 1.605 + MB_STB_O <= #UDLY 1'b1; 1.606 + 1.607 + if (fifo_aempty && (burst_size2 > 5'h2)) 1.608 + begin 1.609 + MB_CTI_O <= #UDLY 3'b000; 1.610 + status2 <= #UDLY ST_FIFO_AEMPTY; 1.611 + fifo_rd <= #UDLY 1'b0; 1.612 + end 1.613 + else 1.614 + begin 1.615 + set_cti_b; 1.616 + status2 <= #UDLY ST_WRITE; 1.617 + end 1.618 + end 1.619 + 1.620 + ST_FIFO_AEMPTY: 1.621 + begin 1.622 + if (MB_ACK_I) 1.623 + begin 1.624 + MB_CYC_O <= #UDLY 1'b0; 1.625 + MB_STB_O <= #UDLY 1'b0; 1.626 + 1.627 + burst_cnt2 <= #UDLY burst_cnt2 - 1; 1.628 + 1.629 + if (!reg_d_con) 1.630 + MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.631 + 1.632 + if (incr_unit == 3'b001) 1.633 + MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.634 + else 1.635 + if (incr_unit == 3'b010) 1.636 + MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.637 + end 1.638 + 1.639 + if (!MB_CYC_O && !fifo_aempty) 1.640 + begin 1.641 + status2 <= #UDLY ST_FIFO_RESUME; 1.642 + read_fifo; 1.643 + end 1.644 + end 1.645 + 1.646 + ST_FIFO_RESUME: 1.647 + begin 1.648 + MB_CYC_O <= #UDLY 1'b1; 1.649 + MB_STB_O <= #UDLY 1'b1; 1.650 + 1.651 + if (fifo_aempty && (burst_cnt2 > 5'h2)) 1.652 + begin 1.653 + MB_CTI_O <= #UDLY 3'b000; 1.654 + status2 <= #UDLY ST_FIFO_AEMPTY; 1.655 + fifo_rd <= #UDLY 1'b0; 1.656 + end 1.657 + else 1.658 + begin 1.659 + set_cti_b; 1.660 + status2 <= #UDLY ST_WRITE; 1.661 + end 1.662 + end 1.663 + 1.664 + ST_WRITE: 1.665 + begin 1.666 + if (MB_ACK_I) 1.667 + begin 1.668 + if(var_length2) 1.669 + begin 1.670 + if(burst_cnt2 == 0) 1.671 + begin 1.672 + MB_CYC_O <= #UDLY 1'b0; 1.673 + MB_STB_O <= #UDLY 1'b0; 1.674 + MB_CTI_O <= #UDLY 3'h0; 1.675 + end_of_transfer <= #UDLY 1'b1; 1.676 + status2 <= #UDLY ST_WRITE_IDLE; 1.677 + fifo_rd <= #UDLY 1'b0; 1.678 + burst_cnt2 <= #UDLY burst_size2; 1.679 + end 1.680 + else 1.681 + begin 1.682 + if(burst_cnt2 == 1) 1.683 + MB_CTI_O <= #UDLY 3'h7; 1.684 + else 1.685 + set_cti_b; 1.686 + if(!reg_d_con) 1.687 + MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.688 + if (incr_unit == 3'b001) 1.689 + MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.690 + else 1.691 + if (incr_unit == 3'b010) 1.692 + MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.693 + read_fifo; 1.694 + burst_cnt2 <= #UDLY burst_cnt2 - 1; 1.695 + end 1.696 + end 1.697 + else 1.698 + begin 1.699 + if(burst_cnt2 == 0) 1.700 + begin 1.701 + MB_CYC_O <= #UDLY 1'b0; 1.702 + MB_STB_O <= #UDLY 1'b0; 1.703 + MB_CTI_O <= #UDLY 3'h0; 1.704 + reg_cntlg_burst <= #UDLY 1'b1; 1.705 + status2 <= #UDLY ST_CNTLNGTH; 1.706 + fifo_rd <= #UDLY 1'b0; 1.707 + burst_cnt2 <= #UDLY burst_size2; 1.708 + end 1.709 + else 1.710 + begin 1.711 + if ((fifo_aempty && (burst_cnt2 > 5'h2)) || (burst_cnt2 == 5'h1)) 1.712 + MB_CTI_O <= #UDLY 3'h7; 1.713 + else 1.714 + set_cti_b; 1.715 + 1.716 + burst_cnt2 <= #UDLY burst_cnt2 - 1; 1.717 + 1.718 + if(!reg_d_con) 1.719 + MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.720 + 1.721 + if (incr_unit == 3'b001) 1.722 + MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.723 + else 1.724 + if (incr_unit == 3'b010) 1.725 + MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.726 + 1.727 + if (fifo_aempty && (burst_cnt2 > 5'h2)) 1.728 + begin 1.729 + status2 <= #UDLY ST_FIFO_AEMPTY; 1.730 + fifo_rd <= 1'b0; 1.731 + end 1.732 + else 1.733 + read_fifo; 1.734 + end 1.735 + end 1.736 + end 1.737 + 1.738 + else if(MB_RTY_I) 1.739 + begin 1.740 + if(var_length2) 1.741 + begin 1.742 + MB_CYC_O <= #UDLY 1'b0; 1.743 + MB_STB_O <= #UDLY 1'b0; 1.744 + MB_CTI_O <= #UDLY 3'h0; 1.745 + status2 <= #UDLY ST_WRITE_IDLE; 1.746 + reg_status2 <= #UDLY 1'b0; 1.747 + reg_interrupt2 <= #UDLY 1'b1; 1.748 + var_length2 <= #UDLY 1'b0; 1.749 + donot_start_again <= #UDLY 1'b1; 1.750 + fifo_rd <= #UDLY 1'b0; 1.751 + end 1.752 + end // if (MB_RTY_I) 1.753 + 1.754 + else if(MB_ERR_I) 1.755 + begin 1.756 + MB_CYC_O <= #UDLY 1'b0; 1.757 + MB_STB_O <= #UDLY 1'b0; 1.758 + MB_CTI_O <= #UDLY 3'h0; 1.759 + status2 <= #UDLY ST_WRITE_IDLE; 1.760 + reg_status2 <= #UDLY 1'b1; 1.761 + reg_interrupt2 <= #UDLY 1'b1; 1.762 + donot_start_again <= #UDLY 1'b1; 1.763 + fifo_rd <= #UDLY 1'b0; 1.764 + end // if (MB_ERR_I) 1.765 + 1.766 + end 1.767 + 1.768 + ST_CNTLNGTH: 1.769 + begin 1.770 + reg_cntlg_burst <= #UDLY 1'b0; 1.771 + status2 <= #UDLY ST_JUSTICE; 1.772 + end 1.773 + 1.774 + ST_JUSTICE: 1.775 + begin 1.776 + if(!(|data_length)) 1.777 + begin 1.778 + status2 <= #UDLY ST_WRITE_IDLE; 1.779 + reg_status2 <= #UDLY 1'b0; 1.780 + reg_interrupt2 <= #UDLY 1'b1; 1.781 + burst_completed <= #UDLY 1'b1; 1.782 + end 1.783 + else 1.784 + begin 1.785 + end_of_transfer <= #UDLY 1'b1; 1.786 + status2 <= ST_WRITE_IDLE; 1.787 + end 1.788 + end 1.789 + 1.790 + default: 1.791 + begin 1.792 + status2 <= #UDLY ST_WRITE_IDLE; 1.793 + MB_ADR_O <= #UDLY 32'h0; 1.794 + MB_SEL_O <= #UDLY 4'b1111; 1.795 + MB_CYC_O <= #UDLY 1'b0; 1.796 + MB_CTI_O <= #UDLY 3'h0; 1.797 + MB_STB_O <= #UDLY 1'b0; 1.798 + reg_status2 <= #UDLY 1'b0; 1.799 + reg_interrupt2 <= #UDLY 1'b0; 1.800 + reg_cntlg_burst <= #UDLY 1'b0; 1.801 + burst_size2 <= #UDLY 5'h0; 1.802 + burst_cnt2 <= #UDLY 5'h0; 1.803 + fifo_rd <= #UDLY 1'b0; 1.804 + end_of_transfer <= #UDLY 1'b0; 1.805 + var_length2 <= #UDLY 1'b0; 1.806 + burst_completed <= #UDLY 1'b0; 1.807 + donot_start_again <= #UDLY 1'b0; 1.808 + end 1.809 + endcase 1.810 + end 1.811 + end 1.812 + else begin 1.813 + // Read/Write Normal 1.814 + case(status) 1.815 + 1.816 + ST_IDLE1: 1.817 + begin 1.818 + if(reg_start | latch_start) 1.819 + begin 1.820 + if(fifo_empty) 1.821 + begin 1.822 + if(latch_start) 1.823 + latch_start <= #UDLY 1'b0; 1.824 + status <= #UDLY ST_READ1; 1.825 + MA_CYC_O <= #UDLY 1'b1; 1.826 + MA_STB_O <= #UDLY 1'b1; 1.827 + MA_ADR_O <= #UDLY reg_00_data; 1.828 + case (reg_00_data[1:0]) 1.829 + 2'b01: MA_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 1.830 + 2'b10: MA_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 1.831 + 2'b11: MA_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 1.832 + default: 1.833 + MA_SEL_O <= #UDLY M_SEL_O; 1.834 + endcase 1.835 + MB_ADR_O <= #UDLY reg_04_data; 1.836 + case (reg_04_data[1:0]) 1.837 + 2'b01: MB_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 1.838 + 2'b10: MB_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 1.839 + 2'b11: MB_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 1.840 + default: 1.841 + MB_SEL_O <= #UDLY M_SEL_O; 1.842 + endcase 1.843 + set_cti_a; 1.844 + start_flag <= #UDLY 1'b1; 1.845 + if(!(|data_length)) 1.846 + var_length <= #UDLY 1'b1; 1.847 + else 1.848 + var_length <= #UDLY 1'b0; 1.849 + burst_size <= #UDLY 5'h0; 1.850 + burst_cnt <= #UDLY 5'h0; 1.851 + end 1.852 + else 1.853 + begin 1.854 + status <= #UDLY ST_RDFIFO1; 1.855 + end 1.856 + end 1.857 + else 1.858 + begin 1.859 + status <= #UDLY ST_IDLE1; 1.860 + end 1.861 + reg_interrupt_normal <= #UDLY 1'b0; 1.862 + end 1.863 + ST_RDFIFO1: 1.864 + begin 1.865 + if(fifo_empty) 1.866 + begin 1.867 + status <= #UDLY ST_IDLE1; 1.868 + fifo_clear <= #UDLY 1'b0; 1.869 + latch_start <= #UDLY 1'b1; 1.870 + end 1.871 + else 1.872 + fifo_clear <= #UDLY !fifo_clear; 1.873 + end 1.874 + 1.875 + ST_RDADDR1: 1.876 + begin 1.877 + MA_CYC_O <= #UDLY 1'b1; 1.878 + MA_STB_O <= #UDLY 1'b1; 1.879 + set_cti_a; 1.880 + status <= #UDLY ST_READ1; 1.881 + direct_data <= #UDLY 1'b1; 1.882 + end 1.883 + 1.884 + ST_READ1: 1.885 + begin 1.886 + if(!start_flag) 1.887 + write_fifo; 1.888 + if(MA_ACK_I) 1.889 + begin 1.890 + if(start_flag) 1.891 + begin 1.892 + MA_CYC_O <= #UDLY 1'b0; 1.893 + MA_STB_O <= #UDLY 1'b0; 1.894 + MA_CTI_O <= #UDLY 3'h0; 1.895 + MB_CYC_O <= #UDLY 1'b1; 1.896 + MB_STB_O <= #UDLY 1'b1; 1.897 + set_cti_b; 1.898 + status <= #UDLY ST_WRITE1; 1.899 + start_flag <= #UDLY 1'b0; 1.900 + burst_cnt <= #UDLY burst_size; 1.901 + end 1.902 + else 1.903 + begin 1.904 + MA_CYC_O <= #UDLY 1'b0; 1.905 + MA_STB_O <= #UDLY 1'b0; 1.906 + MA_CTI_O <= #UDLY 3'h0; 1.907 + if(!reg_d_con) 1.908 + begin 1.909 + MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.910 + if (incr_unit == 3'b001) 1.911 + MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.912 + else 1.913 + if (incr_unit == 3'b010) 1.914 + MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.915 + end 1.916 + status <= #UDLY ST_WRADDR1; 1.917 + burst_cnt <= #UDLY burst_size; 1.918 + end 1.919 + end 1.920 + else if(MA_RTY_I) 1.921 + begin 1.922 + if(var_length) 1.923 + begin 1.924 + MA_CYC_O <= #UDLY 1'b0; 1.925 + MA_STB_O <= #UDLY 1'b0; 1.926 + MA_CTI_O <= #UDLY 3'h0; 1.927 + status <= #UDLY ST_IDLE1; 1.928 + reg_status_normal <= #UDLY 1'b0; 1.929 + reg_interrupt_normal <= #UDLY 1'b1; 1.930 + end 1.931 + end 1.932 + else if(MA_ERR_I) 1.933 + begin 1.934 + MA_CYC_O <= #UDLY 1'b0; 1.935 + MA_STB_O <= #UDLY 1'b0; 1.936 + MA_CTI_O <= #UDLY 3'h0; 1.937 + status <= #UDLY ST_IDLE1; 1.938 + reg_status_normal <= #UDLY 1'b1; 1.939 + reg_interrupt_normal <= #UDLY 1'b1; 1.940 + end 1.941 + end 1.942 + 1.943 + ST_WRADDR1: 1.944 + begin 1.945 + fifo_wr <= #UDLY 1'b0; 1.946 + MB_CYC_O <= #UDLY 1'b1; 1.947 + MB_STB_O <= #UDLY 1'b1; 1.948 + burst_cnt <= #UDLY burst_size; 1.949 + set_cti_b; 1.950 + status <= #UDLY ST_WRITE1; 1.951 + read_fifo; 1.952 + end 1.953 + 1.954 + ST_WRITE1: 1.955 + begin 1.956 + if(fifo_wr) 1.957 + fifo_wr <= #UDLY 1'b0; 1.958 + if(MB_ACK_I) 1.959 + begin 1.960 + direct_data <= #UDLY 1'b0; 1.961 + if(var_length) 1.962 + begin 1.963 + MB_CYC_O <= #UDLY 1'b0; 1.964 + MB_STB_O <= #UDLY 1'b0; 1.965 + MB_CTI_O <= #UDLY 3'h0; 1.966 + if(!reg_s_con) 1.967 + begin 1.968 + MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.969 + if (incr_unit == 3'b001) 1.970 + MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.971 + else 1.972 + if (incr_unit == 3'b010) 1.973 + MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.974 + end 1.975 + status <= #UDLY ST_RDADDR1; 1.976 + fifo_rd <= #UDLY 1'b0; 1.977 + burst_cnt <= #UDLY burst_size; 1.978 + end 1.979 + else 1.980 + begin 1.981 + MB_CYC_O <= #UDLY 1'b0; 1.982 + MB_STB_O <= #UDLY 1'b0; 1.983 + MB_CTI_O <= #UDLY 3'h0; 1.984 + reg_cntlg_normal <= #UDLY 1'b1; 1.985 + status <= #UDLY ST_CNTLNGTH1; 1.986 + fifo_rd <= #UDLY 1'b0; 1.987 + burst_cnt <= #UDLY burst_size; 1.988 + end 1.989 + end 1.990 + else if(MB_RTY_I) 1.991 + begin 1.992 + if(var_length) 1.993 + begin 1.994 + MB_CYC_O <= #UDLY 1'b0; 1.995 + MB_STB_O <= #UDLY 1'b0; 1.996 + MB_CTI_O <= #UDLY 3'h0; 1.997 + status <= #UDLY ST_IDLE1; 1.998 + reg_status_normal <= #UDLY 1'b0; 1.999 + reg_interrupt_normal <= #UDLY 1'b1; 1.1000 + var_length <= #UDLY 1'b0; 1.1001 + fifo_rd <= #UDLY 1'b0; 1.1002 + end 1.1003 + end 1.1004 + else if(MB_ERR_I) 1.1005 + begin 1.1006 + MB_CYC_O <= #UDLY 1'b0; 1.1007 + MB_STB_O <= #UDLY 1'b0; 1.1008 + MB_CTI_O <= #UDLY 3'h0; 1.1009 + status <= #UDLY ST_IDLE1; 1.1010 + reg_status_normal <= #UDLY 1'b1; 1.1011 + reg_interrupt_normal <= #UDLY 1'b1; 1.1012 + fifo_rd <= #UDLY 1'b0; 1.1013 + end 1.1014 + end 1.1015 + 1.1016 + ST_CNTLNGTH1: 1.1017 + begin 1.1018 + reg_cntlg_normal <= #UDLY 1'b0; 1.1019 + status <= #UDLY ST_JUSTICE1; 1.1020 + end 1.1021 + 1.1022 + ST_JUSTICE1: 1.1023 + begin 1.1024 + if(!(|data_length)) 1.1025 + begin 1.1026 + status <= #UDLY ST_IDLE1; 1.1027 + reg_status_normal <= #UDLY 1'b0; 1.1028 + reg_interrupt_normal <= #UDLY 1'b1; 1.1029 + end 1.1030 + else 1.1031 + begin 1.1032 + if(!reg_s_con) 1.1033 + begin 1.1034 + MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.1035 + if (incr_unit == 3'b001) 1.1036 + MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.1037 + else 1.1038 + if (incr_unit == 3'b010) 1.1039 + MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.1040 + end 1.1041 + status <= #UDLY ST_RDADDR1; 1.1042 + end 1.1043 + end 1.1044 + 1.1045 + default: 1.1046 + begin 1.1047 + status <= #UDLY ST_IDLE1; 1.1048 + var_length <= #UDLY 1'b0; 1.1049 + MA_CYC_O <= #UDLY 1'b0; 1.1050 + MA_CTI_O <= #UDLY 3'h0; 1.1051 + MB_CYC_O <= #UDLY 1'b0; 1.1052 + MB_CTI_O <= #UDLY 3'h0; 1.1053 + MA_STB_O <= #UDLY 1'b0; 1.1054 + MB_STB_O <= #UDLY 1'b0; 1.1055 + reg_status_normal <= #UDLY 1'b0; 1.1056 + reg_interrupt_normal <= #UDLY 1'b0; 1.1057 + reg_cntlg_normal <= #UDLY 1'b0; 1.1058 + burst_size <= #UDLY 3'h0; 1.1059 + burst_cnt <= #UDLY 3'h0; 1.1060 + fifo_wr <= #UDLY 1'b0; 1.1061 + fifo_rd <= #UDLY 1'b0; 1.1062 + fifo_clear <= #UDLY 1'b0; 1.1063 + latch_start <= #UDLY 1'b0; 1.1064 + direct_data <= #UDLY 1'b0; 1.1065 + end 1.1066 + endcase 1.1067 + end 1.1068 + end 1.1069 + 1.1070 + //Task for generating write enable to the FIFO 1.1071 + task write_fifo; 1.1072 + begin 1.1073 + if(MA_ACK_I) 1.1074 + begin 1.1075 + fifo_wr <= #UDLY 1'b1; 1.1076 + fifo_din <= #UDLY MA_DAT_I; 1.1077 + end 1.1078 + else 1.1079 + begin 1.1080 + fifo_wr <= #UDLY 1'b0; 1.1081 + end 1.1082 + end 1.1083 + endtask 1.1084 + 1.1085 + //Task for generating read enable signal to the FIFO 1.1086 + task read_fifo; 1.1087 + begin 1.1088 + fifo_rd <= #UDLY 1'b1; 1.1089 + end 1.1090 + endtask 1.1091 + 1.1092 + //Task for setting wishbone CTI signal for read 1.1093 + //master port depending upon whether request is for burst 1.1094 + //transfer or classic cycle. 1.1095 + task set_cti_a; 1.1096 + begin 1.1097 + if(reg_bt2) 1.1098 + begin 1.1099 + if(reg_s_con) 1.1100 + MA_CTI_O <= #UDLY 3'b001; 1.1101 + else 1.1102 + MA_CTI_O <= #UDLY 3'b010; 1.1103 + end 1.1104 + else 1.1105 + MA_CTI_O <= #UDLY 3'b000; 1.1106 + end 1.1107 + endtask 1.1108 + 1.1109 + //Task for setting wishbone CTI signal for write 1.1110 + //master port depending upon whether request is for burst 1.1111 + //transfer or classic cycle. 1.1112 + task set_cti_b; 1.1113 + begin 1.1114 + if(reg_bt2) begin 1.1115 + if(reg_d_con) 1.1116 + MB_CTI_O <= #UDLY 3'b001; 1.1117 + else 1.1118 + MB_CTI_O <= #UDLY 3'b010; 1.1119 + end else 1.1120 + MB_CTI_O <= #UDLY 3'b000; 1.1121 + end 1.1122 + endtask 1.1123 + 1.1124 + //RdEn 1.1125 + reg fifo_rd_dly; 1.1126 + always @(posedge CLK_I or posedge RST_I) 1.1127 + if(RST_I) 1.1128 + fifo_rd_dly <= #UDLY 1'b0; 1.1129 + else 1.1130 + fifo_rd_dly <= #UDLY fifo_rd; 1.1131 + 1.1132 + wire RdEn = fifo_rd & (!fifo_rd_dly | (reg_bt2 ? (burst_cnt2[5:0] != 5'b00000) : (burst_cnt[5:0] != 5'b00000)) & MB_ACK_I) | fifo_clear; 1.1133 + 1.1134 + generate 1.1135 + if (lat_family == "SC" || lat_family == "SCM") begin 1.1136 + 1.1137 + pmi_fifo_dc #(.pmi_data_width_w(32), 1.1138 + .pmi_data_width_r(32), 1.1139 + .pmi_data_depth_w(32), 1.1140 + .pmi_data_depth_r(32), 1.1141 + .pmi_full_flag(32), 1.1142 + .pmi_empty_flag(0), 1.1143 + .pmi_almost_full_flag(28), 1.1144 + .pmi_almost_empty_flag(4), 1.1145 + .pmi_regmode("noreg"), 1.1146 + .pmi_family(`LATTICE_FAMILY), 1.1147 + .module_type("pmi_fifo_dc"), 1.1148 + .pmi_implementation(FIFO_IMPLEMENTATION)) 1.1149 + dma_fifo_dc ( 1.1150 + .Data(fifo_din), 1.1151 + .WrClock(CLK_I), 1.1152 + .RdClock(CLK_I), 1.1153 + .WrEn (fifo_wr), 1.1154 + .RdEn (RdEn), 1.1155 + .Reset (RST_I), 1.1156 + .RPReset(RST_I), 1.1157 + .Q (fifo_dout), 1.1158 + .Empty (fifo_empty), 1.1159 + .Full (), 1.1160 + .AlmostEmpty (), 1.1161 + .AlmostFull ()); 1.1162 + 1.1163 + 1.1164 + 1.1165 + end else begin 1.1166 + pmi_fifo #(.pmi_data_width(32), 1.1167 + .pmi_data_depth(32), 1.1168 + .pmi_full_flag(32), 1.1169 + .pmi_empty_flag(0), 1.1170 + .pmi_almost_full_flag(28), 1.1171 + .pmi_almost_empty_flag(1), 1.1172 + .pmi_regmode("noreg"), 1.1173 + .pmi_family(`LATTICE_FAMILY), 1.1174 + .module_type("pmi_fifo"), 1.1175 + .pmi_implementation(FIFO_IMPLEMENTATION)) 1.1176 + dma_fifo (.Data (fifo_din), 1.1177 + .Clock (CLK_I), 1.1178 + .WrEn (fifo_wr), 1.1179 + .RdEn (RdEn), 1.1180 + .Reset (RST_I), 1.1181 + .Q (fifo_dout), 1.1182 + .Empty (fifo_empty), 1.1183 + .Full (), 1.1184 + .AlmostEmpty (fifo_aempty), 1.1185 + .AlmostFull ()); 1.1186 + end 1.1187 + endgenerate 1.1188 + 1.1189 +endmodule // MASTER_CTRL 1.1190 + 1.1191 +`endif // MASTER_CTRL_FILE