Fri, 13 Aug 2010 10:43:05 +0100
Initial commit, DMAC version 3.1
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LM32 DMA Component
18 // File : master_ctrl.v
19 // Title : DMA Master controller
20 // Dependencies : None
21 //
22 // Version 3.1
23 // 1. Make DMA Engine compliant to Rule 3.100 of Wishbone Spec which defines
24 // alignement of bytes in sub-word transfers.
25 // 2. Removed glitch that did not pause the burst write when the read burst
26 // was paused by the "read slave".
27 //
28 // Version 7.0SP2, 3.0
29 // 1. Read and Write channel of DMA controller are working in parallel,
30 // due to that now as soon as FIFO is not empty write channel of the DMA
31 // controller start writing data to the slave.
32 // 2. Burst Size supported by DMA controller is increased to support bigger
33 // burst (from current value of 4 and 8 to 16 and 32). Now 4 different type
34 // of burst sizes are supported by the DMA controller 4, 8, 16 and 32.
35 // For this Burst Size field of the control register is increased to 2 bits.
36 // 3. Glitch is removed on the S_ACK_O signal.
37 //
38 // Version 7.0
39 // 1. Initial Release
40 //
41 // =============================================================================
43 `ifndef MASTER_CTRL_FILE
44 `define MASTER_CTRL_FILE
45 `include "system_conf.v"
46 module MASTER_CTRL
47 #(parameter LENGTH_WIDTH = 16,
48 parameter FIFO_IMPLEMENTATION = "EBR")
49 (
50 //master read port
51 MA_ADR_O,
52 MA_SEL_O,
53 MA_WE_O,
54 MA_STB_O,
55 MA_CYC_O,
56 MA_CTI_O,
57 MA_LOCK_O,
58 MA_DAT_I, //32bits
59 MA_ACK_I,
60 MA_ERR_I,
61 MA_RTY_I,
62 //master write port
63 MB_ADR_O,
64 MB_SEL_O,
65 MB_DAT_O, //32bits
66 MB_WE_O,
67 MB_STB_O,
68 MB_CYC_O,
69 MB_CTI_O,
70 MB_LOCK_O,
71 MB_ACK_I,
72 MB_ERR_I,
73 MB_RTY_I,
74 //register interface
75 M_SEL_O,
76 reg_start,
77 reg_status,
78 reg_interrupt,
79 reg_busy,
80 data_length,
81 reg_cntlg,
82 reg_bt2,reg_bt1,reg_bt0,
83 incr_unit,
84 reg_s_con,
85 reg_d_con,
86 reg_00_data,
87 reg_04_data,
88 //system clock and reset
89 CLK_I,
90 RST_I
91 );
92 //master read port
93 output [31:0] MA_ADR_O;
94 output [3:0] MA_SEL_O;
95 output MA_WE_O;
96 output MA_STB_O;
97 output MA_CYC_O;
98 output [2:0] MA_CTI_O;
99 output MA_LOCK_O;
100 input [31:0] MA_DAT_I; //32bits
101 input MA_ACK_I;
102 input MA_ERR_I;
103 input MA_RTY_I;
104 //master write port
105 output [31:0] MB_ADR_O;
106 output [3:0] MB_SEL_O;
107 output [31:0] MB_DAT_O; //32bits
108 output MB_WE_O;
109 output MB_STB_O;
110 output MB_CYC_O;
111 output [2:0] MB_CTI_O;
112 output MB_LOCK_O;
113 input MB_ACK_I;
114 input MB_ERR_I;
115 input MB_RTY_I;
117 //register interface
118 input [3:0] M_SEL_O;
119 input reg_start;
120 output reg_status;
121 output reg_interrupt;
122 output reg_busy;
123 input [LENGTH_WIDTH-1:0] data_length;
124 output reg_cntlg;
125 input reg_bt2,reg_bt1,reg_bt0;
126 input [2:0] incr_unit;
127 input reg_s_con;
128 input reg_d_con;
129 input [31:0] reg_00_data;
130 input [31:0] reg_04_data;
131 //system clock and reset
132 input CLK_I;
133 input RST_I;
135 parameter lat_family = `LATTICE_FAMILY;
136 parameter UDLY = 1;
137 //Read FSM States encoding
138 parameter ST_IDLE = 3'b000;
139 parameter ST_READ = 3'b001;
140 parameter ST_RDADDR = 3'b010;
141 parameter ST_RDFIFO = 3'b011;
142 parameter ST_WAIT_WRITE_FINISH = 3'b100;
144 //Write FSM States encoding
145 parameter ST_WRITE_IDLE = 4'b0000;
146 parameter ST_WRITE = 4'b0001;
147 parameter ST_WRADDR = 4'b0010;
148 parameter ST_CNTLNGTH = 4'b0011;
149 parameter ST_JUSTICE = 4'b0100;
150 parameter ST_FIFO_EMPTY = 4'b0101;
151 parameter ST_WRITE_WAIT = 4'b0110;
152 parameter ST_FIFO_AEMPTY = 4'b1010;
153 parameter ST_FIFO_RESUME = 4'b1000;
155 // FSM for normal data transfer
156 parameter ST_IDLE1 = 3'b000;
157 parameter ST_READ1 = 3'b001;
158 parameter ST_WRITE1 = 3'b010;
159 parameter ST_RDADDR1 = 3'b011;
160 parameter ST_WRADDR1 = 3'b100;
161 parameter ST_CNTLNGTH1 = 3'b101;
162 parameter ST_JUSTICE1 = 3'b110;
163 parameter ST_RDFIFO1 = 3'b111;
164 reg [2:0] status;
165 reg var_length;
168 //fifo status
170 reg [2:0] status1;
171 reg [3:0] status2;
172 reg var_length2;
173 reg var_length1;
174 reg MA_STB_O;
175 reg MB_STB_O;
176 reg MA_CYC_O;
177 reg MB_CYC_O;
178 reg [2:0] MA_CTI_O;
179 reg [2:0] MB_CTI_O;
180 wire MA_WE_O = 1'b0;
181 wire MB_WE_O = 1'b1;
182 reg [31:0] MA_ADR_O;
183 reg [31:0] MB_ADR_O;
184 reg [3:0] MA_SEL_O;
185 reg [3:0] MB_SEL_O;
186 wire MA_LOCK_O = 0; //reg_bt2 ? (status1 == ST_READ) && (!(MA_CTI_O == 3'h7)) : 1'b0;
187 wire MB_LOCK_O = 0; //reg_bt2 ? (status2 == ST_WRITE) && (!(MB_CTI_O == 3'h7)) : 1'b0;
189 wire reg_busy = reg_bt2 ? !(status1 == ST_IDLE) : !(status == ST_IDLE1);
190 wire reg_interrupt;
191 wire reg_status;
193 wire reg_cntlg;
194 reg start_flag;
195 reg [5:0] burst_size;
196 reg [5:0] burst_cnt;
197 reg fifo_wr;
198 reg fifo_rd;
199 reg [31:0] fifo_din;
200 wire [31:0] fifo_dout;
201 wire fifo_empty;
202 wire fifo_aempty;
203 reg fifo_clear;
204 reg [31:0] first_data;
205 reg first_data_flag;
206 wire [31:0] MB_DAT_O = first_data_flag ? first_data : fifo_dout;
207 reg latch_start;
209 reg reg_status1, reg_status2;
210 reg reg_interrupt1, reg_interrupt2;
211 reg end_of_transfer;
212 reg burst_completed;
213 reg donot_start_again;
214 reg [5:0] burst_size2;
215 reg [5:0] burst_cnt2;
217 reg reg_cntlg_burst, reg_cntlg_normal;
218 reg reg_status_normal, reg_interrupt_normal;
219 reg direct_data;
221 always @(posedge CLK_I or posedge RST_I)
222 if(RST_I)
223 begin
224 first_data <= #UDLY 'h0;
225 first_data_flag <= #UDLY 1'b0;
226 end
227 else if((start_flag || direct_data) & !reg_bt2 & MA_ACK_I)
228 begin
229 first_data <= #UDLY MA_DAT_I;
230 first_data_flag <= #UDLY 1'b1;
231 end
232 else if(first_data_flag & MB_ACK_I)
233 begin
234 first_data_flag <= #UDLY 1'b0;
235 end
237 assign reg_status = reg_bt2 ? (reg_status1 | reg_status2) : reg_status_normal;
238 assign reg_interrupt = reg_bt2 ? (reg_interrupt1 | reg_interrupt2) : reg_interrupt_normal;
239 assign reg_cntlg = reg_bt2 ? reg_cntlg_burst : reg_cntlg_normal;
242 //FSM
243 always @(posedge CLK_I or posedge RST_I)
244 if(RST_I)
245 begin
246 status1 <= #UDLY ST_IDLE;
247 var_length1 <= #UDLY 1'b0;
248 MA_ADR_O <= #UDLY 32'h0;
249 MA_SEL_O <= #UDLY 4'b1111;
250 MA_CYC_O <= #UDLY 1'b0;
251 MA_CTI_O <= #UDLY 3'h0;
252 MA_STB_O <= #UDLY 1'b0;
253 reg_status1 <= #UDLY 1'b0;
254 reg_interrupt1 <= #UDLY 1'b0;
255 start_flag <= #UDLY 1'b0;
256 burst_size <= #UDLY 5'h0;
257 burst_cnt <= #UDLY 5'h0;
258 fifo_clear <= #UDLY 1'b0;
259 latch_start <= #UDLY 1'b0;
260 fifo_wr <= #UDLY 1'b0;
262 status2 <= #UDLY ST_WRITE_IDLE;
263 MB_ADR_O <= #UDLY 32'h0;
264 MB_SEL_O <= #UDLY 4'b1111;
265 MB_CYC_O <= #UDLY 1'b0;
266 MB_CTI_O <= #UDLY 3'h0;
267 MB_STB_O <= #UDLY 1'b0;
268 reg_status2 <= #UDLY 1'b0;
269 reg_interrupt2 <= #UDLY 1'b0;
270 reg_cntlg_burst <= #UDLY 1'b0;
271 burst_size2 <= #UDLY 5'h0;
272 burst_cnt2 <= #UDLY 5'h0;
273 fifo_rd <= #UDLY 1'b0;
274 end_of_transfer <= #UDLY 1'b0;
275 var_length2 <= #UDLY 1'b0;
276 burst_completed <= #UDLY 1'b0;
277 donot_start_again <= #UDLY 1'b0;
279 status <= #UDLY ST_IDLE1;
280 var_length <= #UDLY 1'b0;
281 reg_status_normal <= #UDLY 1'b0;
282 reg_interrupt_normal <= #UDLY 1'b0;
283 reg_cntlg_normal <= #UDLY 1'b0;
284 direct_data <= #UDLY 1'b0;
285 end
286 else
287 begin
288 if (reg_bt2) begin
289 // Read Burst
290 if ((MB_RTY_I && (!(|data_length))) || (MB_ERR_I && (status2 == ST_WRITE)))
291 begin
292 status1 <= #UDLY ST_IDLE;
293 end
294 else
295 begin
296 case(status1)
297 ST_IDLE:
298 begin
299 if(fifo_wr)
300 fifo_wr <= #UDLY 1'b0;
301 if(MA_ACK_I)
302 begin
303 MA_CYC_O <= #UDLY 1'b0;
304 MA_STB_O <= #UDLY 1'b0;
305 MA_CTI_O <= #UDLY 3'h0;
306 end
307 if(reg_start | latch_start)
308 begin
309 if(fifo_empty)
310 begin
311 if(latch_start)
312 latch_start <= #UDLY 1'b0;
313 status1 <= #UDLY ST_READ;
314 MA_CYC_O <= #UDLY 1'b1;
315 MA_STB_O <= #UDLY 1'b1;
316 MA_ADR_O <= #UDLY reg_00_data;
317 case (reg_00_data[1:0])
318 2'b01: MA_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]};
319 2'b10: MA_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]};
320 2'b11: MA_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]};
321 default:
322 MA_SEL_O <= #UDLY M_SEL_O;
323 endcase
324 set_cti_a;
325 start_flag <= #UDLY 1'b1;
326 if(!(|data_length))
327 var_length1 <= #UDLY 1'b1;
328 else
329 var_length1 <= #UDLY 1'b0;
330 burst_size <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3);
331 burst_cnt <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3);
332 end
333 else
334 status1 <= #UDLY ST_RDFIFO;
335 end
336 else
337 status1 <= #UDLY ST_IDLE;
338 reg_interrupt1 <= #UDLY 1'b0;
339 end
341 ST_WAIT_WRITE_FINISH:
342 begin
343 fifo_wr <= #UDLY 1'b0;
344 if (status2 == ST_WRITE)
345 start_flag <= #UDLY 1'b0;
346 if(end_of_transfer)
347 begin
348 if(!reg_s_con)
349 MA_ADR_O <= #UDLY MA_ADR_O + incr_unit;
350 if (incr_unit == 3'b001)
351 MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]};
352 else
353 if (incr_unit == 3'b010)
354 MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]};
356 status1 <= #UDLY ST_RDADDR;
357 burst_cnt <= #UDLY burst_size;
358 end
359 else
360 begin
361 if(burst_completed)
362 status1 <= #UDLY ST_IDLE;
363 end
364 end
366 ST_RDFIFO:
367 begin
368 if(fifo_empty)
369 begin
370 status1 <= #UDLY ST_IDLE;
371 fifo_clear <= #UDLY 1'b0;
372 latch_start <= #UDLY 1'b1;
373 end
374 else
375 fifo_clear <= #UDLY !fifo_clear;
376 end
378 ST_RDADDR:
379 begin
380 MA_CYC_O <= #UDLY 1'b1;
381 MA_STB_O <= #UDLY 1'b1;
382 set_cti_a;
383 status1 <= #UDLY ST_READ;
384 end
386 ST_READ:
387 begin
388 write_fifo;
389 if(MA_ACK_I)
390 begin
391 if(start_flag)
392 begin
393 if(burst_cnt == 0)
394 begin
395 MA_CYC_O <= #UDLY 1'b0;
396 MA_STB_O <= #UDLY 1'b0;
397 MA_CTI_O <= #UDLY 3'h0;
398 status1 <= #UDLY ST_WAIT_WRITE_FINISH;
399 end
400 else
401 begin
402 if(burst_cnt == 1)
403 MA_CTI_O <= #UDLY 3'h7;
404 burst_cnt <= #UDLY burst_cnt - 1;
405 if(!reg_s_con)
406 MA_ADR_O <= #UDLY MA_ADR_O + incr_unit;
407 if (incr_unit == 3'b001)
408 MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]};
409 else
410 if (incr_unit == 3'b010)
411 MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]};
412 end
413 end
414 else
415 begin
416 if(burst_cnt == 0)
417 begin
418 MA_CYC_O <= #UDLY 1'b0;
419 MA_STB_O <= #UDLY 1'b0;
420 MA_CTI_O <= #UDLY 3'h0;
421 status1 <= #UDLY ST_WAIT_WRITE_FINISH;
422 end
423 else
424 begin
425 if(burst_cnt == 1)
426 MA_CTI_O <= #UDLY 3'h7;
427 if(!reg_s_con)
428 MA_ADR_O <= #UDLY MA_ADR_O + incr_unit;
429 if (incr_unit == 3'b001)
430 MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]};
431 else
432 if (incr_unit == 3'b010)
433 MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]};
434 burst_cnt <= #UDLY burst_cnt - 1;
435 end
436 end
437 end
438 else if(MA_RTY_I)
439 begin
440 if(var_length1)
441 begin
442 MA_CYC_O <= #UDLY 1'b0;
443 MA_STB_O <= #UDLY 1'b0;
444 MA_CTI_O <= #UDLY 3'h0;
445 status1 <= #UDLY ST_IDLE;
446 reg_status1 <= #UDLY 1'b0;
447 reg_interrupt1 <= #UDLY 1'b1;
448 start_flag <= #UDLY 1'b0;
449 end
450 end
451 else if(MA_ERR_I)
452 begin
453 MA_CYC_O <= #UDLY 1'b0;
454 MA_STB_O <= #UDLY 1'b0;
455 MA_CTI_O <= #UDLY 3'h0;
456 status1 <= #UDLY ST_IDLE;
457 reg_status1 <= #UDLY 1'b1;
458 reg_interrupt1 <= #UDLY 1'b1;
459 start_flag <= #UDLY 1'b0;
460 end
461 end
463 default:
464 begin
465 status1 <= #UDLY ST_IDLE;
466 var_length1 <= #UDLY 1'b0;
467 MA_ADR_O <= #UDLY 32'h0;
468 MA_SEL_O <= #UDLY 4'b1111;
469 MA_CYC_O <= #UDLY 1'b0;
470 MA_CTI_O <= #UDLY 3'h0;
471 MA_STB_O <= #UDLY 1'b0;
472 reg_status1 <= #UDLY 1'b0;
473 reg_interrupt1 <= #UDLY 1'b0;
474 start_flag <= #UDLY 1'b0;
475 burst_size <= #UDLY 5'h0;
476 burst_cnt <= #UDLY 5'h0;
477 fifo_clear <= #UDLY 1'b0;
478 latch_start <= #UDLY 1'b0;
479 fifo_wr <= #UDLY 1'b0;
480 end
481 endcase
482 end
483 // Write Burst
484 if ((MA_RTY_I && (!(|data_length))) || (MA_ERR_I && (status1 == ST_READ)))
485 begin
486 status2 <= #UDLY ST_WRITE_IDLE;
487 donot_start_again <= #UDLY 1'b1;
488 end
489 else
490 begin
491 case(status2)
492 ST_WRITE_IDLE:
493 begin
494 if(reg_start)
495 begin
496 MB_ADR_O <= #UDLY reg_04_data;
497 case (reg_04_data[1:0])
498 2'b01: MB_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]};
499 2'b10: MB_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]};
500 2'b11: MB_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]};
501 default:
502 MB_SEL_O <= #UDLY M_SEL_O;
503 endcase
504 if(!(|data_length))
505 var_length2 <= #UDLY 1'b1;
506 else
507 var_length2 <= #UDLY 1'b0;
508 burst_size2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3);
509 burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3);
510 if(!fifo_empty)
511 status2 <= #UDLY ST_FIFO_EMPTY;
512 else
513 donot_start_again <= #UDLY 1'b0;
514 end
515 if(fifo_empty)
516 begin
517 if(MB_ACK_I)
518 begin
519 MB_CYC_O <= #UDLY 1'b0;
520 MB_STB_O <= #UDLY 1'b0;
521 MB_CTI_O <= #UDLY 3'h0;
522 fifo_rd <= #UDLY 1'b0;
523 end
524 burst_cnt2 <= #UDLY 5'h0;
525 end
526 else
527 begin
528 if(donot_start_again)
529 begin
530 if(MB_ACK_I)
531 begin
532 if(!reg_d_con)
533 MB_ADR_O <= #UDLY MB_ADR_O + incr_unit;
534 if (incr_unit == 3'b001)
535 MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]};
536 else
537 if (incr_unit == 3'b010)
538 MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]};
539 end
540 end
541 end
543 if(!fifo_empty && !donot_start_again)
544 begin
545 if(start_flag)
546 begin
547 set_cti_b;
548 status2 <= #UDLY ST_WRITE_WAIT;
549 read_fifo;
550 burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3);
551 end
552 else
553 begin
554 if(!reg_d_con)
555 MB_ADR_O <= #UDLY MB_ADR_O + incr_unit;
556 if (incr_unit == 3'b001)
557 MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]};
558 else
559 if (incr_unit == 3'b010)
560 MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]};
561 status2 <= #UDLY ST_WRADDR;
562 read_fifo;
563 burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3);
564 end
565 end
566 end_of_transfer <= #UDLY 1'b0;
567 burst_completed <= #UDLY 1'b0;
568 reg_interrupt2 <= #UDLY 1'b0;
569 end
571 ST_FIFO_EMPTY:
572 begin
573 if(fifo_empty)
574 begin
575 status2 <= #UDLY ST_WRITE_IDLE;
576 donot_start_again <= #UDLY 1'b0;
577 end
578 end
580 ST_WRADDR:
581 begin
582 burst_cnt2 <= #UDLY burst_size2;
583 MB_CYC_O <= #UDLY 1'b1;
584 MB_STB_O <= #UDLY 1'b1;
586 if (fifo_aempty && (burst_size2 > 5'h2))
587 begin
588 MB_CTI_O <= #UDLY 3'b000;
589 status2 <= #UDLY ST_FIFO_AEMPTY;
590 fifo_rd <= #UDLY 1'b0;
591 end
592 else
593 begin
594 set_cti_b;
595 status2 <= #UDLY ST_WRITE;
596 end
597 end
599 ST_WRITE_WAIT:
600 begin
601 MB_CYC_O <= #UDLY 1'b1;
602 MB_STB_O <= #UDLY 1'b1;
604 if (fifo_aempty && (burst_size2 > 5'h2))
605 begin
606 MB_CTI_O <= #UDLY 3'b000;
607 status2 <= #UDLY ST_FIFO_AEMPTY;
608 fifo_rd <= #UDLY 1'b0;
609 end
610 else
611 begin
612 set_cti_b;
613 status2 <= #UDLY ST_WRITE;
614 end
615 end
617 ST_FIFO_AEMPTY:
618 begin
619 if (MB_ACK_I)
620 begin
621 MB_CYC_O <= #UDLY 1'b0;
622 MB_STB_O <= #UDLY 1'b0;
624 burst_cnt2 <= #UDLY burst_cnt2 - 1;
626 if (!reg_d_con)
627 MB_ADR_O <= #UDLY MB_ADR_O + incr_unit;
629 if (incr_unit == 3'b001)
630 MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]};
631 else
632 if (incr_unit == 3'b010)
633 MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]};
634 end
636 if (!MB_CYC_O && !fifo_aempty)
637 begin
638 status2 <= #UDLY ST_FIFO_RESUME;
639 read_fifo;
640 end
641 end
643 ST_FIFO_RESUME:
644 begin
645 MB_CYC_O <= #UDLY 1'b1;
646 MB_STB_O <= #UDLY 1'b1;
648 if (fifo_aempty && (burst_cnt2 > 5'h2))
649 begin
650 MB_CTI_O <= #UDLY 3'b000;
651 status2 <= #UDLY ST_FIFO_AEMPTY;
652 fifo_rd <= #UDLY 1'b0;
653 end
654 else
655 begin
656 set_cti_b;
657 status2 <= #UDLY ST_WRITE;
658 end
659 end
661 ST_WRITE:
662 begin
663 if (MB_ACK_I)
664 begin
665 if(var_length2)
666 begin
667 if(burst_cnt2 == 0)
668 begin
669 MB_CYC_O <= #UDLY 1'b0;
670 MB_STB_O <= #UDLY 1'b0;
671 MB_CTI_O <= #UDLY 3'h0;
672 end_of_transfer <= #UDLY 1'b1;
673 status2 <= #UDLY ST_WRITE_IDLE;
674 fifo_rd <= #UDLY 1'b0;
675 burst_cnt2 <= #UDLY burst_size2;
676 end
677 else
678 begin
679 if(burst_cnt2 == 1)
680 MB_CTI_O <= #UDLY 3'h7;
681 else
682 set_cti_b;
683 if(!reg_d_con)
684 MB_ADR_O <= #UDLY MB_ADR_O + incr_unit;
685 if (incr_unit == 3'b001)
686 MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]};
687 else
688 if (incr_unit == 3'b010)
689 MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]};
690 read_fifo;
691 burst_cnt2 <= #UDLY burst_cnt2 - 1;
692 end
693 end
694 else
695 begin
696 if(burst_cnt2 == 0)
697 begin
698 MB_CYC_O <= #UDLY 1'b0;
699 MB_STB_O <= #UDLY 1'b0;
700 MB_CTI_O <= #UDLY 3'h0;
701 reg_cntlg_burst <= #UDLY 1'b1;
702 status2 <= #UDLY ST_CNTLNGTH;
703 fifo_rd <= #UDLY 1'b0;
704 burst_cnt2 <= #UDLY burst_size2;
705 end
706 else
707 begin
708 if ((fifo_aempty && (burst_cnt2 > 5'h2)) || (burst_cnt2 == 5'h1))
709 MB_CTI_O <= #UDLY 3'h7;
710 else
711 set_cti_b;
713 burst_cnt2 <= #UDLY burst_cnt2 - 1;
715 if(!reg_d_con)
716 MB_ADR_O <= #UDLY MB_ADR_O + incr_unit;
718 if (incr_unit == 3'b001)
719 MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]};
720 else
721 if (incr_unit == 3'b010)
722 MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]};
724 if (fifo_aempty && (burst_cnt2 > 5'h2))
725 begin
726 status2 <= #UDLY ST_FIFO_AEMPTY;
727 fifo_rd <= 1'b0;
728 end
729 else
730 read_fifo;
731 end
732 end
733 end
735 else if(MB_RTY_I)
736 begin
737 if(var_length2)
738 begin
739 MB_CYC_O <= #UDLY 1'b0;
740 MB_STB_O <= #UDLY 1'b0;
741 MB_CTI_O <= #UDLY 3'h0;
742 status2 <= #UDLY ST_WRITE_IDLE;
743 reg_status2 <= #UDLY 1'b0;
744 reg_interrupt2 <= #UDLY 1'b1;
745 var_length2 <= #UDLY 1'b0;
746 donot_start_again <= #UDLY 1'b1;
747 fifo_rd <= #UDLY 1'b0;
748 end
749 end // if (MB_RTY_I)
751 else if(MB_ERR_I)
752 begin
753 MB_CYC_O <= #UDLY 1'b0;
754 MB_STB_O <= #UDLY 1'b0;
755 MB_CTI_O <= #UDLY 3'h0;
756 status2 <= #UDLY ST_WRITE_IDLE;
757 reg_status2 <= #UDLY 1'b1;
758 reg_interrupt2 <= #UDLY 1'b1;
759 donot_start_again <= #UDLY 1'b1;
760 fifo_rd <= #UDLY 1'b0;
761 end // if (MB_ERR_I)
763 end
765 ST_CNTLNGTH:
766 begin
767 reg_cntlg_burst <= #UDLY 1'b0;
768 status2 <= #UDLY ST_JUSTICE;
769 end
771 ST_JUSTICE:
772 begin
773 if(!(|data_length))
774 begin
775 status2 <= #UDLY ST_WRITE_IDLE;
776 reg_status2 <= #UDLY 1'b0;
777 reg_interrupt2 <= #UDLY 1'b1;
778 burst_completed <= #UDLY 1'b1;
779 end
780 else
781 begin
782 end_of_transfer <= #UDLY 1'b1;
783 status2 <= ST_WRITE_IDLE;
784 end
785 end
787 default:
788 begin
789 status2 <= #UDLY ST_WRITE_IDLE;
790 MB_ADR_O <= #UDLY 32'h0;
791 MB_SEL_O <= #UDLY 4'b1111;
792 MB_CYC_O <= #UDLY 1'b0;
793 MB_CTI_O <= #UDLY 3'h0;
794 MB_STB_O <= #UDLY 1'b0;
795 reg_status2 <= #UDLY 1'b0;
796 reg_interrupt2 <= #UDLY 1'b0;
797 reg_cntlg_burst <= #UDLY 1'b0;
798 burst_size2 <= #UDLY 5'h0;
799 burst_cnt2 <= #UDLY 5'h0;
800 fifo_rd <= #UDLY 1'b0;
801 end_of_transfer <= #UDLY 1'b0;
802 var_length2 <= #UDLY 1'b0;
803 burst_completed <= #UDLY 1'b0;
804 donot_start_again <= #UDLY 1'b0;
805 end
806 endcase
807 end
808 end
809 else begin
810 // Read/Write Normal
811 case(status)
813 ST_IDLE1:
814 begin
815 if(reg_start | latch_start)
816 begin
817 if(fifo_empty)
818 begin
819 if(latch_start)
820 latch_start <= #UDLY 1'b0;
821 status <= #UDLY ST_READ1;
822 MA_CYC_O <= #UDLY 1'b1;
823 MA_STB_O <= #UDLY 1'b1;
824 MA_ADR_O <= #UDLY reg_00_data;
825 case (reg_00_data[1:0])
826 2'b01: MA_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]};
827 2'b10: MA_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]};
828 2'b11: MA_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]};
829 default:
830 MA_SEL_O <= #UDLY M_SEL_O;
831 endcase
832 MB_ADR_O <= #UDLY reg_04_data;
833 case (reg_04_data[1:0])
834 2'b01: MB_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]};
835 2'b10: MB_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]};
836 2'b11: MB_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]};
837 default:
838 MB_SEL_O <= #UDLY M_SEL_O;
839 endcase
840 set_cti_a;
841 start_flag <= #UDLY 1'b1;
842 if(!(|data_length))
843 var_length <= #UDLY 1'b1;
844 else
845 var_length <= #UDLY 1'b0;
846 burst_size <= #UDLY 5'h0;
847 burst_cnt <= #UDLY 5'h0;
848 end
849 else
850 begin
851 status <= #UDLY ST_RDFIFO1;
852 end
853 end
854 else
855 begin
856 status <= #UDLY ST_IDLE1;
857 end
858 reg_interrupt_normal <= #UDLY 1'b0;
859 end
860 ST_RDFIFO1:
861 begin
862 if(fifo_empty)
863 begin
864 status <= #UDLY ST_IDLE1;
865 fifo_clear <= #UDLY 1'b0;
866 latch_start <= #UDLY 1'b1;
867 end
868 else
869 fifo_clear <= #UDLY !fifo_clear;
870 end
872 ST_RDADDR1:
873 begin
874 MA_CYC_O <= #UDLY 1'b1;
875 MA_STB_O <= #UDLY 1'b1;
876 set_cti_a;
877 status <= #UDLY ST_READ1;
878 direct_data <= #UDLY 1'b1;
879 end
881 ST_READ1:
882 begin
883 if(!start_flag)
884 write_fifo;
885 if(MA_ACK_I)
886 begin
887 if(start_flag)
888 begin
889 MA_CYC_O <= #UDLY 1'b0;
890 MA_STB_O <= #UDLY 1'b0;
891 MA_CTI_O <= #UDLY 3'h0;
892 MB_CYC_O <= #UDLY 1'b1;
893 MB_STB_O <= #UDLY 1'b1;
894 set_cti_b;
895 status <= #UDLY ST_WRITE1;
896 start_flag <= #UDLY 1'b0;
897 burst_cnt <= #UDLY burst_size;
898 end
899 else
900 begin
901 MA_CYC_O <= #UDLY 1'b0;
902 MA_STB_O <= #UDLY 1'b0;
903 MA_CTI_O <= #UDLY 3'h0;
904 if(!reg_d_con)
905 begin
906 MB_ADR_O <= #UDLY MB_ADR_O + incr_unit;
907 if (incr_unit == 3'b001)
908 MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]};
909 else
910 if (incr_unit == 3'b010)
911 MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]};
912 end
913 status <= #UDLY ST_WRADDR1;
914 burst_cnt <= #UDLY burst_size;
915 end
916 end
917 else if(MA_RTY_I)
918 begin
919 if(var_length)
920 begin
921 MA_CYC_O <= #UDLY 1'b0;
922 MA_STB_O <= #UDLY 1'b0;
923 MA_CTI_O <= #UDLY 3'h0;
924 status <= #UDLY ST_IDLE1;
925 reg_status_normal <= #UDLY 1'b0;
926 reg_interrupt_normal <= #UDLY 1'b1;
927 end
928 end
929 else if(MA_ERR_I)
930 begin
931 MA_CYC_O <= #UDLY 1'b0;
932 MA_STB_O <= #UDLY 1'b0;
933 MA_CTI_O <= #UDLY 3'h0;
934 status <= #UDLY ST_IDLE1;
935 reg_status_normal <= #UDLY 1'b1;
936 reg_interrupt_normal <= #UDLY 1'b1;
937 end
938 end
940 ST_WRADDR1:
941 begin
942 fifo_wr <= #UDLY 1'b0;
943 MB_CYC_O <= #UDLY 1'b1;
944 MB_STB_O <= #UDLY 1'b1;
945 burst_cnt <= #UDLY burst_size;
946 set_cti_b;
947 status <= #UDLY ST_WRITE1;
948 read_fifo;
949 end
951 ST_WRITE1:
952 begin
953 if(fifo_wr)
954 fifo_wr <= #UDLY 1'b0;
955 if(MB_ACK_I)
956 begin
957 direct_data <= #UDLY 1'b0;
958 if(var_length)
959 begin
960 MB_CYC_O <= #UDLY 1'b0;
961 MB_STB_O <= #UDLY 1'b0;
962 MB_CTI_O <= #UDLY 3'h0;
963 if(!reg_s_con)
964 begin
965 MA_ADR_O <= #UDLY MA_ADR_O + incr_unit;
966 if (incr_unit == 3'b001)
967 MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]};
968 else
969 if (incr_unit == 3'b010)
970 MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]};
971 end
972 status <= #UDLY ST_RDADDR1;
973 fifo_rd <= #UDLY 1'b0;
974 burst_cnt <= #UDLY burst_size;
975 end
976 else
977 begin
978 MB_CYC_O <= #UDLY 1'b0;
979 MB_STB_O <= #UDLY 1'b0;
980 MB_CTI_O <= #UDLY 3'h0;
981 reg_cntlg_normal <= #UDLY 1'b1;
982 status <= #UDLY ST_CNTLNGTH1;
983 fifo_rd <= #UDLY 1'b0;
984 burst_cnt <= #UDLY burst_size;
985 end
986 end
987 else if(MB_RTY_I)
988 begin
989 if(var_length)
990 begin
991 MB_CYC_O <= #UDLY 1'b0;
992 MB_STB_O <= #UDLY 1'b0;
993 MB_CTI_O <= #UDLY 3'h0;
994 status <= #UDLY ST_IDLE1;
995 reg_status_normal <= #UDLY 1'b0;
996 reg_interrupt_normal <= #UDLY 1'b1;
997 var_length <= #UDLY 1'b0;
998 fifo_rd <= #UDLY 1'b0;
999 end
1000 end
1001 else if(MB_ERR_I)
1002 begin
1003 MB_CYC_O <= #UDLY 1'b0;
1004 MB_STB_O <= #UDLY 1'b0;
1005 MB_CTI_O <= #UDLY 3'h0;
1006 status <= #UDLY ST_IDLE1;
1007 reg_status_normal <= #UDLY 1'b1;
1008 reg_interrupt_normal <= #UDLY 1'b1;
1009 fifo_rd <= #UDLY 1'b0;
1010 end
1011 end
1013 ST_CNTLNGTH1:
1014 begin
1015 reg_cntlg_normal <= #UDLY 1'b0;
1016 status <= #UDLY ST_JUSTICE1;
1017 end
1019 ST_JUSTICE1:
1020 begin
1021 if(!(|data_length))
1022 begin
1023 status <= #UDLY ST_IDLE1;
1024 reg_status_normal <= #UDLY 1'b0;
1025 reg_interrupt_normal <= #UDLY 1'b1;
1026 end
1027 else
1028 begin
1029 if(!reg_s_con)
1030 begin
1031 MA_ADR_O <= #UDLY MA_ADR_O + incr_unit;
1032 if (incr_unit == 3'b001)
1033 MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]};
1034 else
1035 if (incr_unit == 3'b010)
1036 MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]};
1037 end
1038 status <= #UDLY ST_RDADDR1;
1039 end
1040 end
1042 default:
1043 begin
1044 status <= #UDLY ST_IDLE1;
1045 var_length <= #UDLY 1'b0;
1046 MA_CYC_O <= #UDLY 1'b0;
1047 MA_CTI_O <= #UDLY 3'h0;
1048 MB_CYC_O <= #UDLY 1'b0;
1049 MB_CTI_O <= #UDLY 3'h0;
1050 MA_STB_O <= #UDLY 1'b0;
1051 MB_STB_O <= #UDLY 1'b0;
1052 reg_status_normal <= #UDLY 1'b0;
1053 reg_interrupt_normal <= #UDLY 1'b0;
1054 reg_cntlg_normal <= #UDLY 1'b0;
1055 burst_size <= #UDLY 3'h0;
1056 burst_cnt <= #UDLY 3'h0;
1057 fifo_wr <= #UDLY 1'b0;
1058 fifo_rd <= #UDLY 1'b0;
1059 fifo_clear <= #UDLY 1'b0;
1060 latch_start <= #UDLY 1'b0;
1061 direct_data <= #UDLY 1'b0;
1062 end
1063 endcase
1064 end
1065 end
1067 //Task for generating write enable to the FIFO
1068 task write_fifo;
1069 begin
1070 if(MA_ACK_I)
1071 begin
1072 fifo_wr <= #UDLY 1'b1;
1073 fifo_din <= #UDLY MA_DAT_I;
1074 end
1075 else
1076 begin
1077 fifo_wr <= #UDLY 1'b0;
1078 end
1079 end
1080 endtask
1082 //Task for generating read enable signal to the FIFO
1083 task read_fifo;
1084 begin
1085 fifo_rd <= #UDLY 1'b1;
1086 end
1087 endtask
1089 //Task for setting wishbone CTI signal for read
1090 //master port depending upon whether request is for burst
1091 //transfer or classic cycle.
1092 task set_cti_a;
1093 begin
1094 if(reg_bt2)
1095 begin
1096 if(reg_s_con)
1097 MA_CTI_O <= #UDLY 3'b001;
1098 else
1099 MA_CTI_O <= #UDLY 3'b010;
1100 end
1101 else
1102 MA_CTI_O <= #UDLY 3'b000;
1103 end
1104 endtask
1106 //Task for setting wishbone CTI signal for write
1107 //master port depending upon whether request is for burst
1108 //transfer or classic cycle.
1109 task set_cti_b;
1110 begin
1111 if(reg_bt2) begin
1112 if(reg_d_con)
1113 MB_CTI_O <= #UDLY 3'b001;
1114 else
1115 MB_CTI_O <= #UDLY 3'b010;
1116 end else
1117 MB_CTI_O <= #UDLY 3'b000;
1118 end
1119 endtask
1121 //RdEn
1122 reg fifo_rd_dly;
1123 always @(posedge CLK_I or posedge RST_I)
1124 if(RST_I)
1125 fifo_rd_dly <= #UDLY 1'b0;
1126 else
1127 fifo_rd_dly <= #UDLY fifo_rd;
1129 wire RdEn = fifo_rd & (!fifo_rd_dly | (reg_bt2 ? (burst_cnt2[5:0] != 5'b00000) : (burst_cnt[5:0] != 5'b00000)) & MB_ACK_I) | fifo_clear;
1131 generate
1132 if (lat_family == "SC" || lat_family == "SCM") begin
1134 pmi_fifo_dc #(.pmi_data_width_w(32),
1135 .pmi_data_width_r(32),
1136 .pmi_data_depth_w(32),
1137 .pmi_data_depth_r(32),
1138 .pmi_full_flag(32),
1139 .pmi_empty_flag(0),
1140 .pmi_almost_full_flag(28),
1141 .pmi_almost_empty_flag(4),
1142 .pmi_regmode("noreg"),
1143 .pmi_family(`LATTICE_FAMILY),
1144 .module_type("pmi_fifo_dc"),
1145 .pmi_implementation(FIFO_IMPLEMENTATION))
1146 dma_fifo_dc (
1147 .Data(fifo_din),
1148 .WrClock(CLK_I),
1149 .RdClock(CLK_I),
1150 .WrEn (fifo_wr),
1151 .RdEn (RdEn),
1152 .Reset (RST_I),
1153 .RPReset(RST_I),
1154 .Q (fifo_dout),
1155 .Empty (fifo_empty),
1156 .Full (),
1157 .AlmostEmpty (),
1158 .AlmostFull ());
1162 end else begin
1163 pmi_fifo #(.pmi_data_width(32),
1164 .pmi_data_depth(32),
1165 .pmi_full_flag(32),
1166 .pmi_empty_flag(0),
1167 .pmi_almost_full_flag(28),
1168 .pmi_almost_empty_flag(1),
1169 .pmi_regmode("noreg"),
1170 .pmi_family(`LATTICE_FAMILY),
1171 .module_type("pmi_fifo"),
1172 .pmi_implementation(FIFO_IMPLEMENTATION))
1173 dma_fifo (.Data (fifo_din),
1174 .Clock (CLK_I),
1175 .WrEn (fifo_wr),
1176 .RdEn (RdEn),
1177 .Reset (RST_I),
1178 .Q (fifo_dout),
1179 .Empty (fifo_empty),
1180 .Full (),
1181 .AlmostEmpty (fifo_aempty),
1182 .AlmostFull ());
1183 end
1184 endgenerate
1186 endmodule // MASTER_CTRL
1188 `endif // MASTER_CTRL_FILE