Sat, 06 Aug 2011 01:48:48 +0100
Update to LM32 DMA v3.3
+// Version : 3.2
+// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and
+// : Read/Write Ports can be independently configured.
+// : 2. Support for "retry" on receipt of a WISHBONE RTY. This
+// : retry results in the current burst or classic cycle
+// : being issued again after a retry timeout.
+// : 3. Support for "error" on receipt of a WISHBONE ERR. This
+// : results in the current dma transfer being terminated
+// : and the error is updated within the STATUS CSR.
+// : 4. Support for burst size of 64.
+// :
+// Version : 3.3
+// : Support for MachXO2 added. The MachXO2 only has a FIFO
+// : with separate read/write clocks.
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 // ------------------------------------------------------------------
4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5 // ALL RIGHTS RESERVED
6 // ------------------------------------------------------------------
7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 //
10 // Permission:
11 //
12 // Lattice Semiconductor grants permission to use this code
13 // pursuant to the terms of the Lattice Semiconductor Corporation
14 // Open Source License Agreement.
15 //
16 // Disclaimer:
17 //
18 // Lattice Semiconductor provides no warranty regarding the use or
19 // functionality of this code. It is the user's responsibility to
20 // verify the user’s design for consistency and functionality through
21 // the use of formal verification methods.
22 //
23 // --------------------------------------------------------------------
24 //
25 // Lattice Semiconductor Corporation
26 // 5555 NE Moore Court
27 // Hillsboro, OR 97214
28 // U.S.A
29 //
30 // TEL: 1-800-Lattice (USA and Canada)
31 // 503-286-8001 (other locations)
32 //
33 // web: http://www.latticesemi.com/
34 // email: techsupport@latticesemi.com
35 //
36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LM32 DMA Component
39 // File : wb_dma_ctrl.v
40 // Title : DMA controller top file
41 // Dependencies : None
42 // :
43 // Version : 7.0
44 // : Initial Release
45 // :
46 // Version : 7.0SP2, 3.0
47 // : 1. Read and Write channel of DMA controller are working in
48 // : parallel, due to that now as soon as FIFO is not empty
49 // : write channel of the DMA controller start writing data
50 // : to the slave.
51 // : 2. Burst Size supported by DMA controller is increased to
52 // : support bigger burst (from current value of 4 and 8 to
53 // : 16 and 32). Now 4 different type of burst sizes are
54 // : supported by the DMA controller 4, 8, 16 and 32. For
55 // : this Burst Size field of the control register is
56 // : increased to 2 bits.
57 // : 3. Glitch is removed on the S_ACK_O signal.
58 // :
59 // Version : 3.1
60 // : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec
61 // : which defines alignement of bytes in sub-word transfers.
62 // :
63 // Version : 3.2
64 // : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and
65 // : Read/Write Ports can be independently configured.
66 // : 2. Support for "retry" on receipt of a WISHBONE RTY. This
67 // : retry results in the current burst or classic cycle
68 // : being issued again after a retry timeout.
69 // : 3. Support for "error" on receipt of a WISHBONE ERR. This
70 // : results in the current dma transfer being terminated
71 // : and the error is updated within the STATUS CSR.
72 // : 4. Support for burst size of 64.
73 // :
74 // Version : 3.3
75 // : Support for MachXO2 added. The MachXO2 only has a FIFO
76 // : with separate read/write clocks.
77 // =============================================================================
79 `ifndef MASTER_CTRL_FILE
80 `define MASTER_CTRL_FILE
81 `include "system_conf.v"
82 module MASTER_CTRL
83 #(parameter MA_WB_DAT_WIDTH = 32,
84 parameter MA_WB_ADR_WIDTH = 32,
85 parameter MB_WB_DAT_WIDTH = 32,
86 parameter MB_WB_ADR_WIDTH = 32,
87 parameter S_WB_DAT_WIDTH = 32,
88 parameter FIFO_IMPLEMENTATION = "EBR")
89 (
90 // System clock and reset
91 input CLK_I,
92 input RST_I,
93 // Master read port
94 output reg [MA_WB_ADR_WIDTH-1:0] MA_ADR_O,
95 output reg [MA_WB_DAT_WIDTH/8-1:0] MA_SEL_O,
96 output reg [MA_WB_DAT_WIDTH-1:0] MA_DAT_O,
97 output reg MA_WE_O,
98 output reg MA_STB_O,
99 output reg MA_CYC_O,
100 output reg [2:0] MA_CTI_O,
101 output reg MA_LOCK_O,
102 input [MA_WB_DAT_WIDTH-1:0] MA_DAT_I,
103 input MA_ACK_I,
104 input MA_ERR_I,
105 input MA_RTY_I,
106 // Master write port
107 output reg [MB_WB_ADR_WIDTH-1:0] MB_ADR_O,
108 output reg [MB_WB_DAT_WIDTH/8-1:0] MB_SEL_O,
109 output reg [MB_WB_DAT_WIDTH-1:0] MB_DAT_O,
110 output reg MB_WE_O,
111 output reg MB_STB_O,
112 output reg MB_CYC_O,
113 output reg [2:0] MB_CTI_O,
114 output reg MB_LOCK_O,
115 input MB_ACK_I,
116 input MB_ERR_I,
117 input MB_RTY_I,
118 // Register interface
119 input reg_start,
120 output reg reg_busy,
121 output reg reg_status,
122 output reg reg_interrupt,
123 input reg_bt3, reg_bt2, reg_bt1, reg_bt0,
124 input reg_s_con, reg_d_con,
125 input reg_incw, reg_inchw,
126 input [7:0] reg_rdelay,
127 input [31:0] reg_00_data,
128 input [31:0] reg_04_data,
129 input [31:0] reg_08_data
130 );
132 parameter lat_family = `LATTICE_FAMILY;
133 parameter UDLY = 1;
135 wire [MB_WB_DAT_WIDTH-1:0] fifo_dout;
136 wire fifo_empty, fifo_aempty;
137 reg [MA_WB_DAT_WIDTH-1:0] fifo_din;
139 reg [31:0] xfer_length, xfer_length_nxt;
140 reg [5:0] rburst_count, rburst_count_nxt;
141 reg [5:0] wburst_count, wburst_count_nxt;
142 reg [5:0] save_wburst_count, save_wburst_count_nxt;
143 reg [31:0] raddr_checkpoint, raddr_checkpoint_nxt, waddr_checkpoint, waddr_checkpoint_nxt;
144 reg [7:0] retry_delay, retry_delay_nxt;
145 reg MA_CYC_O_nxt, MA_STB_O_nxt, MA_CYC_O_d;
146 reg [2:0] MA_CTI_O_nxt;
147 reg [MA_WB_ADR_WIDTH-1:0] MA_ADR_O_nxt;
148 reg [MA_WB_DAT_WIDTH/8-1:0] MA_SEL_O_nxt;
149 reg MB_CYC_O_nxt, MB_STB_O_nxt, MB_CYC_O_d;
150 reg [2:0] MB_CTI_O_nxt;
151 reg [MB_WB_ADR_WIDTH-1:0] MB_ADR_O_nxt;
152 reg [MB_WB_DAT_WIDTH/8-1:0] MB_SEL_O_nxt;
153 reg reg_status_nxt;
154 reg burst_start, xfer_done;
155 wire [2:0] iCount;
156 wire [5:0] bCount;
157 wire [8:0] biCount;
159 /*----------------------------------------------------------------------
161 READ State Machine
163 ----------------------------------------------------------------------*/
164 reg [2:0] rstate, rstate_nxt;
165 parameter RD_IDLE = 3'b000;
166 parameter RD_SINGLEA = 3'b001;
167 parameter RD_SINGLEB = 3'b010;
168 parameter RD_SINGLE_RETRY = 3'b011;
169 parameter RD_BURST = 3'b100;
171 always @(/*AUTOSENSE*/MA_ACK_I or MA_ERR_I or MA_RTY_I or MB_ERR_I
172 or MB_RTY_I or burst_start or rburst_count or reg_bt3
173 or reg_start or retry_delay or rstate or xfer_done)
174 casez (rstate)
175 RD_IDLE:
176 if (reg_start && (reg_bt3 == 1'b0))
177 rstate_nxt = RD_SINGLEA;
178 else if (burst_start && reg_bt3)
179 rstate_nxt = RD_BURST;
180 else
181 rstate_nxt = rstate;
183 RD_SINGLEA:
184 if (MA_ACK_I)
185 rstate_nxt = RD_SINGLEB;
186 else if (MA_ERR_I)
187 rstate_nxt = RD_IDLE;
188 else if (MA_RTY_I)
189 rstate_nxt = RD_SINGLE_RETRY;
190 else
191 rstate_nxt = rstate;
193 RD_SINGLEB:
194 if (burst_start)
195 rstate_nxt = RD_SINGLEA;
196 else if (MB_ERR_I || xfer_done)
197 rstate_nxt = RD_IDLE;
198 else if (MB_RTY_I)
199 rstate_nxt = RD_SINGLE_RETRY;
200 else
201 rstate_nxt = rstate;
203 RD_BURST:
204 if (MB_ERR_I || MB_RTY_I || MA_ERR_I || MB_RTY_I || (MA_ACK_I && (rburst_count == 0)))
205 rstate_nxt = RD_IDLE;
206 else
207 rstate_nxt = rstate;
209 RD_SINGLE_RETRY:
210 if (retry_delay == 8'h0)
211 rstate_nxt = RD_SINGLEA;
212 else
213 rstate_nxt = rstate;
215 default:
216 rstate_nxt = RD_IDLE;
217 endcase
219 /*----------------------------------------------------------------------
221 WRITE State Machine
223 ----------------------------------------------------------------------*/
224 reg [3:0] wstate, wstate_nxt;
225 parameter WR_IDLE = 4'b0000;
226 parameter WR_SINGLEA = 4'b0001;
227 parameter WR_SINGLEB = 4'b0010;
228 parameter WR_FIFO_CHECK = 4'b0011;
229 parameter WR_SHORT = 4'b0100;
230 parameter WR_BURST = 4'b0101;
231 parameter WR_SBURST = 4'b0110;
232 parameter WR_SETUPA = 4'b0111;
233 parameter WR_SETUPB = 4'b1000;
234 parameter WR_ERROR = 4'b1001;
235 parameter WR_RETRY = 4'b1010;
237 always @(/*AUTOSENSE*/MA_ERR_I or MA_RTY_I or MB_ACK_I or MB_ERR_I
238 or MB_RTY_I or fifo_aempty or fifo_empty or iCount
239 or reg_bt3 or reg_start or retry_delay or wburst_count
240 or wstate or xfer_length)
241 casez (wstate)
242 WR_IDLE:
243 if (reg_start)
244 wstate_nxt = reg_bt3 ? WR_SETUPA : WR_SINGLEA;
245 else
246 wstate_nxt = wstate;
248 WR_SINGLEA:
249 if (MA_ERR_I)
250 wstate_nxt = WR_IDLE;
251 else if (fifo_empty == 1'b0)
252 wstate_nxt = WR_SINGLEB;
253 else
254 wstate_nxt = wstate;
256 WR_SINGLEB:
257 if (MB_ACK_I)
258 wstate_nxt = (xfer_length == iCount) ? WR_IDLE : WR_SINGLEA;
259 else if (MB_ERR_I)
260 wstate_nxt = WR_IDLE;
261 else if (MB_RTY_I)
262 wstate_nxt = WR_SINGLEA;
263 else
264 wstate_nxt = wstate;
266 WR_FIFO_CHECK:
267 if (MA_ERR_I)
268 wstate_nxt = WR_ERROR;
269 else if (MA_RTY_I)
270 wstate_nxt = WR_RETRY;
271 else
272 if ((fifo_empty == 1'b0) && (wburst_count == 6'h0))
273 wstate_nxt = WR_SHORT;
274 else if ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1))
275 wstate_nxt = WR_BURST;
276 else
277 wstate_nxt = wstate;
279 WR_SHORT:
280 if (MA_ERR_I)
281 wstate_nxt = WR_ERROR;
282 else if (MA_RTY_I)
283 wstate_nxt = WR_RETRY;
284 else
285 if (MB_ACK_I)
286 wstate_nxt = WR_FIFO_CHECK;
287 else if (MB_ERR_I)
288 wstate_nxt = WR_ERROR;
289 else if (MB_RTY_I)
290 wstate_nxt = WR_RETRY;
291 else
292 wstate_nxt = wstate;
294 WR_BURST:
295 if (MA_ERR_I)
296 wstate_nxt = WR_ERROR;
297 else if (MA_RTY_I)
298 wstate_nxt = WR_RETRY;
299 else
300 if (MB_ACK_I)
301 if (fifo_aempty && (wburst_count >= 6'h2))
302 wstate_nxt = WR_SBURST;
303 else if (wburst_count == 6'h0)
304 wstate_nxt = WR_SETUPA;
305 else
306 wstate_nxt = wstate;
307 else if (MB_ERR_I)
308 wstate_nxt = WR_ERROR;
309 else if (MB_RTY_I)
310 wstate_nxt = WR_RETRY;
311 else
312 wstate_nxt = wstate;
314 WR_SBURST:
315 if (MA_ERR_I)
316 wstate_nxt = WR_ERROR;
317 else if (MA_RTY_I)
318 wstate_nxt = WR_RETRY;
319 else
320 if (MB_ACK_I)
321 wstate_nxt = WR_FIFO_CHECK;
322 else if (MB_RTY_I)
323 wstate_nxt = WR_RETRY;
324 else
325 wstate_nxt = wstate;
327 WR_SETUPA:
328 wstate_nxt = WR_SETUPB;
330 WR_SETUPB:
331 wstate_nxt = (wburst_count == 6'h0) ? WR_IDLE : WR_FIFO_CHECK;
333 WR_ERROR:
334 wstate_nxt = fifo_empty ? WR_IDLE : wstate;
336 WR_RETRY:
337 if (fifo_empty && (retry_delay == 8'h0))
338 wstate_nxt = WR_FIFO_CHECK;
339 else
340 wstate_nxt = wstate;
342 default:
343 wstate_nxt = WR_IDLE;
344 endcase
346 /*----------------------------------------------------------------------
347 Status Signals
348 ----------------------------------------------------------------------*/
349 always @(/*AUTOSENSE*/MA_ERR_I or MB_ERR_I or reg_status or wstate
350 or wstate_nxt)
351 begin
352 // Raise and hold busy signal until current DMA transfer is complete
353 reg_busy = (wstate_nxt != WR_IDLE);
355 // Raise and hold error signal until a new DMA transfer is initiated.
356 // Error signal is raised when the WISHBONE cycle results in _ERR_I
357 if ((wstate == WR_IDLE) && (wstate_nxt != WR_IDLE))
358 reg_status_nxt = 1'b0;
359 else if (MA_ERR_I || MB_ERR_I)
360 reg_status_nxt = 1'b1;
361 else
362 reg_status_nxt = reg_status;
364 // Raise interrupt on completion of DMA transfer
365 reg_interrupt = (wstate != WR_IDLE) & (wstate_nxt == WR_IDLE);
366 end
368 /*----------------------------------------------------------------------
369 WISHBONE Read Port
370 ----------------------------------------------------------------------*/
371 always @(/*AUTOSENSE*/MA_ACK_I or MA_ADR_O or MA_CTI_O or MA_CYC_O
372 or MA_CYC_O_d or MA_ERR_I or MA_RTY_I or MA_STB_O
373 or MB_ERR_I or MB_RTY_I or burst_start or iCount
374 or raddr_checkpoint or rburst_count or reg_00_data
375 or reg_bt3 or reg_s_con or reg_start or rstate
376 or rstate_nxt)
377 begin
378 // MA_CYC_O and MA_STB_O
380 // handle all conditions that cause MA_CYC_O to go 0
381 if (((rstate == RD_SINGLEA)
382 && (MA_ACK_I || MA_ERR_I || MA_RTY_I))
383 || ((rstate == RD_BURST)
384 && (MB_ERR_I || MB_RTY_I || (MA_ACK_I && (rburst_count == 6'h0)))))
385 begin
386 MA_CYC_O_nxt = 1'b0;
387 MA_STB_O_nxt = 1'b0;
388 end
389 // handle all conditions that cause MA_CYC_O to go 1
390 else if (((rstate_nxt == RD_SINGLEA)
391 && ((rstate == RD_IDLE) || (rstate == RD_SINGLEB) || (rstate == RD_SINGLE_RETRY)))
392 || ((rstate == RD_BURST) && (MA_CYC_O_d == 1'b0)))
393 begin
394 MA_CYC_O_nxt = 1'b1;
395 MA_STB_O_nxt = 1'b1;
396 end
397 // default: maintain state
398 else
399 begin
400 MA_CYC_O_nxt = MA_CYC_O;
401 MA_STB_O_nxt = MA_STB_O;
402 end
405 // MA_ADR_O
407 // set up first address of the dma transfer
408 if (reg_start)
409 MA_ADR_O_nxt = reg_00_data;
410 else if (reg_s_con == 1'b0)
411 begin
412 // roll back to first address in a burst transfer on a retry
413 if (/*(rstate == RD_BURST) && */MB_RTY_I)
414 MA_ADR_O_nxt = raddr_checkpoint;
415 // increment for every regular transfer
416 else if ((MB_RTY_I == 1'b0)
417 && (((rstate == RD_SINGLEB) && burst_start)
418 || ((rstate == RD_BURST) && MA_ACK_I)))
419 MA_ADR_O_nxt = MA_ADR_O + iCount;
420 else
421 MA_ADR_O_nxt = MA_ADR_O;
422 end
423 else
424 MA_ADR_O_nxt = MA_ADR_O;
427 // MA_CTI_O
429 if (reg_start || burst_start)
430 MA_CTI_O_nxt = reg_bt3 ? (reg_s_con ? 3'b001 : 3'b010) : 3'b000;
431 else if ((rstate == RD_BURST) && (rburst_count == 6'h1) && MA_ACK_I)
432 MA_CTI_O_nxt = 3'b111;
433 else
434 MA_CTI_O_nxt = MA_CTI_O;
437 // Other signals
438 MA_WE_O = 1'b0;
439 MA_DAT_O = 0;
440 MA_LOCK_O = 1'b0;
441 end
443 generate
444 if (MA_WB_DAT_WIDTH == 8) begin
446 always @(*)
447 MA_SEL_O_nxt = 1'b1;
449 end
450 else begin
452 always @(/*AUTOSENSE*/MA_ADR_O_nxt or iCount)
453 begin
454 if (iCount == 1)
455 casez (MA_ADR_O_nxt[1:0])
456 2'b00: MA_SEL_O_nxt = 4'b1000;
457 2'b01: MA_SEL_O_nxt = 4'b0100;
458 2'b10: MA_SEL_O_nxt = 4'b0010;
459 2'b11: MA_SEL_O_nxt = 4'b0001;
460 default:
461 MA_SEL_O_nxt = 4'b1111;
462 endcase
463 else if (iCount == 2)
464 MA_SEL_O_nxt = MA_ADR_O_nxt[1] ? 4'b0011 : 4'b1100;
465 else
466 MA_SEL_O_nxt = 4'b1111;
467 end
469 end
470 endgenerate
473 /*----------------------------------------------------------------------
474 WISHBONE Write Port
475 ----------------------------------------------------------------------*/
476 always @(/*AUTOSENSE*/MA_ERR_I or MA_RTY_I or MB_ACK_I or MB_ADR_O
477 or MB_CTI_O or MB_CYC_O or MB_ERR_I or MB_RTY_I
478 or MB_STB_O or fifo_aempty or fifo_dout or fifo_empty
479 or iCount or reg_04_data or reg_d_con or reg_s_con
480 or reg_start or waddr_checkpoint or wburst_count or wstate
481 or wstate_nxt)
482 begin
483 // MB_CYC_O and MB_STB_O
485 // handle all conditions that cause MB_CYC_O to go 0
486 if (((wstate == WR_SINGLEB)
487 && (MB_ACK_I || MB_ERR_I || MB_RTY_I))
488 || ((MA_ERR_I || MA_RTY_I)
489 && ((wstate == WR_SHORT) || (wstate == WR_FIFO_CHECK) || (wstate == WR_BURST) || (wstate == WR_SBURST)))
490 || ((wstate == WR_BURST)
491 && ((MB_ACK_I && (wburst_count == 6'h0)) || MB_ERR_I || MB_RTY_I))
492 || ((wstate == WR_SBURST)
493 && (MB_ACK_I || MB_ERR_I || MB_RTY_I)))
494 begin
495 MB_CYC_O_nxt = 1'b0;
496 MB_STB_O_nxt = 1'b0;
497 end
498 // handle all conditions that cause MB_CYC_O to go 1
499 else if (((wstate == WR_SINGLEA) && (fifo_empty == 1'b0))
500 || ((wstate == WR_FIFO_CHECK)
501 && (((fifo_empty == 1'b0) && (wburst_count == 6'h0))
502 || ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1)))))
503 begin
504 MB_CYC_O_nxt = 1'b1;
505 MB_STB_O_nxt = 1'b1;
506 end
507 // default: maintain state
508 else
509 begin
510 MB_CYC_O_nxt = MB_CYC_O;
511 MB_STB_O_nxt = MB_STB_O;
512 end
515 // MB_ADR_O
517 // set up first address of the dma transfer
518 if (reg_start)
519 MB_ADR_O_nxt = reg_04_data;
520 else if (reg_d_con == 1'b0)
521 begin
522 // roll back to first address in a burst transfer on a retry
523 if (wstate == WR_RETRY)
524 MB_ADR_O_nxt = waddr_checkpoint;
525 // increment for every regular transfer
526 else if (((wstate == WR_SINGLEB) && MB_ACK_I)
527 || (MB_ACK_I && (MA_RTY_I == 1'b0) && (MA_ERR_I == 1'b0)
528 && ((wstate == WR_SHORT) || (wstate == WR_BURST) || (wstate == WR_SBURST))))
529 MB_ADR_O_nxt = MB_ADR_O + iCount;
530 else
531 MB_ADR_O_nxt = MB_ADR_O;
532 end
533 else
534 MB_ADR_O_nxt = MB_ADR_O;
537 // MB_CTI_O
539 // set up classic wishbone cycle
540 if ((wstate == WR_SINGLEA)
541 || ((wstate == WR_FIFO_CHECK) && (wstate_nxt == WR_SHORT)))
542 MB_CTI_O_nxt = 3'b000;
543 // set up termination of a wishbone burst cycle
544 else if ((wstate == WR_BURST)
545 && ((MB_ACK_I && (wburst_count == 6'h1)) || (wstate_nxt == WR_SBURST)))
546 MB_CTI_O_nxt = 3'b111;
547 // set up wishbone burst (incrementing or constant address)
548 else if (((wstate == WR_FIFO_CHECK) && (wstate_nxt == WR_BURST))
549 || ((wstate == WR_BURST) && MB_ACK_I))
550 MB_CTI_O_nxt = reg_s_con ? 3'b001 : 3'b010;
551 // hold
552 else
553 MB_CTI_O_nxt = MB_CTI_O;
555 // MB_DAT_O
556 MB_DAT_O = fifo_dout;
559 // Other signals
560 MB_WE_O = 1'b1;
561 MB_LOCK_O = 1'b0;
562 end
564 generate
565 if (MB_WB_DAT_WIDTH == 8) begin
567 always @(*)
568 MB_SEL_O_nxt = 1'b1;
570 end
571 else begin
573 always @(/*AUTOSENSE*/MB_ADR_O_nxt or iCount)
574 begin
575 if (iCount == 1)
576 casez (MB_ADR_O_nxt[1:0])
577 2'b00: MB_SEL_O_nxt = 4'b1000;
578 2'b01: MB_SEL_O_nxt = 4'b0100;
579 2'b10: MB_SEL_O_nxt = 4'b0010;
580 2'b11: MB_SEL_O_nxt = 4'b0001;
581 default:
582 MB_SEL_O_nxt = 4'b1111;
583 endcase
584 else if (iCount == 2)
585 MB_SEL_O_nxt = MB_ADR_O_nxt[1] ? 4'b0011 : 4'b1100;
586 else
587 MB_SEL_O_nxt = 4'b1111;
588 end
590 end
591 endgenerate
593 /*----------------------------------------------------------------------
594 Logic to keep track of where we are in the transfer process
595 ----------------------------------------------------------------------*/
596 // Increment Count
597 generate
598 if (S_WB_DAT_WIDTH == 8) begin
599 assign iCount = 3'h1;
600 end
601 else begin
602 assign iCount = reg_incw ? 3'h4 : (reg_inchw ? 3'h2 : 3'h1);
603 end
604 endgenerate
606 // Burst Count
607 assign bCount = (reg_bt3
608 ? (reg_bt2
609 ? 6'h3f
610 : (reg_bt1
611 ? (reg_bt0 ? 6'h1f : 6'h0f)
612 : (reg_bt0 ? 6'h07 : 6'h03)))
613 : 6'h01
614 );
616 // Burst Increment Count
617 assign biCount = (reg_bt3
618 ? (reg_bt2
619 ? iCount<<6
620 : (reg_bt1
621 ? (reg_bt0 ? iCount<<5 : iCount<<4)
622 : (reg_bt0 ? iCount<<3 : iCount<<2)
623 )
624 )
625 : iCount
626 );
628 always @(/*AUTOSENSE*/MA_ACK_I or MB_ACK_I or bCount or biCount
629 or fifo_empty or iCount or rburst_count or reg_08_data
630 or reg_inchw or reg_incw or reg_start or rstate
631 or save_wburst_count or wburst_count or wstate
632 or xfer_length)
633 begin
634 // Transfer Length
635 if (reg_start && (wstate == WR_IDLE))
636 xfer_length_nxt = reg_08_data;
637 else if (MB_ACK_I && (wstate == WR_SINGLEB))
638 xfer_length_nxt = xfer_length - iCount;
639 else if (wstate == WR_SETUPA)
640 xfer_length_nxt = (xfer_length >= biCount) ? (xfer_length - biCount) : 0;
641 else
642 xfer_length_nxt = xfer_length;
644 // Read-side Burst Count
645 if (rstate == RD_IDLE)
646 rburst_count_nxt = wburst_count;
647 else if ((rstate == RD_BURST) && MA_ACK_I)
648 rburst_count_nxt = rburst_count - 1'b1;
649 else
650 rburst_count_nxt = rburst_count;
652 // Write-side Burst Count
653 if (wstate == WR_SETUPA)
654 wburst_count_nxt = ((xfer_length == 0)
655 ? 0
656 : ((xfer_length >= biCount)
657 ? bCount
658 : (xfer_length-1)>>(reg_incw ? 2 : (reg_inchw ? 1 : 0))));
659 else if ((wstate == WR_RETRY) && fifo_empty)
660 wburst_count_nxt = save_wburst_count;
661 else if (MB_ACK_I
662 && ((wstate == WR_SHORT) || (wstate == WR_BURST) || (wstate == WR_SBURST)))
663 wburst_count_nxt = wburst_count - 1'b1;
664 else
665 wburst_count_nxt = wburst_count;
666 end
668 /*----------------------------------------------------------------------
669 Logic to support a burst retry
670 ----------------------------------------------------------------------*/
671 always @(/*AUTOSENSE*/MA_ADR_O or MB_ADR_O or raddr_checkpoint
672 or reg_rdelay or retry_delay or rstate or rstate_nxt
673 or save_wburst_count or waddr_checkpoint
674 or wburst_count_nxt or wstate or wstate_nxt)
675 begin
676 // Write-side Saved Burst Count
677 if (wstate == WR_SETUPA)
678 save_wburst_count_nxt = wburst_count_nxt;
679 else
680 save_wburst_count_nxt = save_wburst_count;
682 // Retry Delay
683 if (((wstate != WR_RETRY) && (wstate_nxt == WR_RETRY))
684 || ((rstate == RD_SINGLEA) && (rstate_nxt == RD_SINGLE_RETRY)))
685 retry_delay_nxt = reg_rdelay;
686 else if ((wstate == WR_RETRY) || (rstate == RD_SINGLE_RETRY))
687 retry_delay_nxt = retry_delay - 1'b1;
688 else
689 retry_delay_nxt = retry_delay;
691 // Read Address Checkpoint
692 if ((rstate == RD_IDLE) && (rstate_nxt == RD_BURST))
693 raddr_checkpoint_nxt = MA_ADR_O;
694 else
695 raddr_checkpoint_nxt = raddr_checkpoint;
697 // Write Address Checkpoint
698 if (wstate == WR_SETUPA)
699 waddr_checkpoint_nxt = MB_ADR_O;
700 else
701 waddr_checkpoint_nxt = waddr_checkpoint;
702 end
704 /*----------------------------------------------------------------------
705 Logic to indicate start/end of transfer and bursts
706 ----------------------------------------------------------------------*/
707 always @(/*AUTOSENSE*/MA_ERR_I or MB_ACK_I or MB_ERR_I or iCount
708 or retry_delay or wburst_count or wstate or xfer_length)
709 begin
710 if (((wstate == WR_SINGLEB) && (xfer_length > iCount) && MB_ACK_I)
711 || ((wstate == WR_SETUPB) && (wburst_count > 0))
712 || ((wstate == WR_RETRY) && (retry_delay == 8'b0)))
713 burst_start = 1'b1;
714 else
715 burst_start = 1'b0;
717 if (MB_ERR_I
718 || MA_ERR_I
719 || ((wstate == WR_SINGLEB) && (xfer_length == iCount) && MB_ACK_I)
720 || ((wstate == WR_SETUPB) && (wburst_count == 0)))
721 xfer_done = 1'b1;
722 else
723 xfer_done = 1'b0;
724 end
726 /*----------------------------------------------------------------------
727 Sequential Logic
728 ----------------------------------------------------------------------*/
729 always @(posedge CLK_I or posedge RST_I)
730 if (RST_I)
731 begin
732 rstate <= #UDLY RD_IDLE;
733 wstate <= #UDLY WR_IDLE;
734 xfer_length <= #UDLY 32'b0;
735 rburst_count <= #UDLY 6'b0;
736 wburst_count <= #UDLY 6'b0;
737 retry_delay <= #UDLY 8'b0;
738 reg_status <= #UDLY 1'b0;
739 MA_CYC_O <= #UDLY 1'b0;
740 MA_CYC_O_d <= #UDLY 1'b0;
741 MA_STB_O <= #UDLY 1'b0;
742 MA_CTI_O <= #UDLY 3'b0;
743 MA_ADR_O <= #UDLY 'b0;
744 MA_SEL_O <= #UDLY 'b0;
745 MB_CYC_O <= #UDLY 1'b0;
746 MB_CYC_O_d <= #UDLY 1'b0;
747 MB_STB_O <= #UDLY 1'b0;
748 MB_CTI_O <= #UDLY 3'b0;
749 MB_ADR_O <= #UDLY 'b0;
750 MB_SEL_O <= #UDLY 'b0;
751 raddr_checkpoint <= #UDLY 32'b0;
752 waddr_checkpoint <= #UDLY 32'b0;
753 save_wburst_count <= #UDLY 6'b0;
754 end
755 else
756 begin
757 rstate <= #UDLY rstate_nxt;
758 wstate <= #UDLY wstate_nxt;
759 xfer_length <= #UDLY xfer_length_nxt;
760 rburst_count <= #UDLY rburst_count_nxt;
761 wburst_count <= #UDLY wburst_count_nxt;
762 retry_delay <= #UDLY retry_delay_nxt;
763 reg_status <= #UDLY reg_status_nxt;
764 MA_CYC_O <= #UDLY MA_CYC_O_nxt;
765 MA_CYC_O_d <= #UDLY MA_CYC_O;
766 MA_STB_O <= #UDLY MA_STB_O_nxt;
767 MA_CTI_O <= #UDLY MA_CTI_O_nxt;
768 MA_ADR_O <= #UDLY MA_ADR_O_nxt;
769 MA_SEL_O <= #UDLY MA_SEL_O_nxt;
770 MB_CYC_O <= #UDLY MB_CYC_O_nxt;
771 MB_CYC_O_d <= #UDLY MB_CYC_O;
772 MB_STB_O <= #UDLY MB_STB_O_nxt;
773 MB_CTI_O <= #UDLY MB_CTI_O_nxt;
774 MB_ADR_O <= #UDLY MB_ADR_O_nxt;
775 MB_SEL_O <= #UDLY MB_SEL_O_nxt;
776 raddr_checkpoint <= #UDLY raddr_checkpoint_nxt;
777 waddr_checkpoint <= #UDLY waddr_checkpoint_nxt;
778 save_wburst_count <= #UDLY save_wburst_count_nxt;
779 end
781 /*----------------------------------------------------------------------
782 FIFO Logic
783 ----------------------------------------------------------------------*/
784 reg fifo_rd_en, fifo_wr_en;
785 always @(/*AUTOSENSE*/MA_ACK_I or MA_DAT_I or MB_ACK_I
786 or fifo_aempty or fifo_empty or rstate or wburst_count
787 or wstate)
788 begin
789 if (((wstate == WR_SINGLEA) && (fifo_empty == 1'b0))
790 || ((wstate == WR_FIFO_CHECK)
791 && (((fifo_empty == 1'b0) && (wburst_count == 6'h0))
792 || ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1))))
793 || ((wstate == WR_BURST)
794 && (/*(MB_CYC_O_d == 1'b0)
795 ||*/ (MB_ACK_I && (wburst_count >= 6'h1))))
796 || ((wstate == WR_ERROR) && (fifo_empty == 1'b0))
797 || ((wstate == WR_RETRY) && (fifo_empty == 1'b0)))
798 fifo_rd_en = 1'b1;
799 else
800 fifo_rd_en = 1'b0;
802 if (MA_ACK_I
803 && ((rstate == RD_SINGLEA) || (rstate == RD_BURST)))
804 fifo_wr_en = 1'b1;
805 else
806 fifo_wr_en = 1'b0;
808 fifo_din = MA_DAT_I;
809 end
811 generate
812 if (lat_family == "SC" || lat_family == "SCM") begin
814 pmi_fifo_dc
815 #(.pmi_data_width_w(MA_WB_DAT_WIDTH),
816 .pmi_data_width_r(MA_WB_DAT_WIDTH),
817 .pmi_data_depth_w(64),
818 .pmi_data_depth_r(64),
819 .pmi_full_flag(64),
820 .pmi_empty_flag(0),
821 .pmi_almost_full_flag(60),
822 .pmi_almost_empty_flag(4),
823 .pmi_regmode("noreg"),
824 .pmi_family(`LATTICE_FAMILY),
825 .module_type("pmi_fifo_dc"),
826 .pmi_implementation(FIFO_IMPLEMENTATION))
827 dma_fifo_dc
828 (
829 .Data(fifo_din),
830 .WrClock (CLK_I),
831 .RdClock (CLK_I),
832 .WrEn (fifo_wr_en),
833 .RdEn (fifo_rd_en),
834 .Reset (RST_I),
835 .RPReset (RST_I),
836 .Q (fifo_dout),
837 .Empty (fifo_empty),
838 .Full (),
839 .AlmostEmpty(),
840 .AlmostFull ());
842 end else if (lat_family == "MachXO2") begin
844 pmi_fifo_dc
845 #(.pmi_data_width_w (MA_WB_DAT_WIDTH),
846 .pmi_data_width_r (MA_WB_DAT_WIDTH),
847 .pmi_data_depth_w (64),
848 .pmi_data_depth_r (64),
849 .pmi_full_flag (64),
850 .pmi_empty_flag (0),
851 .pmi_almost_full_flag (60),
852 .pmi_almost_empty_flag (1),
853 .pmi_regmode ("noreg"),
854 .pmi_family ("XO2"),
855 .module_type ("pmi_fifo_dc"),
856 .pmi_implementation (FIFO_IMPLEMENTATION))
857 dma_fifo
858 (.Data (fifo_din),
859 .WrClock (CLK_I),
860 .RdClock (CLK_I),
861 .WrEn (fifo_wr_en),
862 .RdEn (fifo_rd_en),
863 .Reset (RST_I),
864 .RPReset (RST_I),
865 .Q (fifo_dout),
866 .Empty (fifo_empty),
867 .Full (),
868 .AlmostEmpty(fifo_aempty),
869 .AlmostFull ());
871 end else begin
873 pmi_fifo
874 #(.pmi_data_width(MA_WB_DAT_WIDTH),
875 .pmi_data_depth(64),
876 .pmi_full_flag(64),
877 .pmi_empty_flag(0),
878 .pmi_almost_full_flag(60),
879 .pmi_almost_empty_flag(1),
880 .pmi_regmode("noreg"),
881 .pmi_family(`LATTICE_FAMILY),
882 .module_type("pmi_fifo"),
883 .pmi_implementation(FIFO_IMPLEMENTATION))
884 dma_fifo
885 (.Data (fifo_din),
886 .Clock (CLK_I),
887 .WrEn (fifo_wr_en),
888 .RdEn (fifo_rd_en),
889 .Reset (RST_I),
890 .Q (fifo_dout),
891 .Empty (fifo_empty),
892 .Full (),
893 .AlmostEmpty(fifo_aempty),
894 .AlmostFull ());
896 end
898 endgenerate
900 endmodule
902 `endif // `ifndef MASTER_CTRL_FILE