1.1 --- a/rtl/verilog/master_ctrl.v Fri Aug 13 10:43:05 2010 +0100 1.2 +++ b/rtl/verilog/master_ctrl.v Sat Aug 06 01:48:48 2011 +0100 1.3 @@ -1,1188 +1,902 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 +// ================================================================== 1.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.15 +// ------------------------------------------------------------------ 1.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.17 +// ALL RIGHTS RESERVED 1.18 +// ------------------------------------------------------------------ 1.19 +// 1.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.21 +// 1.22 +// Permission: 1.23 +// 1.24 +// Lattice Semiconductor grants permission to use this code 1.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.26 +// Open Source License Agreement. 1.27 +// 1.28 +// Disclaimer: 1.29 // 1.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.33 -// U.S.A email: techsupport@latticesemi.com 1.34 -// =============================================================================/ 1.35 +// Lattice Semiconductor provides no warranty regarding the use or 1.36 +// functionality of this code. It is the user's responsibility to 1.37 +// verify the user’s design for consistency and functionality through 1.38 +// the use of formal verification methods. 1.39 +// 1.40 +// -------------------------------------------------------------------- 1.41 +// 1.42 +// Lattice Semiconductor Corporation 1.43 +// 5555 NE Moore Court 1.44 +// Hillsboro, OR 97214 1.45 +// U.S.A 1.46 +// 1.47 +// TEL: 1-800-Lattice (USA and Canada) 1.48 +// 503-286-8001 (other locations) 1.49 +// 1.50 +// web: http://www.latticesemi.com/ 1.51 +// email: techsupport@latticesemi.com 1.52 +// 1.53 +// -------------------------------------------------------------------- 1.54 // FILE DETAILS 1.55 // Project : LM32 DMA Component 1.56 -// File : master_ctrl.v 1.57 -// Title : DMA Master controller 1.58 +// File : wb_dma_ctrl.v 1.59 +// Title : DMA controller top file 1.60 // Dependencies : None 1.61 -// 1.62 -// Version 3.1 1.63 -// 1. Make DMA Engine compliant to Rule 3.100 of Wishbone Spec which defines 1.64 -// alignement of bytes in sub-word transfers. 1.65 -// 2. Removed glitch that did not pause the burst write when the read burst 1.66 -// was paused by the "read slave". 1.67 -// 1.68 -// Version 7.0SP2, 3.0 1.69 -// 1. Read and Write channel of DMA controller are working in parallel, 1.70 -// due to that now as soon as FIFO is not empty write channel of the DMA 1.71 -// controller start writing data to the slave. 1.72 -// 2. Burst Size supported by DMA controller is increased to support bigger 1.73 -// burst (from current value of 4 and 8 to 16 and 32). Now 4 different type 1.74 -// of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 1.75 -// For this Burst Size field of the control register is increased to 2 bits. 1.76 -// 3. Glitch is removed on the S_ACK_O signal. 1.77 -// 1.78 -// Version 7.0 1.79 -// 1. Initial Release 1.80 -// 1.81 +// : 1.82 +// Version : 7.0 1.83 +// : Initial Release 1.84 +// : 1.85 +// Version : 7.0SP2, 3.0 1.86 +// : 1. Read and Write channel of DMA controller are working in 1.87 +// : parallel, due to that now as soon as FIFO is not empty 1.88 +// : write channel of the DMA controller start writing data 1.89 +// : to the slave. 1.90 +// : 2. Burst Size supported by DMA controller is increased to 1.91 +// : support bigger burst (from current value of 4 and 8 to 1.92 +// : 16 and 32). Now 4 different type of burst sizes are 1.93 +// : supported by the DMA controller 4, 8, 16 and 32. For 1.94 +// : this Burst Size field of the control register is 1.95 +// : increased to 2 bits. 1.96 +// : 3. Glitch is removed on the S_ACK_O signal. 1.97 +// : 1.98 +// Version : 3.1 1.99 +// : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec 1.100 +// : which defines alignement of bytes in sub-word transfers. 1.101 +// : 1.102 +// Version : 3.2 1.103 +// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and 1.104 +// : Read/Write Ports can be independently configured. 1.105 +// : 2. Support for "retry" on receipt of a WISHBONE RTY. This 1.106 +// : retry results in the current burst or classic cycle 1.107 +// : being issued again after a retry timeout. 1.108 +// : 3. Support for "error" on receipt of a WISHBONE ERR. This 1.109 +// : results in the current dma transfer being terminated 1.110 +// : and the error is updated within the STATUS CSR. 1.111 +// : 4. Support for burst size of 64. 1.112 +// : 1.113 +// Version : 3.3 1.114 +// : Support for MachXO2 added. The MachXO2 only has a FIFO 1.115 +// : with separate read/write clocks. 1.116 // ============================================================================= 1.117 1.118 `ifndef MASTER_CTRL_FILE 1.119 `define MASTER_CTRL_FILE 1.120 `include "system_conf.v" 1.121 module MASTER_CTRL 1.122 - #(parameter LENGTH_WIDTH = 16, 1.123 + #(parameter MA_WB_DAT_WIDTH = 32, 1.124 + parameter MA_WB_ADR_WIDTH = 32, 1.125 + parameter MB_WB_DAT_WIDTH = 32, 1.126 + parameter MB_WB_ADR_WIDTH = 32, 1.127 + parameter S_WB_DAT_WIDTH = 32, 1.128 parameter FIFO_IMPLEMENTATION = "EBR") 1.129 - ( 1.130 - //master read port 1.131 - MA_ADR_O, 1.132 - MA_SEL_O, 1.133 - MA_WE_O, 1.134 - MA_STB_O, 1.135 - MA_CYC_O, 1.136 - MA_CTI_O, 1.137 - MA_LOCK_O, 1.138 - MA_DAT_I, //32bits 1.139 - MA_ACK_I, 1.140 - MA_ERR_I, 1.141 - MA_RTY_I, 1.142 - //master write port 1.143 - MB_ADR_O, 1.144 - MB_SEL_O, 1.145 - MB_DAT_O, //32bits 1.146 - MB_WE_O, 1.147 - MB_STB_O, 1.148 - MB_CYC_O, 1.149 - MB_CTI_O, 1.150 - MB_LOCK_O, 1.151 - MB_ACK_I, 1.152 - MB_ERR_I, 1.153 - MB_RTY_I, 1.154 - //register interface 1.155 - M_SEL_O, 1.156 - reg_start, 1.157 - reg_status, 1.158 - reg_interrupt, 1.159 - reg_busy, 1.160 - data_length, 1.161 - reg_cntlg, 1.162 - reg_bt2,reg_bt1,reg_bt0, 1.163 - incr_unit, 1.164 - reg_s_con, 1.165 - reg_d_con, 1.166 - reg_00_data, 1.167 - reg_04_data, 1.168 - //system clock and reset 1.169 - CLK_I, 1.170 - RST_I 1.171 - ); 1.172 - //master read port 1.173 - output [31:0] MA_ADR_O; 1.174 - output [3:0] MA_SEL_O; 1.175 - output MA_WE_O; 1.176 - output MA_STB_O; 1.177 - output MA_CYC_O; 1.178 - output [2:0] MA_CTI_O; 1.179 - output MA_LOCK_O; 1.180 - input [31:0] MA_DAT_I; //32bits 1.181 - input MA_ACK_I; 1.182 - input MA_ERR_I; 1.183 - input MA_RTY_I; 1.184 - //master write port 1.185 - output [31:0] MB_ADR_O; 1.186 - output [3:0] MB_SEL_O; 1.187 - output [31:0] MB_DAT_O; //32bits 1.188 - output MB_WE_O; 1.189 - output MB_STB_O; 1.190 - output MB_CYC_O; 1.191 - output [2:0] MB_CTI_O; 1.192 - output MB_LOCK_O; 1.193 - input MB_ACK_I; 1.194 - input MB_ERR_I; 1.195 - input MB_RTY_I; 1.196 - 1.197 - //register interface 1.198 - input [3:0] M_SEL_O; 1.199 - input reg_start; 1.200 - output reg_status; 1.201 - output reg_interrupt; 1.202 - output reg_busy; 1.203 - input [LENGTH_WIDTH-1:0] data_length; 1.204 - output reg_cntlg; 1.205 - input reg_bt2,reg_bt1,reg_bt0; 1.206 - input [2:0] incr_unit; 1.207 - input reg_s_con; 1.208 - input reg_d_con; 1.209 - input [31:0] reg_00_data; 1.210 - input [31:0] reg_04_data; 1.211 - //system clock and reset 1.212 - input CLK_I; 1.213 - input RST_I; 1.214 + ( 1.215 + // System clock and reset 1.216 + input CLK_I, 1.217 + input RST_I, 1.218 + // Master read port 1.219 + output reg [MA_WB_ADR_WIDTH-1:0] MA_ADR_O, 1.220 + output reg [MA_WB_DAT_WIDTH/8-1:0] MA_SEL_O, 1.221 + output reg [MA_WB_DAT_WIDTH-1:0] MA_DAT_O, 1.222 + output reg MA_WE_O, 1.223 + output reg MA_STB_O, 1.224 + output reg MA_CYC_O, 1.225 + output reg [2:0] MA_CTI_O, 1.226 + output reg MA_LOCK_O, 1.227 + input [MA_WB_DAT_WIDTH-1:0] MA_DAT_I, 1.228 + input MA_ACK_I, 1.229 + input MA_ERR_I, 1.230 + input MA_RTY_I, 1.231 + // Master write port 1.232 + output reg [MB_WB_ADR_WIDTH-1:0] MB_ADR_O, 1.233 + output reg [MB_WB_DAT_WIDTH/8-1:0] MB_SEL_O, 1.234 + output reg [MB_WB_DAT_WIDTH-1:0] MB_DAT_O, 1.235 + output reg MB_WE_O, 1.236 + output reg MB_STB_O, 1.237 + output reg MB_CYC_O, 1.238 + output reg [2:0] MB_CTI_O, 1.239 + output reg MB_LOCK_O, 1.240 + input MB_ACK_I, 1.241 + input MB_ERR_I, 1.242 + input MB_RTY_I, 1.243 + // Register interface 1.244 + input reg_start, 1.245 + output reg reg_busy, 1.246 + output reg reg_status, 1.247 + output reg reg_interrupt, 1.248 + input reg_bt3, reg_bt2, reg_bt1, reg_bt0, 1.249 + input reg_s_con, reg_d_con, 1.250 + input reg_incw, reg_inchw, 1.251 + input [7:0] reg_rdelay, 1.252 + input [31:0] reg_00_data, 1.253 + input [31:0] reg_04_data, 1.254 + input [31:0] reg_08_data 1.255 + ); 1.256 + 1.257 + parameter lat_family = `LATTICE_FAMILY; 1.258 + parameter UDLY = 1; 1.259 + 1.260 + wire [MB_WB_DAT_WIDTH-1:0] fifo_dout; 1.261 + wire fifo_empty, fifo_aempty; 1.262 + reg [MA_WB_DAT_WIDTH-1:0] fifo_din; 1.263 + 1.264 + reg [31:0] xfer_length, xfer_length_nxt; 1.265 + reg [5:0] rburst_count, rburst_count_nxt; 1.266 + reg [5:0] wburst_count, wburst_count_nxt; 1.267 + reg [5:0] save_wburst_count, save_wburst_count_nxt; 1.268 + reg [31:0] raddr_checkpoint, raddr_checkpoint_nxt, waddr_checkpoint, waddr_checkpoint_nxt; 1.269 + reg [7:0] retry_delay, retry_delay_nxt; 1.270 + reg MA_CYC_O_nxt, MA_STB_O_nxt, MA_CYC_O_d; 1.271 + reg [2:0] MA_CTI_O_nxt; 1.272 + reg [MA_WB_ADR_WIDTH-1:0] MA_ADR_O_nxt; 1.273 + reg [MA_WB_DAT_WIDTH/8-1:0] MA_SEL_O_nxt; 1.274 + reg MB_CYC_O_nxt, MB_STB_O_nxt, MB_CYC_O_d; 1.275 + reg [2:0] MB_CTI_O_nxt; 1.276 + reg [MB_WB_ADR_WIDTH-1:0] MB_ADR_O_nxt; 1.277 + reg [MB_WB_DAT_WIDTH/8-1:0] MB_SEL_O_nxt; 1.278 + reg reg_status_nxt; 1.279 + reg burst_start, xfer_done; 1.280 + wire [2:0] iCount; 1.281 + wire [5:0] bCount; 1.282 + wire [8:0] biCount; 1.283 + 1.284 + /*---------------------------------------------------------------------- 1.285 + 1.286 + READ State Machine 1.287 + 1.288 + ----------------------------------------------------------------------*/ 1.289 + reg [2:0] rstate, rstate_nxt; 1.290 + parameter RD_IDLE = 3'b000; 1.291 + parameter RD_SINGLEA = 3'b001; 1.292 + parameter RD_SINGLEB = 3'b010; 1.293 + parameter RD_SINGLE_RETRY = 3'b011; 1.294 + parameter RD_BURST = 3'b100; 1.295 + 1.296 + always @(/*AUTOSENSE*/MA_ACK_I or MA_ERR_I or MA_RTY_I or MB_ERR_I 1.297 + or MB_RTY_I or burst_start or rburst_count or reg_bt3 1.298 + or reg_start or retry_delay or rstate or xfer_done) 1.299 + casez (rstate) 1.300 + RD_IDLE: 1.301 + if (reg_start && (reg_bt3 == 1'b0)) 1.302 + rstate_nxt = RD_SINGLEA; 1.303 + else if (burst_start && reg_bt3) 1.304 + rstate_nxt = RD_BURST; 1.305 + else 1.306 + rstate_nxt = rstate; 1.307 + 1.308 + RD_SINGLEA: 1.309 + if (MA_ACK_I) 1.310 + rstate_nxt = RD_SINGLEB; 1.311 + else if (MA_ERR_I) 1.312 + rstate_nxt = RD_IDLE; 1.313 + else if (MA_RTY_I) 1.314 + rstate_nxt = RD_SINGLE_RETRY; 1.315 + else 1.316 + rstate_nxt = rstate; 1.317 + 1.318 + RD_SINGLEB: 1.319 + if (burst_start) 1.320 + rstate_nxt = RD_SINGLEA; 1.321 + else if (MB_ERR_I || xfer_done) 1.322 + rstate_nxt = RD_IDLE; 1.323 + else if (MB_RTY_I) 1.324 + rstate_nxt = RD_SINGLE_RETRY; 1.325 + else 1.326 + rstate_nxt = rstate; 1.327 + 1.328 + RD_BURST: 1.329 + if (MB_ERR_I || MB_RTY_I || MA_ERR_I || MB_RTY_I || (MA_ACK_I && (rburst_count == 0))) 1.330 + rstate_nxt = RD_IDLE; 1.331 + else 1.332 + rstate_nxt = rstate; 1.333 + 1.334 + RD_SINGLE_RETRY: 1.335 + if (retry_delay == 8'h0) 1.336 + rstate_nxt = RD_SINGLEA; 1.337 + else 1.338 + rstate_nxt = rstate; 1.339 + 1.340 + default: 1.341 + rstate_nxt = RD_IDLE; 1.342 + endcase 1.343 + 1.344 + /*---------------------------------------------------------------------- 1.345 + 1.346 + WRITE State Machine 1.347 + 1.348 + ----------------------------------------------------------------------*/ 1.349 + reg [3:0] wstate, wstate_nxt; 1.350 + parameter WR_IDLE = 4'b0000; 1.351 + parameter WR_SINGLEA = 4'b0001; 1.352 + parameter WR_SINGLEB = 4'b0010; 1.353 + parameter WR_FIFO_CHECK = 4'b0011; 1.354 + parameter WR_SHORT = 4'b0100; 1.355 + parameter WR_BURST = 4'b0101; 1.356 + parameter WR_SBURST = 4'b0110; 1.357 + parameter WR_SETUPA = 4'b0111; 1.358 + parameter WR_SETUPB = 4'b1000; 1.359 + parameter WR_ERROR = 4'b1001; 1.360 + parameter WR_RETRY = 4'b1010; 1.361 + 1.362 + always @(/*AUTOSENSE*/MA_ERR_I or MA_RTY_I or MB_ACK_I or MB_ERR_I 1.363 + or MB_RTY_I or fifo_aempty or fifo_empty or iCount 1.364 + or reg_bt3 or reg_start or retry_delay or wburst_count 1.365 + or wstate or xfer_length) 1.366 + casez (wstate) 1.367 + WR_IDLE: 1.368 + if (reg_start) 1.369 + wstate_nxt = reg_bt3 ? WR_SETUPA : WR_SINGLEA; 1.370 + else 1.371 + wstate_nxt = wstate; 1.372 + 1.373 + WR_SINGLEA: 1.374 + if (MA_ERR_I) 1.375 + wstate_nxt = WR_IDLE; 1.376 + else if (fifo_empty == 1'b0) 1.377 + wstate_nxt = WR_SINGLEB; 1.378 + else 1.379 + wstate_nxt = wstate; 1.380 + 1.381 + WR_SINGLEB: 1.382 + if (MB_ACK_I) 1.383 + wstate_nxt = (xfer_length == iCount) ? WR_IDLE : WR_SINGLEA; 1.384 + else if (MB_ERR_I) 1.385 + wstate_nxt = WR_IDLE; 1.386 + else if (MB_RTY_I) 1.387 + wstate_nxt = WR_SINGLEA; 1.388 + else 1.389 + wstate_nxt = wstate; 1.390 + 1.391 + WR_FIFO_CHECK: 1.392 + if (MA_ERR_I) 1.393 + wstate_nxt = WR_ERROR; 1.394 + else if (MA_RTY_I) 1.395 + wstate_nxt = WR_RETRY; 1.396 + else 1.397 + if ((fifo_empty == 1'b0) && (wburst_count == 6'h0)) 1.398 + wstate_nxt = WR_SHORT; 1.399 + else if ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1)) 1.400 + wstate_nxt = WR_BURST; 1.401 + else 1.402 + wstate_nxt = wstate; 1.403 + 1.404 + WR_SHORT: 1.405 + if (MA_ERR_I) 1.406 + wstate_nxt = WR_ERROR; 1.407 + else if (MA_RTY_I) 1.408 + wstate_nxt = WR_RETRY; 1.409 + else 1.410 + if (MB_ACK_I) 1.411 + wstate_nxt = WR_FIFO_CHECK; 1.412 + else if (MB_ERR_I) 1.413 + wstate_nxt = WR_ERROR; 1.414 + else if (MB_RTY_I) 1.415 + wstate_nxt = WR_RETRY; 1.416 + else 1.417 + wstate_nxt = wstate; 1.418 + 1.419 + WR_BURST: 1.420 + if (MA_ERR_I) 1.421 + wstate_nxt = WR_ERROR; 1.422 + else if (MA_RTY_I) 1.423 + wstate_nxt = WR_RETRY; 1.424 + else 1.425 + if (MB_ACK_I) 1.426 + if (fifo_aempty && (wburst_count >= 6'h2)) 1.427 + wstate_nxt = WR_SBURST; 1.428 + else if (wburst_count == 6'h0) 1.429 + wstate_nxt = WR_SETUPA; 1.430 + else 1.431 + wstate_nxt = wstate; 1.432 + else if (MB_ERR_I) 1.433 + wstate_nxt = WR_ERROR; 1.434 + else if (MB_RTY_I) 1.435 + wstate_nxt = WR_RETRY; 1.436 + else 1.437 + wstate_nxt = wstate; 1.438 + 1.439 + WR_SBURST: 1.440 + if (MA_ERR_I) 1.441 + wstate_nxt = WR_ERROR; 1.442 + else if (MA_RTY_I) 1.443 + wstate_nxt = WR_RETRY; 1.444 + else 1.445 + if (MB_ACK_I) 1.446 + wstate_nxt = WR_FIFO_CHECK; 1.447 + else if (MB_RTY_I) 1.448 + wstate_nxt = WR_RETRY; 1.449 + else 1.450 + wstate_nxt = wstate; 1.451 + 1.452 + WR_SETUPA: 1.453 + wstate_nxt = WR_SETUPB; 1.454 + 1.455 + WR_SETUPB: 1.456 + wstate_nxt = (wburst_count == 6'h0) ? WR_IDLE : WR_FIFO_CHECK; 1.457 + 1.458 + WR_ERROR: 1.459 + wstate_nxt = fifo_empty ? WR_IDLE : wstate; 1.460 + 1.461 + WR_RETRY: 1.462 + if (fifo_empty && (retry_delay == 8'h0)) 1.463 + wstate_nxt = WR_FIFO_CHECK; 1.464 + else 1.465 + wstate_nxt = wstate; 1.466 + 1.467 + default: 1.468 + wstate_nxt = WR_IDLE; 1.469 + endcase 1.470 + 1.471 + /*---------------------------------------------------------------------- 1.472 + Status Signals 1.473 + ----------------------------------------------------------------------*/ 1.474 + always @(/*AUTOSENSE*/MA_ERR_I or MB_ERR_I or reg_status or wstate 1.475 + or wstate_nxt) 1.476 + begin 1.477 + // Raise and hold busy signal until current DMA transfer is complete 1.478 + reg_busy = (wstate_nxt != WR_IDLE); 1.479 + 1.480 + // Raise and hold error signal until a new DMA transfer is initiated. 1.481 + // Error signal is raised when the WISHBONE cycle results in _ERR_I 1.482 + if ((wstate == WR_IDLE) && (wstate_nxt != WR_IDLE)) 1.483 + reg_status_nxt = 1'b0; 1.484 + else if (MA_ERR_I || MB_ERR_I) 1.485 + reg_status_nxt = 1'b1; 1.486 + else 1.487 + reg_status_nxt = reg_status; 1.488 + 1.489 + // Raise interrupt on completion of DMA transfer 1.490 + reg_interrupt = (wstate != WR_IDLE) & (wstate_nxt == WR_IDLE); 1.491 + end 1.492 + 1.493 + /*---------------------------------------------------------------------- 1.494 + WISHBONE Read Port 1.495 + ----------------------------------------------------------------------*/ 1.496 + always @(/*AUTOSENSE*/MA_ACK_I or MA_ADR_O or MA_CTI_O or MA_CYC_O 1.497 + or MA_CYC_O_d or MA_ERR_I or MA_RTY_I or MA_STB_O 1.498 + or MB_ERR_I or MB_RTY_I or burst_start or iCount 1.499 + or raddr_checkpoint or rburst_count or reg_00_data 1.500 + or reg_bt3 or reg_s_con or reg_start or rstate 1.501 + or rstate_nxt) 1.502 + begin 1.503 + // MA_CYC_O and MA_STB_O 1.504 + 1.505 + // handle all conditions that cause MA_CYC_O to go 0 1.506 + if (((rstate == RD_SINGLEA) 1.507 + && (MA_ACK_I || MA_ERR_I || MA_RTY_I)) 1.508 + || ((rstate == RD_BURST) 1.509 + && (MB_ERR_I || MB_RTY_I || (MA_ACK_I && (rburst_count == 6'h0))))) 1.510 + begin 1.511 + MA_CYC_O_nxt = 1'b0; 1.512 + MA_STB_O_nxt = 1'b0; 1.513 + end 1.514 + // handle all conditions that cause MA_CYC_O to go 1 1.515 + else if (((rstate_nxt == RD_SINGLEA) 1.516 + && ((rstate == RD_IDLE) || (rstate == RD_SINGLEB) || (rstate == RD_SINGLE_RETRY))) 1.517 + || ((rstate == RD_BURST) && (MA_CYC_O_d == 1'b0))) 1.518 + begin 1.519 + MA_CYC_O_nxt = 1'b1; 1.520 + MA_STB_O_nxt = 1'b1; 1.521 + end 1.522 + // default: maintain state 1.523 + else 1.524 + begin 1.525 + MA_CYC_O_nxt = MA_CYC_O; 1.526 + MA_STB_O_nxt = MA_STB_O; 1.527 + end 1.528 + 1.529 + 1.530 + // MA_ADR_O 1.531 + 1.532 + // set up first address of the dma transfer 1.533 + if (reg_start) 1.534 + MA_ADR_O_nxt = reg_00_data; 1.535 + else if (reg_s_con == 1'b0) 1.536 + begin 1.537 + // roll back to first address in a burst transfer on a retry 1.538 + if (/*(rstate == RD_BURST) && */MB_RTY_I) 1.539 + MA_ADR_O_nxt = raddr_checkpoint; 1.540 + // increment for every regular transfer 1.541 + else if ((MB_RTY_I == 1'b0) 1.542 + && (((rstate == RD_SINGLEB) && burst_start) 1.543 + || ((rstate == RD_BURST) && MA_ACK_I))) 1.544 + MA_ADR_O_nxt = MA_ADR_O + iCount; 1.545 + else 1.546 + MA_ADR_O_nxt = MA_ADR_O; 1.547 + end 1.548 + else 1.549 + MA_ADR_O_nxt = MA_ADR_O; 1.550 + 1.551 + 1.552 + // MA_CTI_O 1.553 + 1.554 + if (reg_start || burst_start) 1.555 + MA_CTI_O_nxt = reg_bt3 ? (reg_s_con ? 3'b001 : 3'b010) : 3'b000; 1.556 + else if ((rstate == RD_BURST) && (rburst_count == 6'h1) && MA_ACK_I) 1.557 + MA_CTI_O_nxt = 3'b111; 1.558 + else 1.559 + MA_CTI_O_nxt = MA_CTI_O; 1.560 + 1.561 + 1.562 + // Other signals 1.563 + MA_WE_O = 1'b0; 1.564 + MA_DAT_O = 0; 1.565 + MA_LOCK_O = 1'b0; 1.566 + end 1.567 + 1.568 + generate 1.569 + if (MA_WB_DAT_WIDTH == 8) begin 1.570 + 1.571 + always @(*) 1.572 + MA_SEL_O_nxt = 1'b1; 1.573 + 1.574 + end 1.575 + else begin 1.576 + 1.577 + always @(/*AUTOSENSE*/MA_ADR_O_nxt or iCount) 1.578 + begin 1.579 + if (iCount == 1) 1.580 + casez (MA_ADR_O_nxt[1:0]) 1.581 + 2'b00: MA_SEL_O_nxt = 4'b1000; 1.582 + 2'b01: MA_SEL_O_nxt = 4'b0100; 1.583 + 2'b10: MA_SEL_O_nxt = 4'b0010; 1.584 + 2'b11: MA_SEL_O_nxt = 4'b0001; 1.585 + default: 1.586 + MA_SEL_O_nxt = 4'b1111; 1.587 + endcase 1.588 + else if (iCount == 2) 1.589 + MA_SEL_O_nxt = MA_ADR_O_nxt[1] ? 4'b0011 : 4'b1100; 1.590 + else 1.591 + MA_SEL_O_nxt = 4'b1111; 1.592 + end 1.593 + 1.594 + end 1.595 + endgenerate 1.596 + 1.597 + 1.598 + /*---------------------------------------------------------------------- 1.599 + WISHBONE Write Port 1.600 + ----------------------------------------------------------------------*/ 1.601 + always @(/*AUTOSENSE*/MA_ERR_I or MA_RTY_I or MB_ACK_I or MB_ADR_O 1.602 + or MB_CTI_O or MB_CYC_O or MB_ERR_I or MB_RTY_I 1.603 + or MB_STB_O or fifo_aempty or fifo_dout or fifo_empty 1.604 + or iCount or reg_04_data or reg_d_con or reg_s_con 1.605 + or reg_start or waddr_checkpoint or wburst_count or wstate 1.606 + or wstate_nxt) 1.607 + begin 1.608 + // MB_CYC_O and MB_STB_O 1.609 + 1.610 + // handle all conditions that cause MB_CYC_O to go 0 1.611 + if (((wstate == WR_SINGLEB) 1.612 + && (MB_ACK_I || MB_ERR_I || MB_RTY_I)) 1.613 + || ((MA_ERR_I || MA_RTY_I) 1.614 + && ((wstate == WR_SHORT) || (wstate == WR_FIFO_CHECK) || (wstate == WR_BURST) || (wstate == WR_SBURST))) 1.615 + || ((wstate == WR_BURST) 1.616 + && ((MB_ACK_I && (wburst_count == 6'h0)) || MB_ERR_I || MB_RTY_I)) 1.617 + || ((wstate == WR_SBURST) 1.618 + && (MB_ACK_I || MB_ERR_I || MB_RTY_I))) 1.619 + begin 1.620 + MB_CYC_O_nxt = 1'b0; 1.621 + MB_STB_O_nxt = 1'b0; 1.622 + end 1.623 + // handle all conditions that cause MB_CYC_O to go 1 1.624 + else if (((wstate == WR_SINGLEA) && (fifo_empty == 1'b0)) 1.625 + || ((wstate == WR_FIFO_CHECK) 1.626 + && (((fifo_empty == 1'b0) && (wburst_count == 6'h0)) 1.627 + || ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1))))) 1.628 + begin 1.629 + MB_CYC_O_nxt = 1'b1; 1.630 + MB_STB_O_nxt = 1'b1; 1.631 + end 1.632 + // default: maintain state 1.633 + else 1.634 + begin 1.635 + MB_CYC_O_nxt = MB_CYC_O; 1.636 + MB_STB_O_nxt = MB_STB_O; 1.637 + end 1.638 + 1.639 + 1.640 + // MB_ADR_O 1.641 + 1.642 + // set up first address of the dma transfer 1.643 + if (reg_start) 1.644 + MB_ADR_O_nxt = reg_04_data; 1.645 + else if (reg_d_con == 1'b0) 1.646 + begin 1.647 + // roll back to first address in a burst transfer on a retry 1.648 + if (wstate == WR_RETRY) 1.649 + MB_ADR_O_nxt = waddr_checkpoint; 1.650 + // increment for every regular transfer 1.651 + else if (((wstate == WR_SINGLEB) && MB_ACK_I) 1.652 + || (MB_ACK_I && (MA_RTY_I == 1'b0) && (MA_ERR_I == 1'b0) 1.653 + && ((wstate == WR_SHORT) || (wstate == WR_BURST) || (wstate == WR_SBURST)))) 1.654 + MB_ADR_O_nxt = MB_ADR_O + iCount; 1.655 + else 1.656 + MB_ADR_O_nxt = MB_ADR_O; 1.657 + end 1.658 + else 1.659 + MB_ADR_O_nxt = MB_ADR_O; 1.660 + 1.661 + 1.662 + // MB_CTI_O 1.663 + 1.664 + // set up classic wishbone cycle 1.665 + if ((wstate == WR_SINGLEA) 1.666 + || ((wstate == WR_FIFO_CHECK) && (wstate_nxt == WR_SHORT))) 1.667 + MB_CTI_O_nxt = 3'b000; 1.668 + // set up termination of a wishbone burst cycle 1.669 + else if ((wstate == WR_BURST) 1.670 + && ((MB_ACK_I && (wburst_count == 6'h1)) || (wstate_nxt == WR_SBURST))) 1.671 + MB_CTI_O_nxt = 3'b111; 1.672 + // set up wishbone burst (incrementing or constant address) 1.673 + else if (((wstate == WR_FIFO_CHECK) && (wstate_nxt == WR_BURST)) 1.674 + || ((wstate == WR_BURST) && MB_ACK_I)) 1.675 + MB_CTI_O_nxt = reg_s_con ? 3'b001 : 3'b010; 1.676 + // hold 1.677 + else 1.678 + MB_CTI_O_nxt = MB_CTI_O; 1.679 + 1.680 + // MB_DAT_O 1.681 + MB_DAT_O = fifo_dout; 1.682 + 1.683 + 1.684 + // Other signals 1.685 + MB_WE_O = 1'b1; 1.686 + MB_LOCK_O = 1'b0; 1.687 + end 1.688 + 1.689 + generate 1.690 + if (MB_WB_DAT_WIDTH == 8) begin 1.691 + 1.692 + always @(*) 1.693 + MB_SEL_O_nxt = 1'b1; 1.694 + 1.695 + end 1.696 + else begin 1.697 + 1.698 + always @(/*AUTOSENSE*/MB_ADR_O_nxt or iCount) 1.699 + begin 1.700 + if (iCount == 1) 1.701 + casez (MB_ADR_O_nxt[1:0]) 1.702 + 2'b00: MB_SEL_O_nxt = 4'b1000; 1.703 + 2'b01: MB_SEL_O_nxt = 4'b0100; 1.704 + 2'b10: MB_SEL_O_nxt = 4'b0010; 1.705 + 2'b11: MB_SEL_O_nxt = 4'b0001; 1.706 + default: 1.707 + MB_SEL_O_nxt = 4'b1111; 1.708 + endcase 1.709 + else if (iCount == 2) 1.710 + MB_SEL_O_nxt = MB_ADR_O_nxt[1] ? 4'b0011 : 4'b1100; 1.711 + else 1.712 + MB_SEL_O_nxt = 4'b1111; 1.713 + end 1.714 + 1.715 + end 1.716 + endgenerate 1.717 + 1.718 + /*---------------------------------------------------------------------- 1.719 + Logic to keep track of where we are in the transfer process 1.720 + ----------------------------------------------------------------------*/ 1.721 + // Increment Count 1.722 + generate 1.723 + if (S_WB_DAT_WIDTH == 8) begin 1.724 + assign iCount = 3'h1; 1.725 + end 1.726 + else begin 1.727 + assign iCount = reg_incw ? 3'h4 : (reg_inchw ? 3'h2 : 3'h1); 1.728 + end 1.729 + endgenerate 1.730 + 1.731 + // Burst Count 1.732 + assign bCount = (reg_bt3 1.733 + ? (reg_bt2 1.734 + ? 6'h3f 1.735 + : (reg_bt1 1.736 + ? (reg_bt0 ? 6'h1f : 6'h0f) 1.737 + : (reg_bt0 ? 6'h07 : 6'h03))) 1.738 + : 6'h01 1.739 + ); 1.740 + 1.741 + // Burst Increment Count 1.742 + assign biCount = (reg_bt3 1.743 + ? (reg_bt2 1.744 + ? iCount<<6 1.745 + : (reg_bt1 1.746 + ? (reg_bt0 ? iCount<<5 : iCount<<4) 1.747 + : (reg_bt0 ? iCount<<3 : iCount<<2) 1.748 + ) 1.749 + ) 1.750 + : iCount 1.751 + ); 1.752 + 1.753 + always @(/*AUTOSENSE*/MA_ACK_I or MB_ACK_I or bCount or biCount 1.754 + or fifo_empty or iCount or rburst_count or reg_08_data 1.755 + or reg_inchw or reg_incw or reg_start or rstate 1.756 + or save_wburst_count or wburst_count or wstate 1.757 + or xfer_length) 1.758 + begin 1.759 + // Transfer Length 1.760 + if (reg_start && (wstate == WR_IDLE)) 1.761 + xfer_length_nxt = reg_08_data; 1.762 + else if (MB_ACK_I && (wstate == WR_SINGLEB)) 1.763 + xfer_length_nxt = xfer_length - iCount; 1.764 + else if (wstate == WR_SETUPA) 1.765 + xfer_length_nxt = (xfer_length >= biCount) ? (xfer_length - biCount) : 0; 1.766 + else 1.767 + xfer_length_nxt = xfer_length; 1.768 + 1.769 + // Read-side Burst Count 1.770 + if (rstate == RD_IDLE) 1.771 + rburst_count_nxt = wburst_count; 1.772 + else if ((rstate == RD_BURST) && MA_ACK_I) 1.773 + rburst_count_nxt = rburst_count - 1'b1; 1.774 + else 1.775 + rburst_count_nxt = rburst_count; 1.776 + 1.777 + // Write-side Burst Count 1.778 + if (wstate == WR_SETUPA) 1.779 + wburst_count_nxt = ((xfer_length == 0) 1.780 + ? 0 1.781 + : ((xfer_length >= biCount) 1.782 + ? bCount 1.783 + : (xfer_length-1)>>(reg_incw ? 2 : (reg_inchw ? 1 : 0)))); 1.784 + else if ((wstate == WR_RETRY) && fifo_empty) 1.785 + wburst_count_nxt = save_wburst_count; 1.786 + else if (MB_ACK_I 1.787 + && ((wstate == WR_SHORT) || (wstate == WR_BURST) || (wstate == WR_SBURST))) 1.788 + wburst_count_nxt = wburst_count - 1'b1; 1.789 + else 1.790 + wburst_count_nxt = wburst_count; 1.791 + end 1.792 + 1.793 + /*---------------------------------------------------------------------- 1.794 + Logic to support a burst retry 1.795 + ----------------------------------------------------------------------*/ 1.796 + always @(/*AUTOSENSE*/MA_ADR_O or MB_ADR_O or raddr_checkpoint 1.797 + or reg_rdelay or retry_delay or rstate or rstate_nxt 1.798 + or save_wburst_count or waddr_checkpoint 1.799 + or wburst_count_nxt or wstate or wstate_nxt) 1.800 + begin 1.801 + // Write-side Saved Burst Count 1.802 + if (wstate == WR_SETUPA) 1.803 + save_wburst_count_nxt = wburst_count_nxt; 1.804 + else 1.805 + save_wburst_count_nxt = save_wburst_count; 1.806 + 1.807 + // Retry Delay 1.808 + if (((wstate != WR_RETRY) && (wstate_nxt == WR_RETRY)) 1.809 + || ((rstate == RD_SINGLEA) && (rstate_nxt == RD_SINGLE_RETRY))) 1.810 + retry_delay_nxt = reg_rdelay; 1.811 + else if ((wstate == WR_RETRY) || (rstate == RD_SINGLE_RETRY)) 1.812 + retry_delay_nxt = retry_delay - 1'b1; 1.813 + else 1.814 + retry_delay_nxt = retry_delay; 1.815 + 1.816 + // Read Address Checkpoint 1.817 + if ((rstate == RD_IDLE) && (rstate_nxt == RD_BURST)) 1.818 + raddr_checkpoint_nxt = MA_ADR_O; 1.819 + else 1.820 + raddr_checkpoint_nxt = raddr_checkpoint; 1.821 + 1.822 + // Write Address Checkpoint 1.823 + if (wstate == WR_SETUPA) 1.824 + waddr_checkpoint_nxt = MB_ADR_O; 1.825 + else 1.826 + waddr_checkpoint_nxt = waddr_checkpoint; 1.827 + end 1.828 + 1.829 + /*---------------------------------------------------------------------- 1.830 + Logic to indicate start/end of transfer and bursts 1.831 + ----------------------------------------------------------------------*/ 1.832 + always @(/*AUTOSENSE*/MA_ERR_I or MB_ACK_I or MB_ERR_I or iCount 1.833 + or retry_delay or wburst_count or wstate or xfer_length) 1.834 + begin 1.835 + if (((wstate == WR_SINGLEB) && (xfer_length > iCount) && MB_ACK_I) 1.836 + || ((wstate == WR_SETUPB) && (wburst_count > 0)) 1.837 + || ((wstate == WR_RETRY) && (retry_delay == 8'b0))) 1.838 + burst_start = 1'b1; 1.839 + else 1.840 + burst_start = 1'b0; 1.841 + 1.842 + if (MB_ERR_I 1.843 + || MA_ERR_I 1.844 + || ((wstate == WR_SINGLEB) && (xfer_length == iCount) && MB_ACK_I) 1.845 + || ((wstate == WR_SETUPB) && (wburst_count == 0))) 1.846 + xfer_done = 1'b1; 1.847 + else 1.848 + xfer_done = 1'b0; 1.849 + end 1.850 1.851 - parameter lat_family = `LATTICE_FAMILY; 1.852 - parameter UDLY = 1; 1.853 - //Read FSM States encoding 1.854 - parameter ST_IDLE = 3'b000; 1.855 - parameter ST_READ = 3'b001; 1.856 - parameter ST_RDADDR = 3'b010; 1.857 - parameter ST_RDFIFO = 3'b011; 1.858 - parameter ST_WAIT_WRITE_FINISH = 3'b100; 1.859 - 1.860 - //Write FSM States encoding 1.861 - parameter ST_WRITE_IDLE = 4'b0000; 1.862 - parameter ST_WRITE = 4'b0001; 1.863 - parameter ST_WRADDR = 4'b0010; 1.864 - parameter ST_CNTLNGTH = 4'b0011; 1.865 - parameter ST_JUSTICE = 4'b0100; 1.866 - parameter ST_FIFO_EMPTY = 4'b0101; 1.867 - parameter ST_WRITE_WAIT = 4'b0110; 1.868 - parameter ST_FIFO_AEMPTY = 4'b1010; 1.869 - parameter ST_FIFO_RESUME = 4'b1000; 1.870 - 1.871 - // FSM for normal data transfer 1.872 - parameter ST_IDLE1 = 3'b000; 1.873 - parameter ST_READ1 = 3'b001; 1.874 - parameter ST_WRITE1 = 3'b010; 1.875 - parameter ST_RDADDR1 = 3'b011; 1.876 - parameter ST_WRADDR1 = 3'b100; 1.877 - parameter ST_CNTLNGTH1 = 3'b101; 1.878 - parameter ST_JUSTICE1 = 3'b110; 1.879 - parameter ST_RDFIFO1 = 3'b111; 1.880 - reg [2:0] status; 1.881 - reg var_length; 1.882 - 1.883 - 1.884 - //fifo status 1.885 - 1.886 - reg [2:0] status1; 1.887 - reg [3:0] status2; 1.888 - reg var_length2; 1.889 - reg var_length1; 1.890 - reg MA_STB_O; 1.891 - reg MB_STB_O; 1.892 - reg MA_CYC_O; 1.893 - reg MB_CYC_O; 1.894 - reg [2:0] MA_CTI_O; 1.895 - reg [2:0] MB_CTI_O; 1.896 - wire MA_WE_O = 1'b0; 1.897 - wire MB_WE_O = 1'b1; 1.898 - reg [31:0] MA_ADR_O; 1.899 - reg [31:0] MB_ADR_O; 1.900 - reg [3:0] MA_SEL_O; 1.901 - reg [3:0] MB_SEL_O; 1.902 - wire MA_LOCK_O = 0; //reg_bt2 ? (status1 == ST_READ) && (!(MA_CTI_O == 3'h7)) : 1'b0; 1.903 - wire MB_LOCK_O = 0; //reg_bt2 ? (status2 == ST_WRITE) && (!(MB_CTI_O == 3'h7)) : 1'b0; 1.904 - 1.905 - wire reg_busy = reg_bt2 ? !(status1 == ST_IDLE) : !(status == ST_IDLE1); 1.906 - wire reg_interrupt; 1.907 - wire reg_status; 1.908 - 1.909 - wire reg_cntlg; 1.910 - reg start_flag; 1.911 - reg [5:0] burst_size; 1.912 - reg [5:0] burst_cnt; 1.913 - reg fifo_wr; 1.914 - reg fifo_rd; 1.915 - reg [31:0] fifo_din; 1.916 - wire [31:0] fifo_dout; 1.917 - wire fifo_empty; 1.918 - wire fifo_aempty; 1.919 - reg fifo_clear; 1.920 - reg [31:0] first_data; 1.921 - reg first_data_flag; 1.922 - wire [31:0] MB_DAT_O = first_data_flag ? first_data : fifo_dout; 1.923 - reg latch_start; 1.924 - 1.925 - reg reg_status1, reg_status2; 1.926 - reg reg_interrupt1, reg_interrupt2; 1.927 - reg end_of_transfer; 1.928 - reg burst_completed; 1.929 - reg donot_start_again; 1.930 - reg [5:0] burst_size2; 1.931 - reg [5:0] burst_cnt2; 1.932 - 1.933 - reg reg_cntlg_burst, reg_cntlg_normal; 1.934 - reg reg_status_normal, reg_interrupt_normal; 1.935 - reg direct_data; 1.936 - 1.937 + /*---------------------------------------------------------------------- 1.938 + Sequential Logic 1.939 + ----------------------------------------------------------------------*/ 1.940 always @(posedge CLK_I or posedge RST_I) 1.941 - if(RST_I) 1.942 - begin 1.943 - first_data <= #UDLY 'h0; 1.944 - first_data_flag <= #UDLY 1'b0; 1.945 - end 1.946 - else if((start_flag || direct_data) & !reg_bt2 & MA_ACK_I) 1.947 + if (RST_I) 1.948 begin 1.949 - first_data <= #UDLY MA_DAT_I; 1.950 - first_data_flag <= #UDLY 1'b1; 1.951 + rstate <= #UDLY RD_IDLE; 1.952 + wstate <= #UDLY WR_IDLE; 1.953 + xfer_length <= #UDLY 32'b0; 1.954 + rburst_count <= #UDLY 6'b0; 1.955 + wburst_count <= #UDLY 6'b0; 1.956 + retry_delay <= #UDLY 8'b0; 1.957 + reg_status <= #UDLY 1'b0; 1.958 + MA_CYC_O <= #UDLY 1'b0; 1.959 + MA_CYC_O_d <= #UDLY 1'b0; 1.960 + MA_STB_O <= #UDLY 1'b0; 1.961 + MA_CTI_O <= #UDLY 3'b0; 1.962 + MA_ADR_O <= #UDLY 'b0; 1.963 + MA_SEL_O <= #UDLY 'b0; 1.964 + MB_CYC_O <= #UDLY 1'b0; 1.965 + MB_CYC_O_d <= #UDLY 1'b0; 1.966 + MB_STB_O <= #UDLY 1'b0; 1.967 + MB_CTI_O <= #UDLY 3'b0; 1.968 + MB_ADR_O <= #UDLY 'b0; 1.969 + MB_SEL_O <= #UDLY 'b0; 1.970 + raddr_checkpoint <= #UDLY 32'b0; 1.971 + waddr_checkpoint <= #UDLY 32'b0; 1.972 + save_wburst_count <= #UDLY 6'b0; 1.973 end 1.974 - else if(first_data_flag & MB_ACK_I) 1.975 + else 1.976 begin 1.977 - first_data_flag <= #UDLY 1'b0; 1.978 + rstate <= #UDLY rstate_nxt; 1.979 + wstate <= #UDLY wstate_nxt; 1.980 + xfer_length <= #UDLY xfer_length_nxt; 1.981 + rburst_count <= #UDLY rburst_count_nxt; 1.982 + wburst_count <= #UDLY wburst_count_nxt; 1.983 + retry_delay <= #UDLY retry_delay_nxt; 1.984 + reg_status <= #UDLY reg_status_nxt; 1.985 + MA_CYC_O <= #UDLY MA_CYC_O_nxt; 1.986 + MA_CYC_O_d <= #UDLY MA_CYC_O; 1.987 + MA_STB_O <= #UDLY MA_STB_O_nxt; 1.988 + MA_CTI_O <= #UDLY MA_CTI_O_nxt; 1.989 + MA_ADR_O <= #UDLY MA_ADR_O_nxt; 1.990 + MA_SEL_O <= #UDLY MA_SEL_O_nxt; 1.991 + MB_CYC_O <= #UDLY MB_CYC_O_nxt; 1.992 + MB_CYC_O_d <= #UDLY MB_CYC_O; 1.993 + MB_STB_O <= #UDLY MB_STB_O_nxt; 1.994 + MB_CTI_O <= #UDLY MB_CTI_O_nxt; 1.995 + MB_ADR_O <= #UDLY MB_ADR_O_nxt; 1.996 + MB_SEL_O <= #UDLY MB_SEL_O_nxt; 1.997 + raddr_checkpoint <= #UDLY raddr_checkpoint_nxt; 1.998 + waddr_checkpoint <= #UDLY waddr_checkpoint_nxt; 1.999 + save_wburst_count <= #UDLY save_wburst_count_nxt; 1.1000 end 1.1001 1.1002 - assign reg_status = reg_bt2 ? (reg_status1 | reg_status2) : reg_status_normal; 1.1003 - assign reg_interrupt = reg_bt2 ? (reg_interrupt1 | reg_interrupt2) : reg_interrupt_normal; 1.1004 - assign reg_cntlg = reg_bt2 ? reg_cntlg_burst : reg_cntlg_normal; 1.1005 - 1.1006 - 1.1007 - //FSM 1.1008 - always @(posedge CLK_I or posedge RST_I) 1.1009 - if(RST_I) 1.1010 - begin 1.1011 - status1 <= #UDLY ST_IDLE; 1.1012 - var_length1 <= #UDLY 1'b0; 1.1013 - MA_ADR_O <= #UDLY 32'h0; 1.1014 - MA_SEL_O <= #UDLY 4'b1111; 1.1015 - MA_CYC_O <= #UDLY 1'b0; 1.1016 - MA_CTI_O <= #UDLY 3'h0; 1.1017 - MA_STB_O <= #UDLY 1'b0; 1.1018 - reg_status1 <= #UDLY 1'b0; 1.1019 - reg_interrupt1 <= #UDLY 1'b0; 1.1020 - start_flag <= #UDLY 1'b0; 1.1021 - burst_size <= #UDLY 5'h0; 1.1022 - burst_cnt <= #UDLY 5'h0; 1.1023 - fifo_clear <= #UDLY 1'b0; 1.1024 - latch_start <= #UDLY 1'b0; 1.1025 - fifo_wr <= #UDLY 1'b0; 1.1026 - 1.1027 - status2 <= #UDLY ST_WRITE_IDLE; 1.1028 - MB_ADR_O <= #UDLY 32'h0; 1.1029 - MB_SEL_O <= #UDLY 4'b1111; 1.1030 - MB_CYC_O <= #UDLY 1'b0; 1.1031 - MB_CTI_O <= #UDLY 3'h0; 1.1032 - MB_STB_O <= #UDLY 1'b0; 1.1033 - reg_status2 <= #UDLY 1'b0; 1.1034 - reg_interrupt2 <= #UDLY 1'b0; 1.1035 - reg_cntlg_burst <= #UDLY 1'b0; 1.1036 - burst_size2 <= #UDLY 5'h0; 1.1037 - burst_cnt2 <= #UDLY 5'h0; 1.1038 - fifo_rd <= #UDLY 1'b0; 1.1039 - end_of_transfer <= #UDLY 1'b0; 1.1040 - var_length2 <= #UDLY 1'b0; 1.1041 - burst_completed <= #UDLY 1'b0; 1.1042 - donot_start_again <= #UDLY 1'b0; 1.1043 - 1.1044 - status <= #UDLY ST_IDLE1; 1.1045 - var_length <= #UDLY 1'b0; 1.1046 - reg_status_normal <= #UDLY 1'b0; 1.1047 - reg_interrupt_normal <= #UDLY 1'b0; 1.1048 - reg_cntlg_normal <= #UDLY 1'b0; 1.1049 - direct_data <= #UDLY 1'b0; 1.1050 - end 1.1051 - else 1.1052 - begin 1.1053 - if (reg_bt2) begin 1.1054 - // Read Burst 1.1055 - if ((MB_RTY_I && (!(|data_length))) || (MB_ERR_I && (status2 == ST_WRITE))) 1.1056 - begin 1.1057 - status1 <= #UDLY ST_IDLE; 1.1058 - end 1.1059 - else 1.1060 - begin 1.1061 - case(status1) 1.1062 - ST_IDLE: 1.1063 - begin 1.1064 - if(fifo_wr) 1.1065 - fifo_wr <= #UDLY 1'b0; 1.1066 - if(MA_ACK_I) 1.1067 - begin 1.1068 - MA_CYC_O <= #UDLY 1'b0; 1.1069 - MA_STB_O <= #UDLY 1'b0; 1.1070 - MA_CTI_O <= #UDLY 3'h0; 1.1071 - end 1.1072 - if(reg_start | latch_start) 1.1073 - begin 1.1074 - if(fifo_empty) 1.1075 - begin 1.1076 - if(latch_start) 1.1077 - latch_start <= #UDLY 1'b0; 1.1078 - status1 <= #UDLY ST_READ; 1.1079 - MA_CYC_O <= #UDLY 1'b1; 1.1080 - MA_STB_O <= #UDLY 1'b1; 1.1081 - MA_ADR_O <= #UDLY reg_00_data; 1.1082 - case (reg_00_data[1:0]) 1.1083 - 2'b01: MA_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 1.1084 - 2'b10: MA_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 1.1085 - 2'b11: MA_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 1.1086 - default: 1.1087 - MA_SEL_O <= #UDLY M_SEL_O; 1.1088 - endcase 1.1089 - set_cti_a; 1.1090 - start_flag <= #UDLY 1'b1; 1.1091 - if(!(|data_length)) 1.1092 - var_length1 <= #UDLY 1'b1; 1.1093 - else 1.1094 - var_length1 <= #UDLY 1'b0; 1.1095 - burst_size <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.1096 - burst_cnt <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.1097 - end 1.1098 - else 1.1099 - status1 <= #UDLY ST_RDFIFO; 1.1100 - end 1.1101 - else 1.1102 - status1 <= #UDLY ST_IDLE; 1.1103 - reg_interrupt1 <= #UDLY 1'b0; 1.1104 - end 1.1105 - 1.1106 - ST_WAIT_WRITE_FINISH: 1.1107 - begin 1.1108 - fifo_wr <= #UDLY 1'b0; 1.1109 - if (status2 == ST_WRITE) 1.1110 - start_flag <= #UDLY 1'b0; 1.1111 - if(end_of_transfer) 1.1112 - begin 1.1113 - if(!reg_s_con) 1.1114 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.1115 - if (incr_unit == 3'b001) 1.1116 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.1117 - else 1.1118 - if (incr_unit == 3'b010) 1.1119 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.1120 - 1.1121 - status1 <= #UDLY ST_RDADDR; 1.1122 - burst_cnt <= #UDLY burst_size; 1.1123 - end 1.1124 - else 1.1125 - begin 1.1126 - if(burst_completed) 1.1127 - status1 <= #UDLY ST_IDLE; 1.1128 - end 1.1129 - end 1.1130 - 1.1131 - ST_RDFIFO: 1.1132 - begin 1.1133 - if(fifo_empty) 1.1134 - begin 1.1135 - status1 <= #UDLY ST_IDLE; 1.1136 - fifo_clear <= #UDLY 1'b0; 1.1137 - latch_start <= #UDLY 1'b1; 1.1138 - end 1.1139 - else 1.1140 - fifo_clear <= #UDLY !fifo_clear; 1.1141 - end 1.1142 - 1.1143 - ST_RDADDR: 1.1144 - begin 1.1145 - MA_CYC_O <= #UDLY 1'b1; 1.1146 - MA_STB_O <= #UDLY 1'b1; 1.1147 - set_cti_a; 1.1148 - status1 <= #UDLY ST_READ; 1.1149 - end 1.1150 - 1.1151 - ST_READ: 1.1152 - begin 1.1153 - write_fifo; 1.1154 - if(MA_ACK_I) 1.1155 - begin 1.1156 - if(start_flag) 1.1157 - begin 1.1158 - if(burst_cnt == 0) 1.1159 - begin 1.1160 - MA_CYC_O <= #UDLY 1'b0; 1.1161 - MA_STB_O <= #UDLY 1'b0; 1.1162 - MA_CTI_O <= #UDLY 3'h0; 1.1163 - status1 <= #UDLY ST_WAIT_WRITE_FINISH; 1.1164 - end 1.1165 - else 1.1166 - begin 1.1167 - if(burst_cnt == 1) 1.1168 - MA_CTI_O <= #UDLY 3'h7; 1.1169 - burst_cnt <= #UDLY burst_cnt - 1; 1.1170 - if(!reg_s_con) 1.1171 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.1172 - if (incr_unit == 3'b001) 1.1173 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.1174 - else 1.1175 - if (incr_unit == 3'b010) 1.1176 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.1177 - end 1.1178 - end 1.1179 - else 1.1180 - begin 1.1181 - if(burst_cnt == 0) 1.1182 - begin 1.1183 - MA_CYC_O <= #UDLY 1'b0; 1.1184 - MA_STB_O <= #UDLY 1'b0; 1.1185 - MA_CTI_O <= #UDLY 3'h0; 1.1186 - status1 <= #UDLY ST_WAIT_WRITE_FINISH; 1.1187 - end 1.1188 - else 1.1189 - begin 1.1190 - if(burst_cnt == 1) 1.1191 - MA_CTI_O <= #UDLY 3'h7; 1.1192 - if(!reg_s_con) 1.1193 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.1194 - if (incr_unit == 3'b001) 1.1195 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.1196 - else 1.1197 - if (incr_unit == 3'b010) 1.1198 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.1199 - burst_cnt <= #UDLY burst_cnt - 1; 1.1200 - end 1.1201 - end 1.1202 - end 1.1203 - else if(MA_RTY_I) 1.1204 - begin 1.1205 - if(var_length1) 1.1206 - begin 1.1207 - MA_CYC_O <= #UDLY 1'b0; 1.1208 - MA_STB_O <= #UDLY 1'b0; 1.1209 - MA_CTI_O <= #UDLY 3'h0; 1.1210 - status1 <= #UDLY ST_IDLE; 1.1211 - reg_status1 <= #UDLY 1'b0; 1.1212 - reg_interrupt1 <= #UDLY 1'b1; 1.1213 - start_flag <= #UDLY 1'b0; 1.1214 - end 1.1215 - end 1.1216 - else if(MA_ERR_I) 1.1217 - begin 1.1218 - MA_CYC_O <= #UDLY 1'b0; 1.1219 - MA_STB_O <= #UDLY 1'b0; 1.1220 - MA_CTI_O <= #UDLY 3'h0; 1.1221 - status1 <= #UDLY ST_IDLE; 1.1222 - reg_status1 <= #UDLY 1'b1; 1.1223 - reg_interrupt1 <= #UDLY 1'b1; 1.1224 - start_flag <= #UDLY 1'b0; 1.1225 - end 1.1226 - end 1.1227 - 1.1228 - default: 1.1229 - begin 1.1230 - status1 <= #UDLY ST_IDLE; 1.1231 - var_length1 <= #UDLY 1'b0; 1.1232 - MA_ADR_O <= #UDLY 32'h0; 1.1233 - MA_SEL_O <= #UDLY 4'b1111; 1.1234 - MA_CYC_O <= #UDLY 1'b0; 1.1235 - MA_CTI_O <= #UDLY 3'h0; 1.1236 - MA_STB_O <= #UDLY 1'b0; 1.1237 - reg_status1 <= #UDLY 1'b0; 1.1238 - reg_interrupt1 <= #UDLY 1'b0; 1.1239 - start_flag <= #UDLY 1'b0; 1.1240 - burst_size <= #UDLY 5'h0; 1.1241 - burst_cnt <= #UDLY 5'h0; 1.1242 - fifo_clear <= #UDLY 1'b0; 1.1243 - latch_start <= #UDLY 1'b0; 1.1244 - fifo_wr <= #UDLY 1'b0; 1.1245 - end 1.1246 - endcase 1.1247 - end 1.1248 - // Write Burst 1.1249 - if ((MA_RTY_I && (!(|data_length))) || (MA_ERR_I && (status1 == ST_READ))) 1.1250 - begin 1.1251 - status2 <= #UDLY ST_WRITE_IDLE; 1.1252 - donot_start_again <= #UDLY 1'b1; 1.1253 - end 1.1254 - else 1.1255 - begin 1.1256 - case(status2) 1.1257 - ST_WRITE_IDLE: 1.1258 - begin 1.1259 - if(reg_start) 1.1260 - begin 1.1261 - MB_ADR_O <= #UDLY reg_04_data; 1.1262 - case (reg_04_data[1:0]) 1.1263 - 2'b01: MB_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 1.1264 - 2'b10: MB_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 1.1265 - 2'b11: MB_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 1.1266 - default: 1.1267 - MB_SEL_O <= #UDLY M_SEL_O; 1.1268 - endcase 1.1269 - if(!(|data_length)) 1.1270 - var_length2 <= #UDLY 1'b1; 1.1271 - else 1.1272 - var_length2 <= #UDLY 1'b0; 1.1273 - burst_size2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.1274 - burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.1275 - if(!fifo_empty) 1.1276 - status2 <= #UDLY ST_FIFO_EMPTY; 1.1277 - else 1.1278 - donot_start_again <= #UDLY 1'b0; 1.1279 - end 1.1280 - if(fifo_empty) 1.1281 - begin 1.1282 - if(MB_ACK_I) 1.1283 - begin 1.1284 - MB_CYC_O <= #UDLY 1'b0; 1.1285 - MB_STB_O <= #UDLY 1'b0; 1.1286 - MB_CTI_O <= #UDLY 3'h0; 1.1287 - fifo_rd <= #UDLY 1'b0; 1.1288 - end 1.1289 - burst_cnt2 <= #UDLY 5'h0; 1.1290 - end 1.1291 - else 1.1292 - begin 1.1293 - if(donot_start_again) 1.1294 - begin 1.1295 - if(MB_ACK_I) 1.1296 - begin 1.1297 - if(!reg_d_con) 1.1298 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.1299 - if (incr_unit == 3'b001) 1.1300 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.1301 - else 1.1302 - if (incr_unit == 3'b010) 1.1303 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.1304 - end 1.1305 - end 1.1306 - end 1.1307 - 1.1308 - if(!fifo_empty && !donot_start_again) 1.1309 - begin 1.1310 - if(start_flag) 1.1311 - begin 1.1312 - set_cti_b; 1.1313 - status2 <= #UDLY ST_WRITE_WAIT; 1.1314 - read_fifo; 1.1315 - burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.1316 - end 1.1317 - else 1.1318 - begin 1.1319 - if(!reg_d_con) 1.1320 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.1321 - if (incr_unit == 3'b001) 1.1322 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.1323 - else 1.1324 - if (incr_unit == 3'b010) 1.1325 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.1326 - status2 <= #UDLY ST_WRADDR; 1.1327 - read_fifo; 1.1328 - burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.1329 - end 1.1330 - end 1.1331 - end_of_transfer <= #UDLY 1'b0; 1.1332 - burst_completed <= #UDLY 1'b0; 1.1333 - reg_interrupt2 <= #UDLY 1'b0; 1.1334 - end 1.1335 - 1.1336 - ST_FIFO_EMPTY: 1.1337 - begin 1.1338 - if(fifo_empty) 1.1339 - begin 1.1340 - status2 <= #UDLY ST_WRITE_IDLE; 1.1341 - donot_start_again <= #UDLY 1'b0; 1.1342 - end 1.1343 - end 1.1344 - 1.1345 - ST_WRADDR: 1.1346 - begin 1.1347 - burst_cnt2 <= #UDLY burst_size2; 1.1348 - MB_CYC_O <= #UDLY 1'b1; 1.1349 - MB_STB_O <= #UDLY 1'b1; 1.1350 - 1.1351 - if (fifo_aempty && (burst_size2 > 5'h2)) 1.1352 - begin 1.1353 - MB_CTI_O <= #UDLY 3'b000; 1.1354 - status2 <= #UDLY ST_FIFO_AEMPTY; 1.1355 - fifo_rd <= #UDLY 1'b0; 1.1356 - end 1.1357 - else 1.1358 - begin 1.1359 - set_cti_b; 1.1360 - status2 <= #UDLY ST_WRITE; 1.1361 - end 1.1362 - end 1.1363 - 1.1364 - ST_WRITE_WAIT: 1.1365 - begin 1.1366 - MB_CYC_O <= #UDLY 1'b1; 1.1367 - MB_STB_O <= #UDLY 1'b1; 1.1368 - 1.1369 - if (fifo_aempty && (burst_size2 > 5'h2)) 1.1370 - begin 1.1371 - MB_CTI_O <= #UDLY 3'b000; 1.1372 - status2 <= #UDLY ST_FIFO_AEMPTY; 1.1373 - fifo_rd <= #UDLY 1'b0; 1.1374 - end 1.1375 - else 1.1376 - begin 1.1377 - set_cti_b; 1.1378 - status2 <= #UDLY ST_WRITE; 1.1379 - end 1.1380 - end 1.1381 - 1.1382 - ST_FIFO_AEMPTY: 1.1383 - begin 1.1384 - if (MB_ACK_I) 1.1385 - begin 1.1386 - MB_CYC_O <= #UDLY 1'b0; 1.1387 - MB_STB_O <= #UDLY 1'b0; 1.1388 - 1.1389 - burst_cnt2 <= #UDLY burst_cnt2 - 1; 1.1390 - 1.1391 - if (!reg_d_con) 1.1392 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.1393 - 1.1394 - if (incr_unit == 3'b001) 1.1395 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.1396 - else 1.1397 - if (incr_unit == 3'b010) 1.1398 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.1399 - end 1.1400 - 1.1401 - if (!MB_CYC_O && !fifo_aempty) 1.1402 - begin 1.1403 - status2 <= #UDLY ST_FIFO_RESUME; 1.1404 - read_fifo; 1.1405 - end 1.1406 - end 1.1407 - 1.1408 - ST_FIFO_RESUME: 1.1409 - begin 1.1410 - MB_CYC_O <= #UDLY 1'b1; 1.1411 - MB_STB_O <= #UDLY 1'b1; 1.1412 - 1.1413 - if (fifo_aempty && (burst_cnt2 > 5'h2)) 1.1414 - begin 1.1415 - MB_CTI_O <= #UDLY 3'b000; 1.1416 - status2 <= #UDLY ST_FIFO_AEMPTY; 1.1417 - fifo_rd <= #UDLY 1'b0; 1.1418 - end 1.1419 - else 1.1420 - begin 1.1421 - set_cti_b; 1.1422 - status2 <= #UDLY ST_WRITE; 1.1423 - end 1.1424 - end 1.1425 - 1.1426 - ST_WRITE: 1.1427 - begin 1.1428 - if (MB_ACK_I) 1.1429 - begin 1.1430 - if(var_length2) 1.1431 - begin 1.1432 - if(burst_cnt2 == 0) 1.1433 - begin 1.1434 - MB_CYC_O <= #UDLY 1'b0; 1.1435 - MB_STB_O <= #UDLY 1'b0; 1.1436 - MB_CTI_O <= #UDLY 3'h0; 1.1437 - end_of_transfer <= #UDLY 1'b1; 1.1438 - status2 <= #UDLY ST_WRITE_IDLE; 1.1439 - fifo_rd <= #UDLY 1'b0; 1.1440 - burst_cnt2 <= #UDLY burst_size2; 1.1441 - end 1.1442 - else 1.1443 - begin 1.1444 - if(burst_cnt2 == 1) 1.1445 - MB_CTI_O <= #UDLY 3'h7; 1.1446 - else 1.1447 - set_cti_b; 1.1448 - if(!reg_d_con) 1.1449 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.1450 - if (incr_unit == 3'b001) 1.1451 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.1452 - else 1.1453 - if (incr_unit == 3'b010) 1.1454 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.1455 - read_fifo; 1.1456 - burst_cnt2 <= #UDLY burst_cnt2 - 1; 1.1457 - end 1.1458 - end 1.1459 - else 1.1460 - begin 1.1461 - if(burst_cnt2 == 0) 1.1462 - begin 1.1463 - MB_CYC_O <= #UDLY 1'b0; 1.1464 - MB_STB_O <= #UDLY 1'b0; 1.1465 - MB_CTI_O <= #UDLY 3'h0; 1.1466 - reg_cntlg_burst <= #UDLY 1'b1; 1.1467 - status2 <= #UDLY ST_CNTLNGTH; 1.1468 - fifo_rd <= #UDLY 1'b0; 1.1469 - burst_cnt2 <= #UDLY burst_size2; 1.1470 - end 1.1471 - else 1.1472 - begin 1.1473 - if ((fifo_aempty && (burst_cnt2 > 5'h2)) || (burst_cnt2 == 5'h1)) 1.1474 - MB_CTI_O <= #UDLY 3'h7; 1.1475 - else 1.1476 - set_cti_b; 1.1477 - 1.1478 - burst_cnt2 <= #UDLY burst_cnt2 - 1; 1.1479 - 1.1480 - if(!reg_d_con) 1.1481 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.1482 - 1.1483 - if (incr_unit == 3'b001) 1.1484 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.1485 - else 1.1486 - if (incr_unit == 3'b010) 1.1487 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.1488 - 1.1489 - if (fifo_aempty && (burst_cnt2 > 5'h2)) 1.1490 - begin 1.1491 - status2 <= #UDLY ST_FIFO_AEMPTY; 1.1492 - fifo_rd <= 1'b0; 1.1493 - end 1.1494 - else 1.1495 - read_fifo; 1.1496 - end 1.1497 - end 1.1498 - end 1.1499 - 1.1500 - else if(MB_RTY_I) 1.1501 - begin 1.1502 - if(var_length2) 1.1503 - begin 1.1504 - MB_CYC_O <= #UDLY 1'b0; 1.1505 - MB_STB_O <= #UDLY 1'b0; 1.1506 - MB_CTI_O <= #UDLY 3'h0; 1.1507 - status2 <= #UDLY ST_WRITE_IDLE; 1.1508 - reg_status2 <= #UDLY 1'b0; 1.1509 - reg_interrupt2 <= #UDLY 1'b1; 1.1510 - var_length2 <= #UDLY 1'b0; 1.1511 - donot_start_again <= #UDLY 1'b1; 1.1512 - fifo_rd <= #UDLY 1'b0; 1.1513 - end 1.1514 - end // if (MB_RTY_I) 1.1515 - 1.1516 - else if(MB_ERR_I) 1.1517 - begin 1.1518 - MB_CYC_O <= #UDLY 1'b0; 1.1519 - MB_STB_O <= #UDLY 1'b0; 1.1520 - MB_CTI_O <= #UDLY 3'h0; 1.1521 - status2 <= #UDLY ST_WRITE_IDLE; 1.1522 - reg_status2 <= #UDLY 1'b1; 1.1523 - reg_interrupt2 <= #UDLY 1'b1; 1.1524 - donot_start_again <= #UDLY 1'b1; 1.1525 - fifo_rd <= #UDLY 1'b0; 1.1526 - end // if (MB_ERR_I) 1.1527 - 1.1528 - end 1.1529 - 1.1530 - ST_CNTLNGTH: 1.1531 - begin 1.1532 - reg_cntlg_burst <= #UDLY 1'b0; 1.1533 - status2 <= #UDLY ST_JUSTICE; 1.1534 - end 1.1535 - 1.1536 - ST_JUSTICE: 1.1537 - begin 1.1538 - if(!(|data_length)) 1.1539 - begin 1.1540 - status2 <= #UDLY ST_WRITE_IDLE; 1.1541 - reg_status2 <= #UDLY 1'b0; 1.1542 - reg_interrupt2 <= #UDLY 1'b1; 1.1543 - burst_completed <= #UDLY 1'b1; 1.1544 - end 1.1545 - else 1.1546 - begin 1.1547 - end_of_transfer <= #UDLY 1'b1; 1.1548 - status2 <= ST_WRITE_IDLE; 1.1549 - end 1.1550 - end 1.1551 - 1.1552 - default: 1.1553 - begin 1.1554 - status2 <= #UDLY ST_WRITE_IDLE; 1.1555 - MB_ADR_O <= #UDLY 32'h0; 1.1556 - MB_SEL_O <= #UDLY 4'b1111; 1.1557 - MB_CYC_O <= #UDLY 1'b0; 1.1558 - MB_CTI_O <= #UDLY 3'h0; 1.1559 - MB_STB_O <= #UDLY 1'b0; 1.1560 - reg_status2 <= #UDLY 1'b0; 1.1561 - reg_interrupt2 <= #UDLY 1'b0; 1.1562 - reg_cntlg_burst <= #UDLY 1'b0; 1.1563 - burst_size2 <= #UDLY 5'h0; 1.1564 - burst_cnt2 <= #UDLY 5'h0; 1.1565 - fifo_rd <= #UDLY 1'b0; 1.1566 - end_of_transfer <= #UDLY 1'b0; 1.1567 - var_length2 <= #UDLY 1'b0; 1.1568 - burst_completed <= #UDLY 1'b0; 1.1569 - donot_start_again <= #UDLY 1'b0; 1.1570 - end 1.1571 - endcase 1.1572 - end 1.1573 - end 1.1574 - else begin 1.1575 - // Read/Write Normal 1.1576 - case(status) 1.1577 - 1.1578 - ST_IDLE1: 1.1579 - begin 1.1580 - if(reg_start | latch_start) 1.1581 - begin 1.1582 - if(fifo_empty) 1.1583 - begin 1.1584 - if(latch_start) 1.1585 - latch_start <= #UDLY 1'b0; 1.1586 - status <= #UDLY ST_READ1; 1.1587 - MA_CYC_O <= #UDLY 1'b1; 1.1588 - MA_STB_O <= #UDLY 1'b1; 1.1589 - MA_ADR_O <= #UDLY reg_00_data; 1.1590 - case (reg_00_data[1:0]) 1.1591 - 2'b01: MA_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 1.1592 - 2'b10: MA_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 1.1593 - 2'b11: MA_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 1.1594 - default: 1.1595 - MA_SEL_O <= #UDLY M_SEL_O; 1.1596 - endcase 1.1597 - MB_ADR_O <= #UDLY reg_04_data; 1.1598 - case (reg_04_data[1:0]) 1.1599 - 2'b01: MB_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 1.1600 - 2'b10: MB_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 1.1601 - 2'b11: MB_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 1.1602 - default: 1.1603 - MB_SEL_O <= #UDLY M_SEL_O; 1.1604 - endcase 1.1605 - set_cti_a; 1.1606 - start_flag <= #UDLY 1'b1; 1.1607 - if(!(|data_length)) 1.1608 - var_length <= #UDLY 1'b1; 1.1609 - else 1.1610 - var_length <= #UDLY 1'b0; 1.1611 - burst_size <= #UDLY 5'h0; 1.1612 - burst_cnt <= #UDLY 5'h0; 1.1613 - end 1.1614 - else 1.1615 - begin 1.1616 - status <= #UDLY ST_RDFIFO1; 1.1617 - end 1.1618 - end 1.1619 - else 1.1620 - begin 1.1621 - status <= #UDLY ST_IDLE1; 1.1622 - end 1.1623 - reg_interrupt_normal <= #UDLY 1'b0; 1.1624 - end 1.1625 - ST_RDFIFO1: 1.1626 - begin 1.1627 - if(fifo_empty) 1.1628 - begin 1.1629 - status <= #UDLY ST_IDLE1; 1.1630 - fifo_clear <= #UDLY 1'b0; 1.1631 - latch_start <= #UDLY 1'b1; 1.1632 - end 1.1633 - else 1.1634 - fifo_clear <= #UDLY !fifo_clear; 1.1635 - end 1.1636 - 1.1637 - ST_RDADDR1: 1.1638 - begin 1.1639 - MA_CYC_O <= #UDLY 1'b1; 1.1640 - MA_STB_O <= #UDLY 1'b1; 1.1641 - set_cti_a; 1.1642 - status <= #UDLY ST_READ1; 1.1643 - direct_data <= #UDLY 1'b1; 1.1644 - end 1.1645 - 1.1646 - ST_READ1: 1.1647 - begin 1.1648 - if(!start_flag) 1.1649 - write_fifo; 1.1650 - if(MA_ACK_I) 1.1651 - begin 1.1652 - if(start_flag) 1.1653 - begin 1.1654 - MA_CYC_O <= #UDLY 1'b0; 1.1655 - MA_STB_O <= #UDLY 1'b0; 1.1656 - MA_CTI_O <= #UDLY 3'h0; 1.1657 - MB_CYC_O <= #UDLY 1'b1; 1.1658 - MB_STB_O <= #UDLY 1'b1; 1.1659 - set_cti_b; 1.1660 - status <= #UDLY ST_WRITE1; 1.1661 - start_flag <= #UDLY 1'b0; 1.1662 - burst_cnt <= #UDLY burst_size; 1.1663 - end 1.1664 - else 1.1665 - begin 1.1666 - MA_CYC_O <= #UDLY 1'b0; 1.1667 - MA_STB_O <= #UDLY 1'b0; 1.1668 - MA_CTI_O <= #UDLY 3'h0; 1.1669 - if(!reg_d_con) 1.1670 - begin 1.1671 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.1672 - if (incr_unit == 3'b001) 1.1673 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.1674 - else 1.1675 - if (incr_unit == 3'b010) 1.1676 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.1677 - end 1.1678 - status <= #UDLY ST_WRADDR1; 1.1679 - burst_cnt <= #UDLY burst_size; 1.1680 - end 1.1681 - end 1.1682 - else if(MA_RTY_I) 1.1683 - begin 1.1684 - if(var_length) 1.1685 - begin 1.1686 - MA_CYC_O <= #UDLY 1'b0; 1.1687 - MA_STB_O <= #UDLY 1'b0; 1.1688 - MA_CTI_O <= #UDLY 3'h0; 1.1689 - status <= #UDLY ST_IDLE1; 1.1690 - reg_status_normal <= #UDLY 1'b0; 1.1691 - reg_interrupt_normal <= #UDLY 1'b1; 1.1692 - end 1.1693 - end 1.1694 - else if(MA_ERR_I) 1.1695 - begin 1.1696 - MA_CYC_O <= #UDLY 1'b0; 1.1697 - MA_STB_O <= #UDLY 1'b0; 1.1698 - MA_CTI_O <= #UDLY 3'h0; 1.1699 - status <= #UDLY ST_IDLE1; 1.1700 - reg_status_normal <= #UDLY 1'b1; 1.1701 - reg_interrupt_normal <= #UDLY 1'b1; 1.1702 - end 1.1703 - end 1.1704 - 1.1705 - ST_WRADDR1: 1.1706 - begin 1.1707 - fifo_wr <= #UDLY 1'b0; 1.1708 - MB_CYC_O <= #UDLY 1'b1; 1.1709 - MB_STB_O <= #UDLY 1'b1; 1.1710 - burst_cnt <= #UDLY burst_size; 1.1711 - set_cti_b; 1.1712 - status <= #UDLY ST_WRITE1; 1.1713 - read_fifo; 1.1714 - end 1.1715 - 1.1716 - ST_WRITE1: 1.1717 - begin 1.1718 - if(fifo_wr) 1.1719 - fifo_wr <= #UDLY 1'b0; 1.1720 - if(MB_ACK_I) 1.1721 - begin 1.1722 - direct_data <= #UDLY 1'b0; 1.1723 - if(var_length) 1.1724 - begin 1.1725 - MB_CYC_O <= #UDLY 1'b0; 1.1726 - MB_STB_O <= #UDLY 1'b0; 1.1727 - MB_CTI_O <= #UDLY 3'h0; 1.1728 - if(!reg_s_con) 1.1729 - begin 1.1730 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.1731 - if (incr_unit == 3'b001) 1.1732 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.1733 - else 1.1734 - if (incr_unit == 3'b010) 1.1735 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.1736 - end 1.1737 - status <= #UDLY ST_RDADDR1; 1.1738 - fifo_rd <= #UDLY 1'b0; 1.1739 - burst_cnt <= #UDLY burst_size; 1.1740 - end 1.1741 - else 1.1742 - begin 1.1743 - MB_CYC_O <= #UDLY 1'b0; 1.1744 - MB_STB_O <= #UDLY 1'b0; 1.1745 - MB_CTI_O <= #UDLY 3'h0; 1.1746 - reg_cntlg_normal <= #UDLY 1'b1; 1.1747 - status <= #UDLY ST_CNTLNGTH1; 1.1748 - fifo_rd <= #UDLY 1'b0; 1.1749 - burst_cnt <= #UDLY burst_size; 1.1750 - end 1.1751 - end 1.1752 - else if(MB_RTY_I) 1.1753 - begin 1.1754 - if(var_length) 1.1755 - begin 1.1756 - MB_CYC_O <= #UDLY 1'b0; 1.1757 - MB_STB_O <= #UDLY 1'b0; 1.1758 - MB_CTI_O <= #UDLY 3'h0; 1.1759 - status <= #UDLY ST_IDLE1; 1.1760 - reg_status_normal <= #UDLY 1'b0; 1.1761 - reg_interrupt_normal <= #UDLY 1'b1; 1.1762 - var_length <= #UDLY 1'b0; 1.1763 - fifo_rd <= #UDLY 1'b0; 1.1764 - end 1.1765 - end 1.1766 - else if(MB_ERR_I) 1.1767 - begin 1.1768 - MB_CYC_O <= #UDLY 1'b0; 1.1769 - MB_STB_O <= #UDLY 1'b0; 1.1770 - MB_CTI_O <= #UDLY 3'h0; 1.1771 - status <= #UDLY ST_IDLE1; 1.1772 - reg_status_normal <= #UDLY 1'b1; 1.1773 - reg_interrupt_normal <= #UDLY 1'b1; 1.1774 - fifo_rd <= #UDLY 1'b0; 1.1775 - end 1.1776 - end 1.1777 - 1.1778 - ST_CNTLNGTH1: 1.1779 - begin 1.1780 - reg_cntlg_normal <= #UDLY 1'b0; 1.1781 - status <= #UDLY ST_JUSTICE1; 1.1782 - end 1.1783 - 1.1784 - ST_JUSTICE1: 1.1785 - begin 1.1786 - if(!(|data_length)) 1.1787 - begin 1.1788 - status <= #UDLY ST_IDLE1; 1.1789 - reg_status_normal <= #UDLY 1'b0; 1.1790 - reg_interrupt_normal <= #UDLY 1'b1; 1.1791 - end 1.1792 - else 1.1793 - begin 1.1794 - if(!reg_s_con) 1.1795 - begin 1.1796 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.1797 - if (incr_unit == 3'b001) 1.1798 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.1799 - else 1.1800 - if (incr_unit == 3'b010) 1.1801 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.1802 - end 1.1803 - status <= #UDLY ST_RDADDR1; 1.1804 - end 1.1805 - end 1.1806 - 1.1807 - default: 1.1808 - begin 1.1809 - status <= #UDLY ST_IDLE1; 1.1810 - var_length <= #UDLY 1'b0; 1.1811 - MA_CYC_O <= #UDLY 1'b0; 1.1812 - MA_CTI_O <= #UDLY 3'h0; 1.1813 - MB_CYC_O <= #UDLY 1'b0; 1.1814 - MB_CTI_O <= #UDLY 3'h0; 1.1815 - MA_STB_O <= #UDLY 1'b0; 1.1816 - MB_STB_O <= #UDLY 1'b0; 1.1817 - reg_status_normal <= #UDLY 1'b0; 1.1818 - reg_interrupt_normal <= #UDLY 1'b0; 1.1819 - reg_cntlg_normal <= #UDLY 1'b0; 1.1820 - burst_size <= #UDLY 3'h0; 1.1821 - burst_cnt <= #UDLY 3'h0; 1.1822 - fifo_wr <= #UDLY 1'b0; 1.1823 - fifo_rd <= #UDLY 1'b0; 1.1824 - fifo_clear <= #UDLY 1'b0; 1.1825 - latch_start <= #UDLY 1'b0; 1.1826 - direct_data <= #UDLY 1'b0; 1.1827 - end 1.1828 - endcase 1.1829 - end 1.1830 - end 1.1831 - 1.1832 - //Task for generating write enable to the FIFO 1.1833 - task write_fifo; 1.1834 - begin 1.1835 - if(MA_ACK_I) 1.1836 - begin 1.1837 - fifo_wr <= #UDLY 1'b1; 1.1838 - fifo_din <= #UDLY MA_DAT_I; 1.1839 - end 1.1840 - else 1.1841 - begin 1.1842 - fifo_wr <= #UDLY 1'b0; 1.1843 - end 1.1844 - end 1.1845 - endtask 1.1846 - 1.1847 - //Task for generating read enable signal to the FIFO 1.1848 - task read_fifo; 1.1849 - begin 1.1850 - fifo_rd <= #UDLY 1'b1; 1.1851 - end 1.1852 - endtask 1.1853 - 1.1854 - //Task for setting wishbone CTI signal for read 1.1855 - //master port depending upon whether request is for burst 1.1856 - //transfer or classic cycle. 1.1857 - task set_cti_a; 1.1858 - begin 1.1859 - if(reg_bt2) 1.1860 - begin 1.1861 - if(reg_s_con) 1.1862 - MA_CTI_O <= #UDLY 3'b001; 1.1863 - else 1.1864 - MA_CTI_O <= #UDLY 3'b010; 1.1865 - end 1.1866 - else 1.1867 - MA_CTI_O <= #UDLY 3'b000; 1.1868 - end 1.1869 - endtask 1.1870 - 1.1871 - //Task for setting wishbone CTI signal for write 1.1872 - //master port depending upon whether request is for burst 1.1873 - //transfer or classic cycle. 1.1874 - task set_cti_b; 1.1875 - begin 1.1876 - if(reg_bt2) begin 1.1877 - if(reg_d_con) 1.1878 - MB_CTI_O <= #UDLY 3'b001; 1.1879 - else 1.1880 - MB_CTI_O <= #UDLY 3'b010; 1.1881 - end else 1.1882 - MB_CTI_O <= #UDLY 3'b000; 1.1883 - end 1.1884 - endtask 1.1885 - 1.1886 - //RdEn 1.1887 - reg fifo_rd_dly; 1.1888 - always @(posedge CLK_I or posedge RST_I) 1.1889 - if(RST_I) 1.1890 - fifo_rd_dly <= #UDLY 1'b0; 1.1891 - else 1.1892 - fifo_rd_dly <= #UDLY fifo_rd; 1.1893 - 1.1894 - wire RdEn = fifo_rd & (!fifo_rd_dly | (reg_bt2 ? (burst_cnt2[5:0] != 5'b00000) : (burst_cnt[5:0] != 5'b00000)) & MB_ACK_I) | fifo_clear; 1.1895 - 1.1896 + /*---------------------------------------------------------------------- 1.1897 + FIFO Logic 1.1898 + ----------------------------------------------------------------------*/ 1.1899 + reg fifo_rd_en, fifo_wr_en; 1.1900 + always @(/*AUTOSENSE*/MA_ACK_I or MA_DAT_I or MB_ACK_I 1.1901 + or fifo_aempty or fifo_empty or rstate or wburst_count 1.1902 + or wstate) 1.1903 + begin 1.1904 + if (((wstate == WR_SINGLEA) && (fifo_empty == 1'b0)) 1.1905 + || ((wstate == WR_FIFO_CHECK) 1.1906 + && (((fifo_empty == 1'b0) && (wburst_count == 6'h0)) 1.1907 + || ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1)))) 1.1908 + || ((wstate == WR_BURST) 1.1909 + && (/*(MB_CYC_O_d == 1'b0) 1.1910 + ||*/ (MB_ACK_I && (wburst_count >= 6'h1)))) 1.1911 + || ((wstate == WR_ERROR) && (fifo_empty == 1'b0)) 1.1912 + || ((wstate == WR_RETRY) && (fifo_empty == 1'b0))) 1.1913 + fifo_rd_en = 1'b1; 1.1914 + else 1.1915 + fifo_rd_en = 1'b0; 1.1916 + 1.1917 + if (MA_ACK_I 1.1918 + && ((rstate == RD_SINGLEA) || (rstate == RD_BURST))) 1.1919 + fifo_wr_en = 1'b1; 1.1920 + else 1.1921 + fifo_wr_en = 1'b0; 1.1922 + 1.1923 + fifo_din = MA_DAT_I; 1.1924 + end 1.1925 + 1.1926 generate 1.1927 if (lat_family == "SC" || lat_family == "SCM") begin 1.1928 + 1.1929 + pmi_fifo_dc 1.1930 + #(.pmi_data_width_w(MA_WB_DAT_WIDTH), 1.1931 + .pmi_data_width_r(MA_WB_DAT_WIDTH), 1.1932 + .pmi_data_depth_w(64), 1.1933 + .pmi_data_depth_r(64), 1.1934 + .pmi_full_flag(64), 1.1935 + .pmi_empty_flag(0), 1.1936 + .pmi_almost_full_flag(60), 1.1937 + .pmi_almost_empty_flag(4), 1.1938 + .pmi_regmode("noreg"), 1.1939 + .pmi_family(`LATTICE_FAMILY), 1.1940 + .module_type("pmi_fifo_dc"), 1.1941 + .pmi_implementation(FIFO_IMPLEMENTATION)) 1.1942 + dma_fifo_dc 1.1943 + ( 1.1944 + .Data(fifo_din), 1.1945 + .WrClock (CLK_I), 1.1946 + .RdClock (CLK_I), 1.1947 + .WrEn (fifo_wr_en), 1.1948 + .RdEn (fifo_rd_en), 1.1949 + .Reset (RST_I), 1.1950 + .RPReset (RST_I), 1.1951 + .Q (fifo_dout), 1.1952 + .Empty (fifo_empty), 1.1953 + .Full (), 1.1954 + .AlmostEmpty(), 1.1955 + .AlmostFull ()); 1.1956 + 1.1957 + end else if (lat_family == "MachXO2") begin 1.1958 + 1.1959 + pmi_fifo_dc 1.1960 + #(.pmi_data_width_w (MA_WB_DAT_WIDTH), 1.1961 + .pmi_data_width_r (MA_WB_DAT_WIDTH), 1.1962 + .pmi_data_depth_w (64), 1.1963 + .pmi_data_depth_r (64), 1.1964 + .pmi_full_flag (64), 1.1965 + .pmi_empty_flag (0), 1.1966 + .pmi_almost_full_flag (60), 1.1967 + .pmi_almost_empty_flag (1), 1.1968 + .pmi_regmode ("noreg"), 1.1969 + .pmi_family ("XO2"), 1.1970 + .module_type ("pmi_fifo_dc"), 1.1971 + .pmi_implementation (FIFO_IMPLEMENTATION)) 1.1972 + dma_fifo 1.1973 + (.Data (fifo_din), 1.1974 + .WrClock (CLK_I), 1.1975 + .RdClock (CLK_I), 1.1976 + .WrEn (fifo_wr_en), 1.1977 + .RdEn (fifo_rd_en), 1.1978 + .Reset (RST_I), 1.1979 + .RPReset (RST_I), 1.1980 + .Q (fifo_dout), 1.1981 + .Empty (fifo_empty), 1.1982 + .Full (), 1.1983 + .AlmostEmpty(fifo_aempty), 1.1984 + .AlmostFull ()); 1.1985 1.1986 - pmi_fifo_dc #(.pmi_data_width_w(32), 1.1987 - .pmi_data_width_r(32), 1.1988 - .pmi_data_depth_w(32), 1.1989 - .pmi_data_depth_r(32), 1.1990 - .pmi_full_flag(32), 1.1991 - .pmi_empty_flag(0), 1.1992 - .pmi_almost_full_flag(28), 1.1993 - .pmi_almost_empty_flag(4), 1.1994 - .pmi_regmode("noreg"), 1.1995 - .pmi_family(`LATTICE_FAMILY), 1.1996 - .module_type("pmi_fifo_dc"), 1.1997 - .pmi_implementation(FIFO_IMPLEMENTATION)) 1.1998 - dma_fifo_dc ( 1.1999 - .Data(fifo_din), 1.2000 - .WrClock(CLK_I), 1.2001 - .RdClock(CLK_I), 1.2002 - .WrEn (fifo_wr), 1.2003 - .RdEn (RdEn), 1.2004 - .Reset (RST_I), 1.2005 - .RPReset(RST_I), 1.2006 - .Q (fifo_dout), 1.2007 - .Empty (fifo_empty), 1.2008 - .Full (), 1.2009 - .AlmostEmpty (), 1.2010 - .AlmostFull ()); 1.2011 - 1.2012 - 1.2013 - 1.2014 end else begin 1.2015 - pmi_fifo #(.pmi_data_width(32), 1.2016 - .pmi_data_depth(32), 1.2017 - .pmi_full_flag(32), 1.2018 - .pmi_empty_flag(0), 1.2019 - .pmi_almost_full_flag(28), 1.2020 - .pmi_almost_empty_flag(1), 1.2021 - .pmi_regmode("noreg"), 1.2022 - .pmi_family(`LATTICE_FAMILY), 1.2023 - .module_type("pmi_fifo"), 1.2024 - .pmi_implementation(FIFO_IMPLEMENTATION)) 1.2025 - dma_fifo (.Data (fifo_din), 1.2026 - .Clock (CLK_I), 1.2027 - .WrEn (fifo_wr), 1.2028 - .RdEn (RdEn), 1.2029 - .Reset (RST_I), 1.2030 - .Q (fifo_dout), 1.2031 - .Empty (fifo_empty), 1.2032 - .Full (), 1.2033 - .AlmostEmpty (fifo_aempty), 1.2034 - .AlmostFull ()); 1.2035 - end 1.2036 + 1.2037 + pmi_fifo 1.2038 + #(.pmi_data_width(MA_WB_DAT_WIDTH), 1.2039 + .pmi_data_depth(64), 1.2040 + .pmi_full_flag(64), 1.2041 + .pmi_empty_flag(0), 1.2042 + .pmi_almost_full_flag(60), 1.2043 + .pmi_almost_empty_flag(1), 1.2044 + .pmi_regmode("noreg"), 1.2045 + .pmi_family(`LATTICE_FAMILY), 1.2046 + .module_type("pmi_fifo"), 1.2047 + .pmi_implementation(FIFO_IMPLEMENTATION)) 1.2048 + dma_fifo 1.2049 + (.Data (fifo_din), 1.2050 + .Clock (CLK_I), 1.2051 + .WrEn (fifo_wr_en), 1.2052 + .RdEn (fifo_rd_en), 1.2053 + .Reset (RST_I), 1.2054 + .Q (fifo_dout), 1.2055 + .Empty (fifo_empty), 1.2056 + .Full (), 1.2057 + .AlmostEmpty(fifo_aempty), 1.2058 + .AlmostFull ()); 1.2059 + 1.2060 + end 1.2061 + 1.2062 endgenerate 1.2063 1.2064 -endmodule // MASTER_CTRL 1.2065 +endmodule 1.2066 1.2067 -`endif // MASTER_CTRL_FILE 1.2068 +`endif // `ifndef MASTER_CTRL_FILE