1.1 diff -r 11aef665a5d8 -r 522426d22baa rtl/verilog/master_ctrl.v 1.2 --- a/rtl/verilog/master_ctrl.v Fri Aug 13 10:43:05 2010 +0100 1.3 +++ b/rtl/verilog/master_ctrl.v Sat Aug 06 01:48:48 2011 +0100 1.4 @@ -1,1188 +1,902 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 +// ================================================================== 1.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.16 +// ------------------------------------------------------------------ 1.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.18 +// ALL RIGHTS RESERVED 1.19 +// ------------------------------------------------------------------ 1.20 +// 1.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.22 +// 1.23 +// Permission: 1.24 +// 1.25 +// Lattice Semiconductor grants permission to use this code 1.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.27 +// Open Source License Agreement. 1.28 +// 1.29 +// Disclaimer: 1.30 // 1.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.34 -// U.S.A email: techsupport@latticesemi.com 1.35 -// =============================================================================/ 1.36 +// Lattice Semiconductor provides no warranty regarding the use or 1.37 +// functionality of this code. It is the user's responsibility to 1.38 +// verify the user’s design for consistency and functionality through 1.39 +// the use of formal verification methods. 1.40 +// 1.41 +// -------------------------------------------------------------------- 1.42 +// 1.43 +// Lattice Semiconductor Corporation 1.44 +// 5555 NE Moore Court 1.45 +// Hillsboro, OR 97214 1.46 +// U.S.A 1.47 +// 1.48 +// TEL: 1-800-Lattice (USA and Canada) 1.49 +// 503-286-8001 (other locations) 1.50 +// 1.51 +// web: http://www.latticesemi.com/ 1.52 +// email: techsupport@latticesemi.com 1.53 +// 1.54 +// -------------------------------------------------------------------- 1.55 // FILE DETAILS 1.56 // Project : LM32 DMA Component 1.57 -// File : master_ctrl.v 1.58 -// Title : DMA Master controller 1.59 +// File : wb_dma_ctrl.v 1.60 +// Title : DMA controller top file 1.61 // Dependencies : None 1.62 -// 1.63 -// Version 3.1 1.64 -// 1. Make DMA Engine compliant to Rule 3.100 of Wishbone Spec which defines 1.65 -// alignement of bytes in sub-word transfers. 1.66 -// 2. Removed glitch that did not pause the burst write when the read burst 1.67 -// was paused by the "read slave". 1.68 -// 1.69 -// Version 7.0SP2, 3.0 1.70 -// 1. Read and Write channel of DMA controller are working in parallel, 1.71 -// due to that now as soon as FIFO is not empty write channel of the DMA 1.72 -// controller start writing data to the slave. 1.73 -// 2. Burst Size supported by DMA controller is increased to support bigger 1.74 -// burst (from current value of 4 and 8 to 16 and 32). Now 4 different type 1.75 -// of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 1.76 -// For this Burst Size field of the control register is increased to 2 bits. 1.77 -// 3. Glitch is removed on the S_ACK_O signal. 1.78 -// 1.79 -// Version 7.0 1.80 -// 1. Initial Release 1.81 -// 1.82 +// : 1.83 +// Version : 7.0 1.84 +// : Initial Release 1.85 +// : 1.86 +// Version : 7.0SP2, 3.0 1.87 +// : 1. Read and Write channel of DMA controller are working in 1.88 +// : parallel, due to that now as soon as FIFO is not empty 1.89 +// : write channel of the DMA controller start writing data 1.90 +// : to the slave. 1.91 +// : 2. Burst Size supported by DMA controller is increased to 1.92 +// : support bigger burst (from current value of 4 and 8 to 1.93 +// : 16 and 32). Now 4 different type of burst sizes are 1.94 +// : supported by the DMA controller 4, 8, 16 and 32. For 1.95 +// : this Burst Size field of the control register is 1.96 +// : increased to 2 bits. 1.97 +// : 3. Glitch is removed on the S_ACK_O signal. 1.98 +// : 1.99 +// Version : 3.1 1.100 +// : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec 1.101 +// : which defines alignement of bytes in sub-word transfers. 1.102 +// : 1.103 +// Version : 3.2 1.104 +// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and 1.105 +// : Read/Write Ports can be independently configured. 1.106 +// : 2. Support for "retry" on receipt of a WISHBONE RTY. This 1.107 +// : retry results in the current burst or classic cycle 1.108 +// : being issued again after a retry timeout. 1.109 +// : 3. Support for "error" on receipt of a WISHBONE ERR. This 1.110 +// : results in the current dma transfer being terminated 1.111 +// : and the error is updated within the STATUS CSR. 1.112 +// : 4. Support for burst size of 64. 1.113 +// : 1.114 +// Version : 3.3 1.115 +// : Support for MachXO2 added. The MachXO2 only has a FIFO 1.116 +// : with separate read/write clocks. 1.117 // ============================================================================= 1.118 1.119 `ifndef MASTER_CTRL_FILE 1.120 `define MASTER_CTRL_FILE 1.121 `include "system_conf.v" 1.122 module MASTER_CTRL 1.123 - #(parameter LENGTH_WIDTH = 16, 1.124 + #(parameter MA_WB_DAT_WIDTH = 32, 1.125 + parameter MA_WB_ADR_WIDTH = 32, 1.126 + parameter MB_WB_DAT_WIDTH = 32, 1.127 + parameter MB_WB_ADR_WIDTH = 32, 1.128 + parameter S_WB_DAT_WIDTH = 32, 1.129 parameter FIFO_IMPLEMENTATION = "EBR") 1.130 - ( 1.131 - //master read port 1.132 - MA_ADR_O, 1.133 - MA_SEL_O, 1.134 - MA_WE_O, 1.135 - MA_STB_O, 1.136 - MA_CYC_O, 1.137 - MA_CTI_O, 1.138 - MA_LOCK_O, 1.139 - MA_DAT_I, //32bits 1.140 - MA_ACK_I, 1.141 - MA_ERR_I, 1.142 - MA_RTY_I, 1.143 - //master write port 1.144 - MB_ADR_O, 1.145 - MB_SEL_O, 1.146 - MB_DAT_O, //32bits 1.147 - MB_WE_O, 1.148 - MB_STB_O, 1.149 - MB_CYC_O, 1.150 - MB_CTI_O, 1.151 - MB_LOCK_O, 1.152 - MB_ACK_I, 1.153 - MB_ERR_I, 1.154 - MB_RTY_I, 1.155 - //register interface 1.156 - M_SEL_O, 1.157 - reg_start, 1.158 - reg_status, 1.159 - reg_interrupt, 1.160 - reg_busy, 1.161 - data_length, 1.162 - reg_cntlg, 1.163 - reg_bt2,reg_bt1,reg_bt0, 1.164 - incr_unit, 1.165 - reg_s_con, 1.166 - reg_d_con, 1.167 - reg_00_data, 1.168 - reg_04_data, 1.169 - //system clock and reset 1.170 - CLK_I, 1.171 - RST_I 1.172 - ); 1.173 - //master read port 1.174 - output [31:0] MA_ADR_O; 1.175 - output [3:0] MA_SEL_O; 1.176 - output MA_WE_O; 1.177 - output MA_STB_O; 1.178 - output MA_CYC_O; 1.179 - output [2:0] MA_CTI_O; 1.180 - output MA_LOCK_O; 1.181 - input [31:0] MA_DAT_I; //32bits 1.182 - input MA_ACK_I; 1.183 - input MA_ERR_I; 1.184 - input MA_RTY_I; 1.185 - //master write port 1.186 - output [31:0] MB_ADR_O; 1.187 - output [3:0] MB_SEL_O; 1.188 - output [31:0] MB_DAT_O; //32bits 1.189 - output MB_WE_O; 1.190 - output MB_STB_O; 1.191 - output MB_CYC_O; 1.192 - output [2:0] MB_CTI_O; 1.193 - output MB_LOCK_O; 1.194 - input MB_ACK_I; 1.195 - input MB_ERR_I; 1.196 - input MB_RTY_I; 1.197 - 1.198 - //register interface 1.199 - input [3:0] M_SEL_O; 1.200 - input reg_start; 1.201 - output reg_status; 1.202 - output reg_interrupt; 1.203 - output reg_busy; 1.204 - input [LENGTH_WIDTH-1:0] data_length; 1.205 - output reg_cntlg; 1.206 - input reg_bt2,reg_bt1,reg_bt0; 1.207 - input [2:0] incr_unit; 1.208 - input reg_s_con; 1.209 - input reg_d_con; 1.210 - input [31:0] reg_00_data; 1.211 - input [31:0] reg_04_data; 1.212 - //system clock and reset 1.213 - input CLK_I; 1.214 - input RST_I; 1.215 + ( 1.216 + // System clock and reset 1.217 + input CLK_I, 1.218 + input RST_I, 1.219 + // Master read port 1.220 + output reg [MA_WB_ADR_WIDTH-1:0] MA_ADR_O, 1.221 + output reg [MA_WB_DAT_WIDTH/8-1:0] MA_SEL_O, 1.222 + output reg [MA_WB_DAT_WIDTH-1:0] MA_DAT_O, 1.223 + output reg MA_WE_O, 1.224 + output reg MA_STB_O, 1.225 + output reg MA_CYC_O, 1.226 + output reg [2:0] MA_CTI_O, 1.227 + output reg MA_LOCK_O, 1.228 + input [MA_WB_DAT_WIDTH-1:0] MA_DAT_I, 1.229 + input MA_ACK_I, 1.230 + input MA_ERR_I, 1.231 + input MA_RTY_I, 1.232 + // Master write port 1.233 + output reg [MB_WB_ADR_WIDTH-1:0] MB_ADR_O, 1.234 + output reg [MB_WB_DAT_WIDTH/8-1:0] MB_SEL_O, 1.235 + output reg [MB_WB_DAT_WIDTH-1:0] MB_DAT_O, 1.236 + output reg MB_WE_O, 1.237 + output reg MB_STB_O, 1.238 + output reg MB_CYC_O, 1.239 + output reg [2:0] MB_CTI_O, 1.240 + output reg MB_LOCK_O, 1.241 + input MB_ACK_I, 1.242 + input MB_ERR_I, 1.243 + input MB_RTY_I, 1.244 + // Register interface 1.245 + input reg_start, 1.246 + output reg reg_busy, 1.247 + output reg reg_status, 1.248 + output reg reg_interrupt, 1.249 + input reg_bt3, reg_bt2, reg_bt1, reg_bt0, 1.250 + input reg_s_con, reg_d_con, 1.251 + input reg_incw, reg_inchw, 1.252 + input [7:0] reg_rdelay, 1.253 + input [31:0] reg_00_data, 1.254 + input [31:0] reg_04_data, 1.255 + input [31:0] reg_08_data 1.256 + ); 1.257 + 1.258 + parameter lat_family = `LATTICE_FAMILY; 1.259 + parameter UDLY = 1; 1.260 + 1.261 + wire [MB_WB_DAT_WIDTH-1:0] fifo_dout; 1.262 + wire fifo_empty, fifo_aempty; 1.263 + reg [MA_WB_DAT_WIDTH-1:0] fifo_din; 1.264 + 1.265 + reg [31:0] xfer_length, xfer_length_nxt; 1.266 + reg [5:0] rburst_count, rburst_count_nxt; 1.267 + reg [5:0] wburst_count, wburst_count_nxt; 1.268 + reg [5:0] save_wburst_count, save_wburst_count_nxt; 1.269 + reg [31:0] raddr_checkpoint, raddr_checkpoint_nxt, waddr_checkpoint, waddr_checkpoint_nxt; 1.270 + reg [7:0] retry_delay, retry_delay_nxt; 1.271 + reg MA_CYC_O_nxt, MA_STB_O_nxt, MA_CYC_O_d; 1.272 + reg [2:0] MA_CTI_O_nxt; 1.273 + reg [MA_WB_ADR_WIDTH-1:0] MA_ADR_O_nxt; 1.274 + reg [MA_WB_DAT_WIDTH/8-1:0] MA_SEL_O_nxt; 1.275 + reg MB_CYC_O_nxt, MB_STB_O_nxt, MB_CYC_O_d; 1.276 + reg [2:0] MB_CTI_O_nxt; 1.277 + reg [MB_WB_ADR_WIDTH-1:0] MB_ADR_O_nxt; 1.278 + reg [MB_WB_DAT_WIDTH/8-1:0] MB_SEL_O_nxt; 1.279 + reg reg_status_nxt; 1.280 + reg burst_start, xfer_done; 1.281 + wire [2:0] iCount; 1.282 + wire [5:0] bCount; 1.283 + wire [8:0] biCount; 1.284 + 1.285 + /*---------------------------------------------------------------------- 1.286 + 1.287 + READ State Machine 1.288 + 1.289 + ----------------------------------------------------------------------*/ 1.290 + reg [2:0] rstate, rstate_nxt; 1.291 + parameter RD_IDLE = 3'b000; 1.292 + parameter RD_SINGLEA = 3'b001; 1.293 + parameter RD_SINGLEB = 3'b010; 1.294 + parameter RD_SINGLE_RETRY = 3'b011; 1.295 + parameter RD_BURST = 3'b100; 1.296 + 1.297 + always @(/*AUTOSENSE*/MA_ACK_I or MA_ERR_I or MA_RTY_I or MB_ERR_I 1.298 + or MB_RTY_I or burst_start or rburst_count or reg_bt3 1.299 + or reg_start or retry_delay or rstate or xfer_done) 1.300 + casez (rstate) 1.301 + RD_IDLE: 1.302 + if (reg_start && (reg_bt3 == 1'b0)) 1.303 + rstate_nxt = RD_SINGLEA; 1.304 + else if (burst_start && reg_bt3) 1.305 + rstate_nxt = RD_BURST; 1.306 + else 1.307 + rstate_nxt = rstate; 1.308 + 1.309 + RD_SINGLEA: 1.310 + if (MA_ACK_I) 1.311 + rstate_nxt = RD_SINGLEB; 1.312 + else if (MA_ERR_I) 1.313 + rstate_nxt = RD_IDLE; 1.314 + else if (MA_RTY_I) 1.315 + rstate_nxt = RD_SINGLE_RETRY; 1.316 + else 1.317 + rstate_nxt = rstate; 1.318 + 1.319 + RD_SINGLEB: 1.320 + if (burst_start) 1.321 + rstate_nxt = RD_SINGLEA; 1.322 + else if (MB_ERR_I || xfer_done) 1.323 + rstate_nxt = RD_IDLE; 1.324 + else if (MB_RTY_I) 1.325 + rstate_nxt = RD_SINGLE_RETRY; 1.326 + else 1.327 + rstate_nxt = rstate; 1.328 + 1.329 + RD_BURST: 1.330 + if (MB_ERR_I || MB_RTY_I || MA_ERR_I || MB_RTY_I || (MA_ACK_I && (rburst_count == 0))) 1.331 + rstate_nxt = RD_IDLE; 1.332 + else 1.333 + rstate_nxt = rstate; 1.334 + 1.335 + RD_SINGLE_RETRY: 1.336 + if (retry_delay == 8'h0) 1.337 + rstate_nxt = RD_SINGLEA; 1.338 + else 1.339 + rstate_nxt = rstate; 1.340 + 1.341 + default: 1.342 + rstate_nxt = RD_IDLE; 1.343 + endcase 1.344 + 1.345 + /*---------------------------------------------------------------------- 1.346 + 1.347 + WRITE State Machine 1.348 + 1.349 + ----------------------------------------------------------------------*/ 1.350 + reg [3:0] wstate, wstate_nxt; 1.351 + parameter WR_IDLE = 4'b0000; 1.352 + parameter WR_SINGLEA = 4'b0001; 1.353 + parameter WR_SINGLEB = 4'b0010; 1.354 + parameter WR_FIFO_CHECK = 4'b0011; 1.355 + parameter WR_SHORT = 4'b0100; 1.356 + parameter WR_BURST = 4'b0101; 1.357 + parameter WR_SBURST = 4'b0110; 1.358 + parameter WR_SETUPA = 4'b0111; 1.359 + parameter WR_SETUPB = 4'b1000; 1.360 + parameter WR_ERROR = 4'b1001; 1.361 + parameter WR_RETRY = 4'b1010; 1.362 + 1.363 + always @(/*AUTOSENSE*/MA_ERR_I or MA_RTY_I or MB_ACK_I or MB_ERR_I 1.364 + or MB_RTY_I or fifo_aempty or fifo_empty or iCount 1.365 + or reg_bt3 or reg_start or retry_delay or wburst_count 1.366 + or wstate or xfer_length) 1.367 + casez (wstate) 1.368 + WR_IDLE: 1.369 + if (reg_start) 1.370 + wstate_nxt = reg_bt3 ? WR_SETUPA : WR_SINGLEA; 1.371 + else 1.372 + wstate_nxt = wstate; 1.373 + 1.374 + WR_SINGLEA: 1.375 + if (MA_ERR_I) 1.376 + wstate_nxt = WR_IDLE; 1.377 + else if (fifo_empty == 1'b0) 1.378 + wstate_nxt = WR_SINGLEB; 1.379 + else 1.380 + wstate_nxt = wstate; 1.381 + 1.382 + WR_SINGLEB: 1.383 + if (MB_ACK_I) 1.384 + wstate_nxt = (xfer_length == iCount) ? WR_IDLE : WR_SINGLEA; 1.385 + else if (MB_ERR_I) 1.386 + wstate_nxt = WR_IDLE; 1.387 + else if (MB_RTY_I) 1.388 + wstate_nxt = WR_SINGLEA; 1.389 + else 1.390 + wstate_nxt = wstate; 1.391 + 1.392 + WR_FIFO_CHECK: 1.393 + if (MA_ERR_I) 1.394 + wstate_nxt = WR_ERROR; 1.395 + else if (MA_RTY_I) 1.396 + wstate_nxt = WR_RETRY; 1.397 + else 1.398 + if ((fifo_empty == 1'b0) && (wburst_count == 6'h0)) 1.399 + wstate_nxt = WR_SHORT; 1.400 + else if ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1)) 1.401 + wstate_nxt = WR_BURST; 1.402 + else 1.403 + wstate_nxt = wstate; 1.404 + 1.405 + WR_SHORT: 1.406 + if (MA_ERR_I) 1.407 + wstate_nxt = WR_ERROR; 1.408 + else if (MA_RTY_I) 1.409 + wstate_nxt = WR_RETRY; 1.410 + else 1.411 + if (MB_ACK_I) 1.412 + wstate_nxt = WR_FIFO_CHECK; 1.413 + else if (MB_ERR_I) 1.414 + wstate_nxt = WR_ERROR; 1.415 + else if (MB_RTY_I) 1.416 + wstate_nxt = WR_RETRY; 1.417 + else 1.418 + wstate_nxt = wstate; 1.419 + 1.420 + WR_BURST: 1.421 + if (MA_ERR_I) 1.422 + wstate_nxt = WR_ERROR; 1.423 + else if (MA_RTY_I) 1.424 + wstate_nxt = WR_RETRY; 1.425 + else 1.426 + if (MB_ACK_I) 1.427 + if (fifo_aempty && (wburst_count >= 6'h2)) 1.428 + wstate_nxt = WR_SBURST; 1.429 + else if (wburst_count == 6'h0) 1.430 + wstate_nxt = WR_SETUPA; 1.431 + else 1.432 + wstate_nxt = wstate; 1.433 + else if (MB_ERR_I) 1.434 + wstate_nxt = WR_ERROR; 1.435 + else if (MB_RTY_I) 1.436 + wstate_nxt = WR_RETRY; 1.437 + else 1.438 + wstate_nxt = wstate; 1.439 + 1.440 + WR_SBURST: 1.441 + if (MA_ERR_I) 1.442 + wstate_nxt = WR_ERROR; 1.443 + else if (MA_RTY_I) 1.444 + wstate_nxt = WR_RETRY; 1.445 + else 1.446 + if (MB_ACK_I) 1.447 + wstate_nxt = WR_FIFO_CHECK; 1.448 + else if (MB_RTY_I) 1.449 + wstate_nxt = WR_RETRY; 1.450 + else 1.451 + wstate_nxt = wstate; 1.452 + 1.453 + WR_SETUPA: 1.454 + wstate_nxt = WR_SETUPB; 1.455 + 1.456 + WR_SETUPB: 1.457 + wstate_nxt = (wburst_count == 6'h0) ? WR_IDLE : WR_FIFO_CHECK; 1.458 + 1.459 + WR_ERROR: 1.460 + wstate_nxt = fifo_empty ? WR_IDLE : wstate; 1.461 + 1.462 + WR_RETRY: 1.463 + if (fifo_empty && (retry_delay == 8'h0)) 1.464 + wstate_nxt = WR_FIFO_CHECK; 1.465 + else 1.466 + wstate_nxt = wstate; 1.467 + 1.468 + default: 1.469 + wstate_nxt = WR_IDLE; 1.470 + endcase 1.471 + 1.472 + /*---------------------------------------------------------------------- 1.473 + Status Signals 1.474 + ----------------------------------------------------------------------*/ 1.475 + always @(/*AUTOSENSE*/MA_ERR_I or MB_ERR_I or reg_status or wstate 1.476 + or wstate_nxt) 1.477 + begin 1.478 + // Raise and hold busy signal until current DMA transfer is complete 1.479 + reg_busy = (wstate_nxt != WR_IDLE); 1.480 + 1.481 + // Raise and hold error signal until a new DMA transfer is initiated. 1.482 + // Error signal is raised when the WISHBONE cycle results in _ERR_I 1.483 + if ((wstate == WR_IDLE) && (wstate_nxt != WR_IDLE)) 1.484 + reg_status_nxt = 1'b0; 1.485 + else if (MA_ERR_I || MB_ERR_I) 1.486 + reg_status_nxt = 1'b1; 1.487 + else 1.488 + reg_status_nxt = reg_status; 1.489 + 1.490 + // Raise interrupt on completion of DMA transfer 1.491 + reg_interrupt = (wstate != WR_IDLE) & (wstate_nxt == WR_IDLE); 1.492 + end 1.493 + 1.494 + /*---------------------------------------------------------------------- 1.495 + WISHBONE Read Port 1.496 + ----------------------------------------------------------------------*/ 1.497 + always @(/*AUTOSENSE*/MA_ACK_I or MA_ADR_O or MA_CTI_O or MA_CYC_O 1.498 + or MA_CYC_O_d or MA_ERR_I or MA_RTY_I or MA_STB_O 1.499 + or MB_ERR_I or MB_RTY_I or burst_start or iCount 1.500 + or raddr_checkpoint or rburst_count or reg_00_data 1.501 + or reg_bt3 or reg_s_con or reg_start or rstate 1.502 + or rstate_nxt) 1.503 + begin 1.504 + // MA_CYC_O and MA_STB_O 1.505 + 1.506 + // handle all conditions that cause MA_CYC_O to go 0 1.507 + if (((rstate == RD_SINGLEA) 1.508 + && (MA_ACK_I || MA_ERR_I || MA_RTY_I)) 1.509 + || ((rstate == RD_BURST) 1.510 + && (MB_ERR_I || MB_RTY_I || (MA_ACK_I && (rburst_count == 6'h0))))) 1.511 + begin 1.512 + MA_CYC_O_nxt = 1'b0; 1.513 + MA_STB_O_nxt = 1'b0; 1.514 + end 1.515 + // handle all conditions that cause MA_CYC_O to go 1 1.516 + else if (((rstate_nxt == RD_SINGLEA) 1.517 + && ((rstate == RD_IDLE) || (rstate == RD_SINGLEB) || (rstate == RD_SINGLE_RETRY))) 1.518 + || ((rstate == RD_BURST) && (MA_CYC_O_d == 1'b0))) 1.519 + begin 1.520 + MA_CYC_O_nxt = 1'b1; 1.521 + MA_STB_O_nxt = 1'b1; 1.522 + end 1.523 + // default: maintain state 1.524 + else 1.525 + begin 1.526 + MA_CYC_O_nxt = MA_CYC_O; 1.527 + MA_STB_O_nxt = MA_STB_O; 1.528 + end 1.529 + 1.530 + 1.531 + // MA_ADR_O 1.532 + 1.533 + // set up first address of the dma transfer 1.534 + if (reg_start) 1.535 + MA_ADR_O_nxt = reg_00_data; 1.536 + else if (reg_s_con == 1'b0) 1.537 + begin 1.538 + // roll back to first address in a burst transfer on a retry 1.539 + if (/*(rstate == RD_BURST) && */MB_RTY_I) 1.540 + MA_ADR_O_nxt = raddr_checkpoint; 1.541 + // increment for every regular transfer 1.542 + else if ((MB_RTY_I == 1'b0) 1.543 + && (((rstate == RD_SINGLEB) && burst_start) 1.544 + || ((rstate == RD_BURST) && MA_ACK_I))) 1.545 + MA_ADR_O_nxt = MA_ADR_O + iCount; 1.546 + else 1.547 + MA_ADR_O_nxt = MA_ADR_O; 1.548 + end 1.549 + else 1.550 + MA_ADR_O_nxt = MA_ADR_O; 1.551 + 1.552 + 1.553 + // MA_CTI_O 1.554 + 1.555 + if (reg_start || burst_start) 1.556 + MA_CTI_O_nxt = reg_bt3 ? (reg_s_con ? 3'b001 : 3'b010) : 3'b000; 1.557 + else if ((rstate == RD_BURST) && (rburst_count == 6'h1) && MA_ACK_I) 1.558 + MA_CTI_O_nxt = 3'b111; 1.559 + else 1.560 + MA_CTI_O_nxt = MA_CTI_O; 1.561 + 1.562 + 1.563 + // Other signals 1.564 + MA_WE_O = 1'b0; 1.565 + MA_DAT_O = 0; 1.566 + MA_LOCK_O = 1'b0; 1.567 + end 1.568 + 1.569 + generate 1.570 + if (MA_WB_DAT_WIDTH == 8) begin 1.571 + 1.572 + always @(*) 1.573 + MA_SEL_O_nxt = 1'b1; 1.574 + 1.575 + end 1.576 + else begin 1.577 + 1.578 + always @(/*AUTOSENSE*/MA_ADR_O_nxt or iCount) 1.579 + begin 1.580 + if (iCount == 1) 1.581 + casez (MA_ADR_O_nxt[1:0]) 1.582 + 2'b00: MA_SEL_O_nxt = 4'b1000; 1.583 + 2'b01: MA_SEL_O_nxt = 4'b0100; 1.584 + 2'b10: MA_SEL_O_nxt = 4'b0010; 1.585 + 2'b11: MA_SEL_O_nxt = 4'b0001; 1.586 + default: 1.587 + MA_SEL_O_nxt = 4'b1111; 1.588 + endcase 1.589 + else if (iCount == 2) 1.590 + MA_SEL_O_nxt = MA_ADR_O_nxt[1] ? 4'b0011 : 4'b1100; 1.591 + else 1.592 + MA_SEL_O_nxt = 4'b1111; 1.593 + end 1.594 + 1.595 + end 1.596 + endgenerate 1.597 + 1.598 + 1.599 + /*---------------------------------------------------------------------- 1.600 + WISHBONE Write Port 1.601 + ----------------------------------------------------------------------*/ 1.602 + always @(/*AUTOSENSE*/MA_ERR_I or MA_RTY_I or MB_ACK_I or MB_ADR_O 1.603 + or MB_CTI_O or MB_CYC_O or MB_ERR_I or MB_RTY_I 1.604 + or MB_STB_O or fifo_aempty or fifo_dout or fifo_empty 1.605 + or iCount or reg_04_data or reg_d_con or reg_s_con 1.606 + or reg_start or waddr_checkpoint or wburst_count or wstate 1.607 + or wstate_nxt) 1.608 + begin 1.609 + // MB_CYC_O and MB_STB_O 1.610 + 1.611 + // handle all conditions that cause MB_CYC_O to go 0 1.612 + if (((wstate == WR_SINGLEB) 1.613 + && (MB_ACK_I || MB_ERR_I || MB_RTY_I)) 1.614 + || ((MA_ERR_I || MA_RTY_I) 1.615 + && ((wstate == WR_SHORT) || (wstate == WR_FIFO_CHECK) || (wstate == WR_BURST) || (wstate == WR_SBURST))) 1.616 + || ((wstate == WR_BURST) 1.617 + && ((MB_ACK_I && (wburst_count == 6'h0)) || MB_ERR_I || MB_RTY_I)) 1.618 + || ((wstate == WR_SBURST) 1.619 + && (MB_ACK_I || MB_ERR_I || MB_RTY_I))) 1.620 + begin 1.621 + MB_CYC_O_nxt = 1'b0; 1.622 + MB_STB_O_nxt = 1'b0; 1.623 + end 1.624 + // handle all conditions that cause MB_CYC_O to go 1 1.625 + else if (((wstate == WR_SINGLEA) && (fifo_empty == 1'b0)) 1.626 + || ((wstate == WR_FIFO_CHECK) 1.627 + && (((fifo_empty == 1'b0) && (wburst_count == 6'h0)) 1.628 + || ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1))))) 1.629 + begin 1.630 + MB_CYC_O_nxt = 1'b1; 1.631 + MB_STB_O_nxt = 1'b1; 1.632 + end 1.633 + // default: maintain state 1.634 + else 1.635 + begin 1.636 + MB_CYC_O_nxt = MB_CYC_O; 1.637 + MB_STB_O_nxt = MB_STB_O; 1.638 + end 1.639 + 1.640 + 1.641 + // MB_ADR_O 1.642 + 1.643 + // set up first address of the dma transfer 1.644 + if (reg_start) 1.645 + MB_ADR_O_nxt = reg_04_data; 1.646 + else if (reg_d_con == 1'b0) 1.647 + begin 1.648 + // roll back to first address in a burst transfer on a retry 1.649 + if (wstate == WR_RETRY) 1.650 + MB_ADR_O_nxt = waddr_checkpoint; 1.651 + // increment for every regular transfer 1.652 + else if (((wstate == WR_SINGLEB) && MB_ACK_I) 1.653 + || (MB_ACK_I && (MA_RTY_I == 1'b0) && (MA_ERR_I == 1'b0) 1.654 + && ((wstate == WR_SHORT) || (wstate == WR_BURST) || (wstate == WR_SBURST)))) 1.655 + MB_ADR_O_nxt = MB_ADR_O + iCount; 1.656 + else 1.657 + MB_ADR_O_nxt = MB_ADR_O; 1.658 + end 1.659 + else 1.660 + MB_ADR_O_nxt = MB_ADR_O; 1.661 + 1.662 + 1.663 + // MB_CTI_O 1.664 + 1.665 + // set up classic wishbone cycle 1.666 + if ((wstate == WR_SINGLEA) 1.667 + || ((wstate == WR_FIFO_CHECK) && (wstate_nxt == WR_SHORT))) 1.668 + MB_CTI_O_nxt = 3'b000; 1.669 + // set up termination of a wishbone burst cycle 1.670 + else if ((wstate == WR_BURST) 1.671 + && ((MB_ACK_I && (wburst_count == 6'h1)) || (wstate_nxt == WR_SBURST))) 1.672 + MB_CTI_O_nxt = 3'b111; 1.673 + // set up wishbone burst (incrementing or constant address) 1.674 + else if (((wstate == WR_FIFO_CHECK) && (wstate_nxt == WR_BURST)) 1.675 + || ((wstate == WR_BURST) && MB_ACK_I)) 1.676 + MB_CTI_O_nxt = reg_s_con ? 3'b001 : 3'b010; 1.677 + // hold 1.678 + else 1.679 + MB_CTI_O_nxt = MB_CTI_O; 1.680 + 1.681 + // MB_DAT_O 1.682 + MB_DAT_O = fifo_dout; 1.683 + 1.684 + 1.685 + // Other signals 1.686 + MB_WE_O = 1'b1; 1.687 + MB_LOCK_O = 1'b0; 1.688 + end 1.689 + 1.690 + generate 1.691 + if (MB_WB_DAT_WIDTH == 8) begin 1.692 + 1.693 + always @(*) 1.694 + MB_SEL_O_nxt = 1'b1; 1.695 + 1.696 + end 1.697 + else begin 1.698 + 1.699 + always @(/*AUTOSENSE*/MB_ADR_O_nxt or iCount) 1.700 + begin 1.701 + if (iCount == 1) 1.702 + casez (MB_ADR_O_nxt[1:0]) 1.703 + 2'b00: MB_SEL_O_nxt = 4'b1000; 1.704 + 2'b01: MB_SEL_O_nxt = 4'b0100; 1.705 + 2'b10: MB_SEL_O_nxt = 4'b0010; 1.706 + 2'b11: MB_SEL_O_nxt = 4'b0001; 1.707 + default: 1.708 + MB_SEL_O_nxt = 4'b1111; 1.709 + endcase 1.710 + else if (iCount == 2) 1.711 + MB_SEL_O_nxt = MB_ADR_O_nxt[1] ? 4'b0011 : 4'b1100; 1.712 + else 1.713 + MB_SEL_O_nxt = 4'b1111; 1.714 + end 1.715 + 1.716 + end 1.717 + endgenerate 1.718 + 1.719 + /*---------------------------------------------------------------------- 1.720 + Logic to keep track of where we are in the transfer process 1.721 + ----------------------------------------------------------------------*/ 1.722 + // Increment Count 1.723 + generate 1.724 + if (S_WB_DAT_WIDTH == 8) begin 1.725 + assign iCount = 3'h1; 1.726 + end 1.727 + else begin 1.728 + assign iCount = reg_incw ? 3'h4 : (reg_inchw ? 3'h2 : 3'h1); 1.729 + end 1.730 + endgenerate 1.731 + 1.732 + // Burst Count 1.733 + assign bCount = (reg_bt3 1.734 + ? (reg_bt2 1.735 + ? 6'h3f 1.736 + : (reg_bt1 1.737 + ? (reg_bt0 ? 6'h1f : 6'h0f) 1.738 + : (reg_bt0 ? 6'h07 : 6'h03))) 1.739 + : 6'h01 1.740 + ); 1.741 + 1.742 + // Burst Increment Count 1.743 + assign biCount = (reg_bt3 1.744 + ? (reg_bt2 1.745 + ? iCount<<6 1.746 + : (reg_bt1 1.747 + ? (reg_bt0 ? iCount<<5 : iCount<<4) 1.748 + : (reg_bt0 ? iCount<<3 : iCount<<2) 1.749 + ) 1.750 + ) 1.751 + : iCount 1.752 + ); 1.753 + 1.754 + always @(/*AUTOSENSE*/MA_ACK_I or MB_ACK_I or bCount or biCount 1.755 + or fifo_empty or iCount or rburst_count or reg_08_data 1.756 + or reg_inchw or reg_incw or reg_start or rstate 1.757 + or save_wburst_count or wburst_count or wstate 1.758 + or xfer_length) 1.759 + begin 1.760 + // Transfer Length 1.761 + if (reg_start && (wstate == WR_IDLE)) 1.762 + xfer_length_nxt = reg_08_data; 1.763 + else if (MB_ACK_I && (wstate == WR_SINGLEB)) 1.764 + xfer_length_nxt = xfer_length - iCount; 1.765 + else if (wstate == WR_SETUPA) 1.766 + xfer_length_nxt = (xfer_length >= biCount) ? (xfer_length - biCount) : 0; 1.767 + else 1.768 + xfer_length_nxt = xfer_length; 1.769 + 1.770 + // Read-side Burst Count 1.771 + if (rstate == RD_IDLE) 1.772 + rburst_count_nxt = wburst_count; 1.773 + else if ((rstate == RD_BURST) && MA_ACK_I) 1.774 + rburst_count_nxt = rburst_count - 1'b1; 1.775 + else 1.776 + rburst_count_nxt = rburst_count; 1.777 + 1.778 + // Write-side Burst Count 1.779 + if (wstate == WR_SETUPA) 1.780 + wburst_count_nxt = ((xfer_length == 0) 1.781 + ? 0 1.782 + : ((xfer_length >= biCount) 1.783 + ? bCount 1.784 + : (xfer_length-1)>>(reg_incw ? 2 : (reg_inchw ? 1 : 0)))); 1.785 + else if ((wstate == WR_RETRY) && fifo_empty) 1.786 + wburst_count_nxt = save_wburst_count; 1.787 + else if (MB_ACK_I 1.788 + && ((wstate == WR_SHORT) || (wstate == WR_BURST) || (wstate == WR_SBURST))) 1.789 + wburst_count_nxt = wburst_count - 1'b1; 1.790 + else 1.791 + wburst_count_nxt = wburst_count; 1.792 + end 1.793 + 1.794 + /*---------------------------------------------------------------------- 1.795 + Logic to support a burst retry 1.796 + ----------------------------------------------------------------------*/ 1.797 + always @(/*AUTOSENSE*/MA_ADR_O or MB_ADR_O or raddr_checkpoint 1.798 + or reg_rdelay or retry_delay or rstate or rstate_nxt 1.799 + or save_wburst_count or waddr_checkpoint 1.800 + or wburst_count_nxt or wstate or wstate_nxt) 1.801 + begin 1.802 + // Write-side Saved Burst Count 1.803 + if (wstate == WR_SETUPA) 1.804 + save_wburst_count_nxt = wburst_count_nxt; 1.805 + else 1.806 + save_wburst_count_nxt = save_wburst_count; 1.807 + 1.808 + // Retry Delay 1.809 + if (((wstate != WR_RETRY) && (wstate_nxt == WR_RETRY)) 1.810 + || ((rstate == RD_SINGLEA) && (rstate_nxt == RD_SINGLE_RETRY))) 1.811 + retry_delay_nxt = reg_rdelay; 1.812 + else if ((wstate == WR_RETRY) || (rstate == RD_SINGLE_RETRY)) 1.813 + retry_delay_nxt = retry_delay - 1'b1; 1.814 + else 1.815 + retry_delay_nxt = retry_delay; 1.816 + 1.817 + // Read Address Checkpoint 1.818 + if ((rstate == RD_IDLE) && (rstate_nxt == RD_BURST)) 1.819 + raddr_checkpoint_nxt = MA_ADR_O; 1.820 + else 1.821 + raddr_checkpoint_nxt = raddr_checkpoint; 1.822 + 1.823 + // Write Address Checkpoint 1.824 + if (wstate == WR_SETUPA) 1.825 + waddr_checkpoint_nxt = MB_ADR_O; 1.826 + else 1.827 + waddr_checkpoint_nxt = waddr_checkpoint; 1.828 + end 1.829 + 1.830 + /*---------------------------------------------------------------------- 1.831 + Logic to indicate start/end of transfer and bursts 1.832 + ----------------------------------------------------------------------*/ 1.833 + always @(/*AUTOSENSE*/MA_ERR_I or MB_ACK_I or MB_ERR_I or iCount 1.834 + or retry_delay or wburst_count or wstate or xfer_length) 1.835 + begin 1.836 + if (((wstate == WR_SINGLEB) && (xfer_length > iCount) && MB_ACK_I) 1.837 + || ((wstate == WR_SETUPB) && (wburst_count > 0)) 1.838 + || ((wstate == WR_RETRY) && (retry_delay == 8'b0))) 1.839 + burst_start = 1'b1; 1.840 + else 1.841 + burst_start = 1'b0; 1.842 + 1.843 + if (MB_ERR_I 1.844 + || MA_ERR_I 1.845 + || ((wstate == WR_SINGLEB) && (xfer_length == iCount) && MB_ACK_I) 1.846 + || ((wstate == WR_SETUPB) && (wburst_count == 0))) 1.847 + xfer_done = 1'b1; 1.848 + else 1.849 + xfer_done = 1'b0; 1.850 + end 1.851 1.852 - parameter lat_family = `LATTICE_FAMILY; 1.853 - parameter UDLY = 1; 1.854 - //Read FSM States encoding 1.855 - parameter ST_IDLE = 3'b000; 1.856 - parameter ST_READ = 3'b001; 1.857 - parameter ST_RDADDR = 3'b010; 1.858 - parameter ST_RDFIFO = 3'b011; 1.859 - parameter ST_WAIT_WRITE_FINISH = 3'b100; 1.860 - 1.861 - //Write FSM States encoding 1.862 - parameter ST_WRITE_IDLE = 4'b0000; 1.863 - parameter ST_WRITE = 4'b0001; 1.864 - parameter ST_WRADDR = 4'b0010; 1.865 - parameter ST_CNTLNGTH = 4'b0011; 1.866 - parameter ST_JUSTICE = 4'b0100; 1.867 - parameter ST_FIFO_EMPTY = 4'b0101; 1.868 - parameter ST_WRITE_WAIT = 4'b0110; 1.869 - parameter ST_FIFO_AEMPTY = 4'b1010; 1.870 - parameter ST_FIFO_RESUME = 4'b1000; 1.871 - 1.872 - // FSM for normal data transfer 1.873 - parameter ST_IDLE1 = 3'b000; 1.874 - parameter ST_READ1 = 3'b001; 1.875 - parameter ST_WRITE1 = 3'b010; 1.876 - parameter ST_RDADDR1 = 3'b011; 1.877 - parameter ST_WRADDR1 = 3'b100; 1.878 - parameter ST_CNTLNGTH1 = 3'b101; 1.879 - parameter ST_JUSTICE1 = 3'b110; 1.880 - parameter ST_RDFIFO1 = 3'b111; 1.881 - reg [2:0] status; 1.882 - reg var_length; 1.883 - 1.884 - 1.885 - //fifo status 1.886 - 1.887 - reg [2:0] status1; 1.888 - reg [3:0] status2; 1.889 - reg var_length2; 1.890 - reg var_length1; 1.891 - reg MA_STB_O; 1.892 - reg MB_STB_O; 1.893 - reg MA_CYC_O; 1.894 - reg MB_CYC_O; 1.895 - reg [2:0] MA_CTI_O; 1.896 - reg [2:0] MB_CTI_O; 1.897 - wire MA_WE_O = 1'b0; 1.898 - wire MB_WE_O = 1'b1; 1.899 - reg [31:0] MA_ADR_O; 1.900 - reg [31:0] MB_ADR_O; 1.901 - reg [3:0] MA_SEL_O; 1.902 - reg [3:0] MB_SEL_O; 1.903 - wire MA_LOCK_O = 0; //reg_bt2 ? (status1 == ST_READ) && (!(MA_CTI_O == 3'h7)) : 1'b0; 1.904 - wire MB_LOCK_O = 0; //reg_bt2 ? (status2 == ST_WRITE) && (!(MB_CTI_O == 3'h7)) : 1'b0; 1.905 - 1.906 - wire reg_busy = reg_bt2 ? !(status1 == ST_IDLE) : !(status == ST_IDLE1); 1.907 - wire reg_interrupt; 1.908 - wire reg_status; 1.909 - 1.910 - wire reg_cntlg; 1.911 - reg start_flag; 1.912 - reg [5:0] burst_size; 1.913 - reg [5:0] burst_cnt; 1.914 - reg fifo_wr; 1.915 - reg fifo_rd; 1.916 - reg [31:0] fifo_din; 1.917 - wire [31:0] fifo_dout; 1.918 - wire fifo_empty; 1.919 - wire fifo_aempty; 1.920 - reg fifo_clear; 1.921 - reg [31:0] first_data; 1.922 - reg first_data_flag; 1.923 - wire [31:0] MB_DAT_O = first_data_flag ? first_data : fifo_dout; 1.924 - reg latch_start; 1.925 - 1.926 - reg reg_status1, reg_status2; 1.927 - reg reg_interrupt1, reg_interrupt2; 1.928 - reg end_of_transfer; 1.929 - reg burst_completed; 1.930 - reg donot_start_again; 1.931 - reg [5:0] burst_size2; 1.932 - reg [5:0] burst_cnt2; 1.933 - 1.934 - reg reg_cntlg_burst, reg_cntlg_normal; 1.935 - reg reg_status_normal, reg_interrupt_normal; 1.936 - reg direct_data; 1.937 - 1.938 + /*---------------------------------------------------------------------- 1.939 + Sequential Logic 1.940 + ----------------------------------------------------------------------*/ 1.941 always @(posedge CLK_I or posedge RST_I) 1.942 - if(RST_I) 1.943 - begin 1.944 - first_data <= #UDLY 'h0; 1.945 - first_data_flag <= #UDLY 1'b0; 1.946 - end 1.947 - else if((start_flag || direct_data) & !reg_bt2 & MA_ACK_I) 1.948 + if (RST_I) 1.949 begin 1.950 - first_data <= #UDLY MA_DAT_I; 1.951 - first_data_flag <= #UDLY 1'b1; 1.952 + rstate <= #UDLY RD_IDLE; 1.953 + wstate <= #UDLY WR_IDLE; 1.954 + xfer_length <= #UDLY 32'b0; 1.955 + rburst_count <= #UDLY 6'b0; 1.956 + wburst_count <= #UDLY 6'b0; 1.957 + retry_delay <= #UDLY 8'b0; 1.958 + reg_status <= #UDLY 1'b0; 1.959 + MA_CYC_O <= #UDLY 1'b0; 1.960 + MA_CYC_O_d <= #UDLY 1'b0; 1.961 + MA_STB_O <= #UDLY 1'b0; 1.962 + MA_CTI_O <= #UDLY 3'b0; 1.963 + MA_ADR_O <= #UDLY 'b0; 1.964 + MA_SEL_O <= #UDLY 'b0; 1.965 + MB_CYC_O <= #UDLY 1'b0; 1.966 + MB_CYC_O_d <= #UDLY 1'b0; 1.967 + MB_STB_O <= #UDLY 1'b0; 1.968 + MB_CTI_O <= #UDLY 3'b0; 1.969 + MB_ADR_O <= #UDLY 'b0; 1.970 + MB_SEL_O <= #UDLY 'b0; 1.971 + raddr_checkpoint <= #UDLY 32'b0; 1.972 + waddr_checkpoint <= #UDLY 32'b0; 1.973 + save_wburst_count <= #UDLY 6'b0; 1.974 end 1.975 - else if(first_data_flag & MB_ACK_I) 1.976 + else 1.977 begin 1.978 - first_data_flag <= #UDLY 1'b0; 1.979 + rstate <= #UDLY rstate_nxt; 1.980 + wstate <= #UDLY wstate_nxt; 1.981 + xfer_length <= #UDLY xfer_length_nxt; 1.982 + rburst_count <= #UDLY rburst_count_nxt; 1.983 + wburst_count <= #UDLY wburst_count_nxt; 1.984 + retry_delay <= #UDLY retry_delay_nxt; 1.985 + reg_status <= #UDLY reg_status_nxt; 1.986 + MA_CYC_O <= #UDLY MA_CYC_O_nxt; 1.987 + MA_CYC_O_d <= #UDLY MA_CYC_O; 1.988 + MA_STB_O <= #UDLY MA_STB_O_nxt; 1.989 + MA_CTI_O <= #UDLY MA_CTI_O_nxt; 1.990 + MA_ADR_O <= #UDLY MA_ADR_O_nxt; 1.991 + MA_SEL_O <= #UDLY MA_SEL_O_nxt; 1.992 + MB_CYC_O <= #UDLY MB_CYC_O_nxt; 1.993 + MB_CYC_O_d <= #UDLY MB_CYC_O; 1.994 + MB_STB_O <= #UDLY MB_STB_O_nxt; 1.995 + MB_CTI_O <= #UDLY MB_CTI_O_nxt; 1.996 + MB_ADR_O <= #UDLY MB_ADR_O_nxt; 1.997 + MB_SEL_O <= #UDLY MB_SEL_O_nxt; 1.998 + raddr_checkpoint <= #UDLY raddr_checkpoint_nxt; 1.999 + waddr_checkpoint <= #UDLY waddr_checkpoint_nxt; 1.1000 + save_wburst_count <= #UDLY save_wburst_count_nxt; 1.1001 end 1.1002 1.1003 - assign reg_status = reg_bt2 ? (reg_status1 | reg_status2) : reg_status_normal; 1.1004 - assign reg_interrupt = reg_bt2 ? (reg_interrupt1 | reg_interrupt2) : reg_interrupt_normal; 1.1005 - assign reg_cntlg = reg_bt2 ? reg_cntlg_burst : reg_cntlg_normal; 1.1006 - 1.1007 - 1.1008 - //FSM 1.1009 - always @(posedge CLK_I or posedge RST_I) 1.1010 - if(RST_I) 1.1011 - begin 1.1012 - status1 <= #UDLY ST_IDLE; 1.1013 - var_length1 <= #UDLY 1'b0; 1.1014 - MA_ADR_O <= #UDLY 32'h0; 1.1015 - MA_SEL_O <= #UDLY 4'b1111; 1.1016 - MA_CYC_O <= #UDLY 1'b0; 1.1017 - MA_CTI_O <= #UDLY 3'h0; 1.1018 - MA_STB_O <= #UDLY 1'b0; 1.1019 - reg_status1 <= #UDLY 1'b0; 1.1020 - reg_interrupt1 <= #UDLY 1'b0; 1.1021 - start_flag <= #UDLY 1'b0; 1.1022 - burst_size <= #UDLY 5'h0; 1.1023 - burst_cnt <= #UDLY 5'h0; 1.1024 - fifo_clear <= #UDLY 1'b0; 1.1025 - latch_start <= #UDLY 1'b0; 1.1026 - fifo_wr <= #UDLY 1'b0; 1.1027 - 1.1028 - status2 <= #UDLY ST_WRITE_IDLE; 1.1029 - MB_ADR_O <= #UDLY 32'h0; 1.1030 - MB_SEL_O <= #UDLY 4'b1111; 1.1031 - MB_CYC_O <= #UDLY 1'b0; 1.1032 - MB_CTI_O <= #UDLY 3'h0; 1.1033 - MB_STB_O <= #UDLY 1'b0; 1.1034 - reg_status2 <= #UDLY 1'b0; 1.1035 - reg_interrupt2 <= #UDLY 1'b0; 1.1036 - reg_cntlg_burst <= #UDLY 1'b0; 1.1037 - burst_size2 <= #UDLY 5'h0; 1.1038 - burst_cnt2 <= #UDLY 5'h0; 1.1039 - fifo_rd <= #UDLY 1'b0; 1.1040 - end_of_transfer <= #UDLY 1'b0; 1.1041 - var_length2 <= #UDLY 1'b0; 1.1042 - burst_completed <= #UDLY 1'b0; 1.1043 - donot_start_again <= #UDLY 1'b0; 1.1044 - 1.1045 - status <= #UDLY ST_IDLE1; 1.1046 - var_length <= #UDLY 1'b0; 1.1047 - reg_status_normal <= #UDLY 1'b0; 1.1048 - reg_interrupt_normal <= #UDLY 1'b0; 1.1049 - reg_cntlg_normal <= #UDLY 1'b0; 1.1050 - direct_data <= #UDLY 1'b0; 1.1051 - end 1.1052 - else 1.1053 - begin 1.1054 - if (reg_bt2) begin 1.1055 - // Read Burst 1.1056 - if ((MB_RTY_I && (!(|data_length))) || (MB_ERR_I && (status2 == ST_WRITE))) 1.1057 - begin 1.1058 - status1 <= #UDLY ST_IDLE; 1.1059 - end 1.1060 - else 1.1061 - begin 1.1062 - case(status1) 1.1063 - ST_IDLE: 1.1064 - begin 1.1065 - if(fifo_wr) 1.1066 - fifo_wr <= #UDLY 1'b0; 1.1067 - if(MA_ACK_I) 1.1068 - begin 1.1069 - MA_CYC_O <= #UDLY 1'b0; 1.1070 - MA_STB_O <= #UDLY 1'b0; 1.1071 - MA_CTI_O <= #UDLY 3'h0; 1.1072 - end 1.1073 - if(reg_start | latch_start) 1.1074 - begin 1.1075 - if(fifo_empty) 1.1076 - begin 1.1077 - if(latch_start) 1.1078 - latch_start <= #UDLY 1'b0; 1.1079 - status1 <= #UDLY ST_READ; 1.1080 - MA_CYC_O <= #UDLY 1'b1; 1.1081 - MA_STB_O <= #UDLY 1'b1; 1.1082 - MA_ADR_O <= #UDLY reg_00_data; 1.1083 - case (reg_00_data[1:0]) 1.1084 - 2'b01: MA_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 1.1085 - 2'b10: MA_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 1.1086 - 2'b11: MA_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 1.1087 - default: 1.1088 - MA_SEL_O <= #UDLY M_SEL_O; 1.1089 - endcase 1.1090 - set_cti_a; 1.1091 - start_flag <= #UDLY 1'b1; 1.1092 - if(!(|data_length)) 1.1093 - var_length1 <= #UDLY 1'b1; 1.1094 - else 1.1095 - var_length1 <= #UDLY 1'b0; 1.1096 - burst_size <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.1097 - burst_cnt <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.1098 - end 1.1099 - else 1.1100 - status1 <= #UDLY ST_RDFIFO; 1.1101 - end 1.1102 - else 1.1103 - status1 <= #UDLY ST_IDLE; 1.1104 - reg_interrupt1 <= #UDLY 1'b0; 1.1105 - end 1.1106 - 1.1107 - ST_WAIT_WRITE_FINISH: 1.1108 - begin 1.1109 - fifo_wr <= #UDLY 1'b0; 1.1110 - if (status2 == ST_WRITE) 1.1111 - start_flag <= #UDLY 1'b0; 1.1112 - if(end_of_transfer) 1.1113 - begin 1.1114 - if(!reg_s_con) 1.1115 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.1116 - if (incr_unit == 3'b001) 1.1117 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.1118 - else 1.1119 - if (incr_unit == 3'b010) 1.1120 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.1121 - 1.1122 - status1 <= #UDLY ST_RDADDR; 1.1123 - burst_cnt <= #UDLY burst_size; 1.1124 - end 1.1125 - else 1.1126 - begin 1.1127 - if(burst_completed) 1.1128 - status1 <= #UDLY ST_IDLE; 1.1129 - end 1.1130 - end 1.1131 - 1.1132 - ST_RDFIFO: 1.1133 - begin 1.1134 - if(fifo_empty) 1.1135 - begin 1.1136 - status1 <= #UDLY ST_IDLE; 1.1137 - fifo_clear <= #UDLY 1'b0; 1.1138 - latch_start <= #UDLY 1'b1; 1.1139 - end 1.1140 - else 1.1141 - fifo_clear <= #UDLY !fifo_clear; 1.1142 - end 1.1143 - 1.1144 - ST_RDADDR: 1.1145 - begin 1.1146 - MA_CYC_O <= #UDLY 1'b1; 1.1147 - MA_STB_O <= #UDLY 1'b1; 1.1148 - set_cti_a; 1.1149 - status1 <= #UDLY ST_READ; 1.1150 - end 1.1151 - 1.1152 - ST_READ: 1.1153 - begin 1.1154 - write_fifo; 1.1155 - if(MA_ACK_I) 1.1156 - begin 1.1157 - if(start_flag) 1.1158 - begin 1.1159 - if(burst_cnt == 0) 1.1160 - begin 1.1161 - MA_CYC_O <= #UDLY 1'b0; 1.1162 - MA_STB_O <= #UDLY 1'b0; 1.1163 - MA_CTI_O <= #UDLY 3'h0; 1.1164 - status1 <= #UDLY ST_WAIT_WRITE_FINISH; 1.1165 - end 1.1166 - else 1.1167 - begin 1.1168 - if(burst_cnt == 1) 1.1169 - MA_CTI_O <= #UDLY 3'h7; 1.1170 - burst_cnt <= #UDLY burst_cnt - 1; 1.1171 - if(!reg_s_con) 1.1172 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.1173 - if (incr_unit == 3'b001) 1.1174 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.1175 - else 1.1176 - if (incr_unit == 3'b010) 1.1177 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.1178 - end 1.1179 - end 1.1180 - else 1.1181 - begin 1.1182 - if(burst_cnt == 0) 1.1183 - begin 1.1184 - MA_CYC_O <= #UDLY 1'b0; 1.1185 - MA_STB_O <= #UDLY 1'b0; 1.1186 - MA_CTI_O <= #UDLY 3'h0; 1.1187 - status1 <= #UDLY ST_WAIT_WRITE_FINISH; 1.1188 - end 1.1189 - else 1.1190 - begin 1.1191 - if(burst_cnt == 1) 1.1192 - MA_CTI_O <= #UDLY 3'h7; 1.1193 - if(!reg_s_con) 1.1194 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.1195 - if (incr_unit == 3'b001) 1.1196 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.1197 - else 1.1198 - if (incr_unit == 3'b010) 1.1199 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.1200 - burst_cnt <= #UDLY burst_cnt - 1; 1.1201 - end 1.1202 - end 1.1203 - end 1.1204 - else if(MA_RTY_I) 1.1205 - begin 1.1206 - if(var_length1) 1.1207 - begin 1.1208 - MA_CYC_O <= #UDLY 1'b0; 1.1209 - MA_STB_O <= #UDLY 1'b0; 1.1210 - MA_CTI_O <= #UDLY 3'h0; 1.1211 - status1 <= #UDLY ST_IDLE; 1.1212 - reg_status1 <= #UDLY 1'b0; 1.1213 - reg_interrupt1 <= #UDLY 1'b1; 1.1214 - start_flag <= #UDLY 1'b0; 1.1215 - end 1.1216 - end 1.1217 - else if(MA_ERR_I) 1.1218 - begin 1.1219 - MA_CYC_O <= #UDLY 1'b0; 1.1220 - MA_STB_O <= #UDLY 1'b0; 1.1221 - MA_CTI_O <= #UDLY 3'h0; 1.1222 - status1 <= #UDLY ST_IDLE; 1.1223 - reg_status1 <= #UDLY 1'b1; 1.1224 - reg_interrupt1 <= #UDLY 1'b1; 1.1225 - start_flag <= #UDLY 1'b0; 1.1226 - end 1.1227 - end 1.1228 - 1.1229 - default: 1.1230 - begin 1.1231 - status1 <= #UDLY ST_IDLE; 1.1232 - var_length1 <= #UDLY 1'b0; 1.1233 - MA_ADR_O <= #UDLY 32'h0; 1.1234 - MA_SEL_O <= #UDLY 4'b1111; 1.1235 - MA_CYC_O <= #UDLY 1'b0; 1.1236 - MA_CTI_O <= #UDLY 3'h0; 1.1237 - MA_STB_O <= #UDLY 1'b0; 1.1238 - reg_status1 <= #UDLY 1'b0; 1.1239 - reg_interrupt1 <= #UDLY 1'b0; 1.1240 - start_flag <= #UDLY 1'b0; 1.1241 - burst_size <= #UDLY 5'h0; 1.1242 - burst_cnt <= #UDLY 5'h0; 1.1243 - fifo_clear <= #UDLY 1'b0; 1.1244 - latch_start <= #UDLY 1'b0; 1.1245 - fifo_wr <= #UDLY 1'b0; 1.1246 - end 1.1247 - endcase 1.1248 - end 1.1249 - // Write Burst 1.1250 - if ((MA_RTY_I && (!(|data_length))) || (MA_ERR_I && (status1 == ST_READ))) 1.1251 - begin 1.1252 - status2 <= #UDLY ST_WRITE_IDLE; 1.1253 - donot_start_again <= #UDLY 1'b1; 1.1254 - end 1.1255 - else 1.1256 - begin 1.1257 - case(status2) 1.1258 - ST_WRITE_IDLE: 1.1259 - begin 1.1260 - if(reg_start) 1.1261 - begin 1.1262 - MB_ADR_O <= #UDLY reg_04_data; 1.1263 - case (reg_04_data[1:0]) 1.1264 - 2'b01: MB_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 1.1265 - 2'b10: MB_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 1.1266 - 2'b11: MB_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 1.1267 - default: 1.1268 - MB_SEL_O <= #UDLY M_SEL_O; 1.1269 - endcase 1.1270 - if(!(|data_length)) 1.1271 - var_length2 <= #UDLY 1'b1; 1.1272 - else 1.1273 - var_length2 <= #UDLY 1'b0; 1.1274 - burst_size2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.1275 - burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.1276 - if(!fifo_empty) 1.1277 - status2 <= #UDLY ST_FIFO_EMPTY; 1.1278 - else 1.1279 - donot_start_again <= #UDLY 1'b0; 1.1280 - end 1.1281 - if(fifo_empty) 1.1282 - begin 1.1283 - if(MB_ACK_I) 1.1284 - begin 1.1285 - MB_CYC_O <= #UDLY 1'b0; 1.1286 - MB_STB_O <= #UDLY 1'b0; 1.1287 - MB_CTI_O <= #UDLY 3'h0; 1.1288 - fifo_rd <= #UDLY 1'b0; 1.1289 - end 1.1290 - burst_cnt2 <= #UDLY 5'h0; 1.1291 - end 1.1292 - else 1.1293 - begin 1.1294 - if(donot_start_again) 1.1295 - begin 1.1296 - if(MB_ACK_I) 1.1297 - begin 1.1298 - if(!reg_d_con) 1.1299 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.1300 - if (incr_unit == 3'b001) 1.1301 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.1302 - else 1.1303 - if (incr_unit == 3'b010) 1.1304 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.1305 - end 1.1306 - end 1.1307 - end 1.1308 - 1.1309 - if(!fifo_empty && !donot_start_again) 1.1310 - begin 1.1311 - if(start_flag) 1.1312 - begin 1.1313 - set_cti_b; 1.1314 - status2 <= #UDLY ST_WRITE_WAIT; 1.1315 - read_fifo; 1.1316 - burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.1317 - end 1.1318 - else 1.1319 - begin 1.1320 - if(!reg_d_con) 1.1321 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.1322 - if (incr_unit == 3'b001) 1.1323 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.1324 - else 1.1325 - if (incr_unit == 3'b010) 1.1326 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.1327 - status2 <= #UDLY ST_WRADDR; 1.1328 - read_fifo; 1.1329 - burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 1.1330 - end 1.1331 - end 1.1332 - end_of_transfer <= #UDLY 1'b0; 1.1333 - burst_completed <= #UDLY 1'b0; 1.1334 - reg_interrupt2 <= #UDLY 1'b0; 1.1335 - end 1.1336 - 1.1337 - ST_FIFO_EMPTY: 1.1338 - begin 1.1339 - if(fifo_empty) 1.1340 - begin 1.1341 - status2 <= #UDLY ST_WRITE_IDLE; 1.1342 - donot_start_again <= #UDLY 1'b0; 1.1343 - end 1.1344 - end 1.1345 - 1.1346 - ST_WRADDR: 1.1347 - begin 1.1348 - burst_cnt2 <= #UDLY burst_size2; 1.1349 - MB_CYC_O <= #UDLY 1'b1; 1.1350 - MB_STB_O <= #UDLY 1'b1; 1.1351 - 1.1352 - if (fifo_aempty && (burst_size2 > 5'h2)) 1.1353 - begin 1.1354 - MB_CTI_O <= #UDLY 3'b000; 1.1355 - status2 <= #UDLY ST_FIFO_AEMPTY; 1.1356 - fifo_rd <= #UDLY 1'b0; 1.1357 - end 1.1358 - else 1.1359 - begin 1.1360 - set_cti_b; 1.1361 - status2 <= #UDLY ST_WRITE; 1.1362 - end 1.1363 - end 1.1364 - 1.1365 - ST_WRITE_WAIT: 1.1366 - begin 1.1367 - MB_CYC_O <= #UDLY 1'b1; 1.1368 - MB_STB_O <= #UDLY 1'b1; 1.1369 - 1.1370 - if (fifo_aempty && (burst_size2 > 5'h2)) 1.1371 - begin 1.1372 - MB_CTI_O <= #UDLY 3'b000; 1.1373 - status2 <= #UDLY ST_FIFO_AEMPTY; 1.1374 - fifo_rd <= #UDLY 1'b0; 1.1375 - end 1.1376 - else 1.1377 - begin 1.1378 - set_cti_b; 1.1379 - status2 <= #UDLY ST_WRITE; 1.1380 - end 1.1381 - end 1.1382 - 1.1383 - ST_FIFO_AEMPTY: 1.1384 - begin 1.1385 - if (MB_ACK_I) 1.1386 - begin 1.1387 - MB_CYC_O <= #UDLY 1'b0; 1.1388 - MB_STB_O <= #UDLY 1'b0; 1.1389 - 1.1390 - burst_cnt2 <= #UDLY burst_cnt2 - 1; 1.1391 - 1.1392 - if (!reg_d_con) 1.1393 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.1394 - 1.1395 - if (incr_unit == 3'b001) 1.1396 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.1397 - else 1.1398 - if (incr_unit == 3'b010) 1.1399 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.1400 - end 1.1401 - 1.1402 - if (!MB_CYC_O && !fifo_aempty) 1.1403 - begin 1.1404 - status2 <= #UDLY ST_FIFO_RESUME; 1.1405 - read_fifo; 1.1406 - end 1.1407 - end 1.1408 - 1.1409 - ST_FIFO_RESUME: 1.1410 - begin 1.1411 - MB_CYC_O <= #UDLY 1'b1; 1.1412 - MB_STB_O <= #UDLY 1'b1; 1.1413 - 1.1414 - if (fifo_aempty && (burst_cnt2 > 5'h2)) 1.1415 - begin 1.1416 - MB_CTI_O <= #UDLY 3'b000; 1.1417 - status2 <= #UDLY ST_FIFO_AEMPTY; 1.1418 - fifo_rd <= #UDLY 1'b0; 1.1419 - end 1.1420 - else 1.1421 - begin 1.1422 - set_cti_b; 1.1423 - status2 <= #UDLY ST_WRITE; 1.1424 - end 1.1425 - end 1.1426 - 1.1427 - ST_WRITE: 1.1428 - begin 1.1429 - if (MB_ACK_I) 1.1430 - begin 1.1431 - if(var_length2) 1.1432 - begin 1.1433 - if(burst_cnt2 == 0) 1.1434 - begin 1.1435 - MB_CYC_O <= #UDLY 1'b0; 1.1436 - MB_STB_O <= #UDLY 1'b0; 1.1437 - MB_CTI_O <= #UDLY 3'h0; 1.1438 - end_of_transfer <= #UDLY 1'b1; 1.1439 - status2 <= #UDLY ST_WRITE_IDLE; 1.1440 - fifo_rd <= #UDLY 1'b0; 1.1441 - burst_cnt2 <= #UDLY burst_size2; 1.1442 - end 1.1443 - else 1.1444 - begin 1.1445 - if(burst_cnt2 == 1) 1.1446 - MB_CTI_O <= #UDLY 3'h7; 1.1447 - else 1.1448 - set_cti_b; 1.1449 - if(!reg_d_con) 1.1450 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.1451 - if (incr_unit == 3'b001) 1.1452 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.1453 - else 1.1454 - if (incr_unit == 3'b010) 1.1455 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.1456 - read_fifo; 1.1457 - burst_cnt2 <= #UDLY burst_cnt2 - 1; 1.1458 - end 1.1459 - end 1.1460 - else 1.1461 - begin 1.1462 - if(burst_cnt2 == 0) 1.1463 - begin 1.1464 - MB_CYC_O <= #UDLY 1'b0; 1.1465 - MB_STB_O <= #UDLY 1'b0; 1.1466 - MB_CTI_O <= #UDLY 3'h0; 1.1467 - reg_cntlg_burst <= #UDLY 1'b1; 1.1468 - status2 <= #UDLY ST_CNTLNGTH; 1.1469 - fifo_rd <= #UDLY 1'b0; 1.1470 - burst_cnt2 <= #UDLY burst_size2; 1.1471 - end 1.1472 - else 1.1473 - begin 1.1474 - if ((fifo_aempty && (burst_cnt2 > 5'h2)) || (burst_cnt2 == 5'h1)) 1.1475 - MB_CTI_O <= #UDLY 3'h7; 1.1476 - else 1.1477 - set_cti_b; 1.1478 - 1.1479 - burst_cnt2 <= #UDLY burst_cnt2 - 1; 1.1480 - 1.1481 - if(!reg_d_con) 1.1482 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.1483 - 1.1484 - if (incr_unit == 3'b001) 1.1485 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.1486 - else 1.1487 - if (incr_unit == 3'b010) 1.1488 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.1489 - 1.1490 - if (fifo_aempty && (burst_cnt2 > 5'h2)) 1.1491 - begin 1.1492 - status2 <= #UDLY ST_FIFO_AEMPTY; 1.1493 - fifo_rd <= 1'b0; 1.1494 - end 1.1495 - else 1.1496 - read_fifo; 1.1497 - end 1.1498 - end 1.1499 - end 1.1500 - 1.1501 - else if(MB_RTY_I) 1.1502 - begin 1.1503 - if(var_length2) 1.1504 - begin 1.1505 - MB_CYC_O <= #UDLY 1'b0; 1.1506 - MB_STB_O <= #UDLY 1'b0; 1.1507 - MB_CTI_O <= #UDLY 3'h0; 1.1508 - status2 <= #UDLY ST_WRITE_IDLE; 1.1509 - reg_status2 <= #UDLY 1'b0; 1.1510 - reg_interrupt2 <= #UDLY 1'b1; 1.1511 - var_length2 <= #UDLY 1'b0; 1.1512 - donot_start_again <= #UDLY 1'b1; 1.1513 - fifo_rd <= #UDLY 1'b0; 1.1514 - end 1.1515 - end // if (MB_RTY_I) 1.1516 - 1.1517 - else if(MB_ERR_I) 1.1518 - begin 1.1519 - MB_CYC_O <= #UDLY 1'b0; 1.1520 - MB_STB_O <= #UDLY 1'b0; 1.1521 - MB_CTI_O <= #UDLY 3'h0; 1.1522 - status2 <= #UDLY ST_WRITE_IDLE; 1.1523 - reg_status2 <= #UDLY 1'b1; 1.1524 - reg_interrupt2 <= #UDLY 1'b1; 1.1525 - donot_start_again <= #UDLY 1'b1; 1.1526 - fifo_rd <= #UDLY 1'b0; 1.1527 - end // if (MB_ERR_I) 1.1528 - 1.1529 - end 1.1530 - 1.1531 - ST_CNTLNGTH: 1.1532 - begin 1.1533 - reg_cntlg_burst <= #UDLY 1'b0; 1.1534 - status2 <= #UDLY ST_JUSTICE; 1.1535 - end 1.1536 - 1.1537 - ST_JUSTICE: 1.1538 - begin 1.1539 - if(!(|data_length)) 1.1540 - begin 1.1541 - status2 <= #UDLY ST_WRITE_IDLE; 1.1542 - reg_status2 <= #UDLY 1'b0; 1.1543 - reg_interrupt2 <= #UDLY 1'b1; 1.1544 - burst_completed <= #UDLY 1'b1; 1.1545 - end 1.1546 - else 1.1547 - begin 1.1548 - end_of_transfer <= #UDLY 1'b1; 1.1549 - status2 <= ST_WRITE_IDLE; 1.1550 - end 1.1551 - end 1.1552 - 1.1553 - default: 1.1554 - begin 1.1555 - status2 <= #UDLY ST_WRITE_IDLE; 1.1556 - MB_ADR_O <= #UDLY 32'h0; 1.1557 - MB_SEL_O <= #UDLY 4'b1111; 1.1558 - MB_CYC_O <= #UDLY 1'b0; 1.1559 - MB_CTI_O <= #UDLY 3'h0; 1.1560 - MB_STB_O <= #UDLY 1'b0; 1.1561 - reg_status2 <= #UDLY 1'b0; 1.1562 - reg_interrupt2 <= #UDLY 1'b0; 1.1563 - reg_cntlg_burst <= #UDLY 1'b0; 1.1564 - burst_size2 <= #UDLY 5'h0; 1.1565 - burst_cnt2 <= #UDLY 5'h0; 1.1566 - fifo_rd <= #UDLY 1'b0; 1.1567 - end_of_transfer <= #UDLY 1'b0; 1.1568 - var_length2 <= #UDLY 1'b0; 1.1569 - burst_completed <= #UDLY 1'b0; 1.1570 - donot_start_again <= #UDLY 1'b0; 1.1571 - end 1.1572 - endcase 1.1573 - end 1.1574 - end 1.1575 - else begin 1.1576 - // Read/Write Normal 1.1577 - case(status) 1.1578 - 1.1579 - ST_IDLE1: 1.1580 - begin 1.1581 - if(reg_start | latch_start) 1.1582 - begin 1.1583 - if(fifo_empty) 1.1584 - begin 1.1585 - if(latch_start) 1.1586 - latch_start <= #UDLY 1'b0; 1.1587 - status <= #UDLY ST_READ1; 1.1588 - MA_CYC_O <= #UDLY 1'b1; 1.1589 - MA_STB_O <= #UDLY 1'b1; 1.1590 - MA_ADR_O <= #UDLY reg_00_data; 1.1591 - case (reg_00_data[1:0]) 1.1592 - 2'b01: MA_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 1.1593 - 2'b10: MA_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 1.1594 - 2'b11: MA_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 1.1595 - default: 1.1596 - MA_SEL_O <= #UDLY M_SEL_O; 1.1597 - endcase 1.1598 - MB_ADR_O <= #UDLY reg_04_data; 1.1599 - case (reg_04_data[1:0]) 1.1600 - 2'b01: MB_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 1.1601 - 2'b10: MB_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 1.1602 - 2'b11: MB_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 1.1603 - default: 1.1604 - MB_SEL_O <= #UDLY M_SEL_O; 1.1605 - endcase 1.1606 - set_cti_a; 1.1607 - start_flag <= #UDLY 1'b1; 1.1608 - if(!(|data_length)) 1.1609 - var_length <= #UDLY 1'b1; 1.1610 - else 1.1611 - var_length <= #UDLY 1'b0; 1.1612 - burst_size <= #UDLY 5'h0; 1.1613 - burst_cnt <= #UDLY 5'h0; 1.1614 - end 1.1615 - else 1.1616 - begin 1.1617 - status <= #UDLY ST_RDFIFO1; 1.1618 - end 1.1619 - end 1.1620 - else 1.1621 - begin 1.1622 - status <= #UDLY ST_IDLE1; 1.1623 - end 1.1624 - reg_interrupt_normal <= #UDLY 1'b0; 1.1625 - end 1.1626 - ST_RDFIFO1: 1.1627 - begin 1.1628 - if(fifo_empty) 1.1629 - begin 1.1630 - status <= #UDLY ST_IDLE1; 1.1631 - fifo_clear <= #UDLY 1'b0; 1.1632 - latch_start <= #UDLY 1'b1; 1.1633 - end 1.1634 - else 1.1635 - fifo_clear <= #UDLY !fifo_clear; 1.1636 - end 1.1637 - 1.1638 - ST_RDADDR1: 1.1639 - begin 1.1640 - MA_CYC_O <= #UDLY 1'b1; 1.1641 - MA_STB_O <= #UDLY 1'b1; 1.1642 - set_cti_a; 1.1643 - status <= #UDLY ST_READ1; 1.1644 - direct_data <= #UDLY 1'b1; 1.1645 - end 1.1646 - 1.1647 - ST_READ1: 1.1648 - begin 1.1649 - if(!start_flag) 1.1650 - write_fifo; 1.1651 - if(MA_ACK_I) 1.1652 - begin 1.1653 - if(start_flag) 1.1654 - begin 1.1655 - MA_CYC_O <= #UDLY 1'b0; 1.1656 - MA_STB_O <= #UDLY 1'b0; 1.1657 - MA_CTI_O <= #UDLY 3'h0; 1.1658 - MB_CYC_O <= #UDLY 1'b1; 1.1659 - MB_STB_O <= #UDLY 1'b1; 1.1660 - set_cti_b; 1.1661 - status <= #UDLY ST_WRITE1; 1.1662 - start_flag <= #UDLY 1'b0; 1.1663 - burst_cnt <= #UDLY burst_size; 1.1664 - end 1.1665 - else 1.1666 - begin 1.1667 - MA_CYC_O <= #UDLY 1'b0; 1.1668 - MA_STB_O <= #UDLY 1'b0; 1.1669 - MA_CTI_O <= #UDLY 3'h0; 1.1670 - if(!reg_d_con) 1.1671 - begin 1.1672 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 1.1673 - if (incr_unit == 3'b001) 1.1674 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 1.1675 - else 1.1676 - if (incr_unit == 3'b010) 1.1677 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 1.1678 - end 1.1679 - status <= #UDLY ST_WRADDR1; 1.1680 - burst_cnt <= #UDLY burst_size; 1.1681 - end 1.1682 - end 1.1683 - else if(MA_RTY_I) 1.1684 - begin 1.1685 - if(var_length) 1.1686 - begin 1.1687 - MA_CYC_O <= #UDLY 1'b0; 1.1688 - MA_STB_O <= #UDLY 1'b0; 1.1689 - MA_CTI_O <= #UDLY 3'h0; 1.1690 - status <= #UDLY ST_IDLE1; 1.1691 - reg_status_normal <= #UDLY 1'b0; 1.1692 - reg_interrupt_normal <= #UDLY 1'b1; 1.1693 - end 1.1694 - end 1.1695 - else if(MA_ERR_I) 1.1696 - begin 1.1697 - MA_CYC_O <= #UDLY 1'b0; 1.1698 - MA_STB_O <= #UDLY 1'b0; 1.1699 - MA_CTI_O <= #UDLY 3'h0; 1.1700 - status <= #UDLY ST_IDLE1; 1.1701 - reg_status_normal <= #UDLY 1'b1; 1.1702 - reg_interrupt_normal <= #UDLY 1'b1; 1.1703 - end 1.1704 - end 1.1705 - 1.1706 - ST_WRADDR1: 1.1707 - begin 1.1708 - fifo_wr <= #UDLY 1'b0; 1.1709 - MB_CYC_O <= #UDLY 1'b1; 1.1710 - MB_STB_O <= #UDLY 1'b1; 1.1711 - burst_cnt <= #UDLY burst_size; 1.1712 - set_cti_b; 1.1713 - status <= #UDLY ST_WRITE1; 1.1714 - read_fifo; 1.1715 - end 1.1716 - 1.1717 - ST_WRITE1: 1.1718 - begin 1.1719 - if(fifo_wr) 1.1720 - fifo_wr <= #UDLY 1'b0; 1.1721 - if(MB_ACK_I) 1.1722 - begin 1.1723 - direct_data <= #UDLY 1'b0; 1.1724 - if(var_length) 1.1725 - begin 1.1726 - MB_CYC_O <= #UDLY 1'b0; 1.1727 - MB_STB_O <= #UDLY 1'b0; 1.1728 - MB_CTI_O <= #UDLY 3'h0; 1.1729 - if(!reg_s_con) 1.1730 - begin 1.1731 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.1732 - if (incr_unit == 3'b001) 1.1733 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.1734 - else 1.1735 - if (incr_unit == 3'b010) 1.1736 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.1737 - end 1.1738 - status <= #UDLY ST_RDADDR1; 1.1739 - fifo_rd <= #UDLY 1'b0; 1.1740 - burst_cnt <= #UDLY burst_size; 1.1741 - end 1.1742 - else 1.1743 - begin 1.1744 - MB_CYC_O <= #UDLY 1'b0; 1.1745 - MB_STB_O <= #UDLY 1'b0; 1.1746 - MB_CTI_O <= #UDLY 3'h0; 1.1747 - reg_cntlg_normal <= #UDLY 1'b1; 1.1748 - status <= #UDLY ST_CNTLNGTH1; 1.1749 - fifo_rd <= #UDLY 1'b0; 1.1750 - burst_cnt <= #UDLY burst_size; 1.1751 - end 1.1752 - end 1.1753 - else if(MB_RTY_I) 1.1754 - begin 1.1755 - if(var_length) 1.1756 - begin 1.1757 - MB_CYC_O <= #UDLY 1'b0; 1.1758 - MB_STB_O <= #UDLY 1'b0; 1.1759 - MB_CTI_O <= #UDLY 3'h0; 1.1760 - status <= #UDLY ST_IDLE1; 1.1761 - reg_status_normal <= #UDLY 1'b0; 1.1762 - reg_interrupt_normal <= #UDLY 1'b1; 1.1763 - var_length <= #UDLY 1'b0; 1.1764 - fifo_rd <= #UDLY 1'b0; 1.1765 - end 1.1766 - end 1.1767 - else if(MB_ERR_I) 1.1768 - begin 1.1769 - MB_CYC_O <= #UDLY 1'b0; 1.1770 - MB_STB_O <= #UDLY 1'b0; 1.1771 - MB_CTI_O <= #UDLY 3'h0; 1.1772 - status <= #UDLY ST_IDLE1; 1.1773 - reg_status_normal <= #UDLY 1'b1; 1.1774 - reg_interrupt_normal <= #UDLY 1'b1; 1.1775 - fifo_rd <= #UDLY 1'b0; 1.1776 - end 1.1777 - end 1.1778 - 1.1779 - ST_CNTLNGTH1: 1.1780 - begin 1.1781 - reg_cntlg_normal <= #UDLY 1'b0; 1.1782 - status <= #UDLY ST_JUSTICE1; 1.1783 - end 1.1784 - 1.1785 - ST_JUSTICE1: 1.1786 - begin 1.1787 - if(!(|data_length)) 1.1788 - begin 1.1789 - status <= #UDLY ST_IDLE1; 1.1790 - reg_status_normal <= #UDLY 1'b0; 1.1791 - reg_interrupt_normal <= #UDLY 1'b1; 1.1792 - end 1.1793 - else 1.1794 - begin 1.1795 - if(!reg_s_con) 1.1796 - begin 1.1797 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 1.1798 - if (incr_unit == 3'b001) 1.1799 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 1.1800 - else 1.1801 - if (incr_unit == 3'b010) 1.1802 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 1.1803 - end 1.1804 - status <= #UDLY ST_RDADDR1; 1.1805 - end 1.1806 - end 1.1807 - 1.1808 - default: 1.1809 - begin 1.1810 - status <= #UDLY ST_IDLE1; 1.1811 - var_length <= #UDLY 1'b0; 1.1812 - MA_CYC_O <= #UDLY 1'b0; 1.1813 - MA_CTI_O <= #UDLY 3'h0; 1.1814 - MB_CYC_O <= #UDLY 1'b0; 1.1815 - MB_CTI_O <= #UDLY 3'h0; 1.1816 - MA_STB_O <= #UDLY 1'b0; 1.1817 - MB_STB_O <= #UDLY 1'b0; 1.1818 - reg_status_normal <= #UDLY 1'b0; 1.1819 - reg_interrupt_normal <= #UDLY 1'b0; 1.1820 - reg_cntlg_normal <= #UDLY 1'b0; 1.1821 - burst_size <= #UDLY 3'h0; 1.1822 - burst_cnt <= #UDLY 3'h0; 1.1823 - fifo_wr <= #UDLY 1'b0; 1.1824 - fifo_rd <= #UDLY 1'b0; 1.1825 - fifo_clear <= #UDLY 1'b0; 1.1826 - latch_start <= #UDLY 1'b0; 1.1827 - direct_data <= #UDLY 1'b0; 1.1828 - end 1.1829 - endcase 1.1830 - end 1.1831 - end 1.1832 - 1.1833 - //Task for generating write enable to the FIFO 1.1834 - task write_fifo; 1.1835 - begin 1.1836 - if(MA_ACK_I) 1.1837 - begin 1.1838 - fifo_wr <= #UDLY 1'b1; 1.1839 - fifo_din <= #UDLY MA_DAT_I; 1.1840 - end 1.1841 - else 1.1842 - begin 1.1843 - fifo_wr <= #UDLY 1'b0; 1.1844 - end 1.1845 - end 1.1846 - endtask 1.1847 - 1.1848 - //Task for generating read enable signal to the FIFO 1.1849 - task read_fifo; 1.1850 - begin 1.1851 - fifo_rd <= #UDLY 1'b1; 1.1852 - end 1.1853 - endtask 1.1854 - 1.1855 - //Task for setting wishbone CTI signal for read 1.1856 - //master port depending upon whether request is for burst 1.1857 - //transfer or classic cycle. 1.1858 - task set_cti_a; 1.1859 - begin 1.1860 - if(reg_bt2) 1.1861 - begin 1.1862 - if(reg_s_con) 1.1863 - MA_CTI_O <= #UDLY 3'b001; 1.1864 - else 1.1865 - MA_CTI_O <= #UDLY 3'b010; 1.1866 - end 1.1867 - else 1.1868 - MA_CTI_O <= #UDLY 3'b000; 1.1869 - end 1.1870 - endtask 1.1871 - 1.1872 - //Task for setting wishbone CTI signal for write 1.1873 - //master port depending upon whether request is for burst 1.1874 - //transfer or classic cycle. 1.1875 - task set_cti_b; 1.1876 - begin 1.1877 - if(reg_bt2) begin 1.1878 - if(reg_d_con) 1.1879 - MB_CTI_O <= #UDLY 3'b001; 1.1880 - else 1.1881 - MB_CTI_O <= #UDLY 3'b010; 1.1882 - end else 1.1883 - MB_CTI_O <= #UDLY 3'b000; 1.1884 - end 1.1885 - endtask 1.1886 - 1.1887 - //RdEn 1.1888 - reg fifo_rd_dly; 1.1889 - always @(posedge CLK_I or posedge RST_I) 1.1890 - if(RST_I) 1.1891 - fifo_rd_dly <= #UDLY 1'b0; 1.1892 - else 1.1893 - fifo_rd_dly <= #UDLY fifo_rd; 1.1894 - 1.1895 - wire RdEn = fifo_rd & (!fifo_rd_dly | (reg_bt2 ? (burst_cnt2[5:0] != 5'b00000) : (burst_cnt[5:0] != 5'b00000)) & MB_ACK_I) | fifo_clear; 1.1896 - 1.1897 + /*---------------------------------------------------------------------- 1.1898 + FIFO Logic 1.1899 + ----------------------------------------------------------------------*/ 1.1900 + reg fifo_rd_en, fifo_wr_en; 1.1901 + always @(/*AUTOSENSE*/MA_ACK_I or MA_DAT_I or MB_ACK_I 1.1902 + or fifo_aempty or fifo_empty or rstate or wburst_count 1.1903 + or wstate) 1.1904 + begin 1.1905 + if (((wstate == WR_SINGLEA) && (fifo_empty == 1'b0)) 1.1906 + || ((wstate == WR_FIFO_CHECK) 1.1907 + && (((fifo_empty == 1'b0) && (wburst_count == 6'h0)) 1.1908 + || ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1)))) 1.1909 + || ((wstate == WR_BURST) 1.1910 + && (/*(MB_CYC_O_d == 1'b0) 1.1911 + ||*/ (MB_ACK_I && (wburst_count >= 6'h1)))) 1.1912 + || ((wstate == WR_ERROR) && (fifo_empty == 1'b0)) 1.1913 + || ((wstate == WR_RETRY) && (fifo_empty == 1'b0))) 1.1914 + fifo_rd_en = 1'b1; 1.1915 + else 1.1916 + fifo_rd_en = 1'b0; 1.1917 + 1.1918 + if (MA_ACK_I 1.1919 + && ((rstate == RD_SINGLEA) || (rstate == RD_BURST))) 1.1920 + fifo_wr_en = 1'b1; 1.1921 + else 1.1922 + fifo_wr_en = 1'b0; 1.1923 + 1.1924 + fifo_din = MA_DAT_I; 1.1925 + end 1.1926 + 1.1927 generate 1.1928 if (lat_family == "SC" || lat_family == "SCM") begin 1.1929 + 1.1930 + pmi_fifo_dc 1.1931 + #(.pmi_data_width_w(MA_WB_DAT_WIDTH), 1.1932 + .pmi_data_width_r(MA_WB_DAT_WIDTH), 1.1933 + .pmi_data_depth_w(64), 1.1934 + .pmi_data_depth_r(64), 1.1935 + .pmi_full_flag(64), 1.1936 + .pmi_empty_flag(0), 1.1937 + .pmi_almost_full_flag(60), 1.1938 + .pmi_almost_empty_flag(4), 1.1939 + .pmi_regmode("noreg"), 1.1940 + .pmi_family(`LATTICE_FAMILY), 1.1941 + .module_type("pmi_fifo_dc"), 1.1942 + .pmi_implementation(FIFO_IMPLEMENTATION)) 1.1943 + dma_fifo_dc 1.1944 + ( 1.1945 + .Data(fifo_din), 1.1946 + .WrClock (CLK_I), 1.1947 + .RdClock (CLK_I), 1.1948 + .WrEn (fifo_wr_en), 1.1949 + .RdEn (fifo_rd_en), 1.1950 + .Reset (RST_I), 1.1951 + .RPReset (RST_I), 1.1952 + .Q (fifo_dout), 1.1953 + .Empty (fifo_empty), 1.1954 + .Full (), 1.1955 + .AlmostEmpty(), 1.1956 + .AlmostFull ()); 1.1957 + 1.1958 + end else if (lat_family == "MachXO2") begin 1.1959 + 1.1960 + pmi_fifo_dc 1.1961 + #(.pmi_data_width_w (MA_WB_DAT_WIDTH), 1.1962 + .pmi_data_width_r (MA_WB_DAT_WIDTH), 1.1963 + .pmi_data_depth_w (64), 1.1964 + .pmi_data_depth_r (64), 1.1965 + .pmi_full_flag (64), 1.1966 + .pmi_empty_flag (0), 1.1967 + .pmi_almost_full_flag (60), 1.1968 + .pmi_almost_empty_flag (1), 1.1969 + .pmi_regmode ("noreg"), 1.1970 + .pmi_family ("XO2"), 1.1971 + .module_type ("pmi_fifo_dc"), 1.1972 + .pmi_implementation (FIFO_IMPLEMENTATION)) 1.1973 + dma_fifo 1.1974 + (.Data (fifo_din), 1.1975 + .WrClock (CLK_I), 1.1976 + .RdClock (CLK_I), 1.1977 + .WrEn (fifo_wr_en), 1.1978 + .RdEn (fifo_rd_en), 1.1979 + .Reset (RST_I), 1.1980 + .RPReset (RST_I), 1.1981 + .Q (fifo_dout), 1.1982 + .Empty (fifo_empty), 1.1983 + .Full (), 1.1984 + .AlmostEmpty(fifo_aempty), 1.1985 + .AlmostFull ()); 1.1986 1.1987 - pmi_fifo_dc #(.pmi_data_width_w(32), 1.1988 - .pmi_data_width_r(32), 1.1989 - .pmi_data_depth_w(32), 1.1990 - .pmi_data_depth_r(32), 1.1991 - .pmi_full_flag(32), 1.1992 - .pmi_empty_flag(0), 1.1993 - .pmi_almost_full_flag(28), 1.1994 - .pmi_almost_empty_flag(4), 1.1995 - .pmi_regmode("noreg"), 1.1996 - .pmi_family(`LATTICE_FAMILY), 1.1997 - .module_type("pmi_fifo_dc"), 1.1998 - .pmi_implementation(FIFO_IMPLEMENTATION)) 1.1999 - dma_fifo_dc ( 1.2000 - .Data(fifo_din), 1.2001 - .WrClock(CLK_I), 1.2002 - .RdClock(CLK_I), 1.2003 - .WrEn (fifo_wr), 1.2004 - .RdEn (RdEn), 1.2005 - .Reset (RST_I), 1.2006 - .RPReset(RST_I), 1.2007 - .Q (fifo_dout), 1.2008 - .Empty (fifo_empty), 1.2009 - .Full (), 1.2010 - .AlmostEmpty (), 1.2011 - .AlmostFull ()); 1.2012 - 1.2013 - 1.2014 - 1.2015 end else begin 1.2016 - pmi_fifo #(.pmi_data_width(32), 1.2017 - .pmi_data_depth(32), 1.2018 - .pmi_full_flag(32), 1.2019 - .pmi_empty_flag(0), 1.2020 - .pmi_almost_full_flag(28), 1.2021 - .pmi_almost_empty_flag(1), 1.2022 - .pmi_regmode("noreg"), 1.2023 - .pmi_family(`LATTICE_FAMILY), 1.2024 - .module_type("pmi_fifo"), 1.2025 - .pmi_implementation(FIFO_IMPLEMENTATION)) 1.2026 - dma_fifo (.Data (fifo_din), 1.2027 - .Clock (CLK_I), 1.2028 - .WrEn (fifo_wr), 1.2029 - .RdEn (RdEn), 1.2030 - .Reset (RST_I), 1.2031 - .Q (fifo_dout), 1.2032 - .Empty (fifo_empty), 1.2033 - .Full (), 1.2034 - .AlmostEmpty (fifo_aempty), 1.2035 - .AlmostFull ()); 1.2036 - end 1.2037 + 1.2038 + pmi_fifo 1.2039 + #(.pmi_data_width(MA_WB_DAT_WIDTH), 1.2040 + .pmi_data_depth(64), 1.2041 + .pmi_full_flag(64), 1.2042 + .pmi_empty_flag(0), 1.2043 + .pmi_almost_full_flag(60), 1.2044 + .pmi_almost_empty_flag(1), 1.2045 + .pmi_regmode("noreg"), 1.2046 + .pmi_family(`LATTICE_FAMILY), 1.2047 + .module_type("pmi_fifo"), 1.2048 + .pmi_implementation(FIFO_IMPLEMENTATION)) 1.2049 + dma_fifo 1.2050 + (.Data (fifo_din), 1.2051 + .Clock (CLK_I), 1.2052 + .WrEn (fifo_wr_en), 1.2053 + .RdEn (fifo_rd_en), 1.2054 + .Reset (RST_I), 1.2055 + .Q (fifo_dout), 1.2056 + .Empty (fifo_empty), 1.2057 + .Full (), 1.2058 + .AlmostEmpty(fifo_aempty), 1.2059 + .AlmostFull ()); 1.2060 + 1.2061 + end 1.2062 + 1.2063 endgenerate 1.2064 1.2065 -endmodule // MASTER_CTRL 1.2066 +endmodule 1.2067 1.2068 -`endif // MASTER_CTRL_FILE 1.2069 +`endif // `ifndef MASTER_CTRL_FILE