Sat, 06 Aug 2011 01:43:24 +0100
Update to latest Lattice code dump (LM32 V3.8, GPIO V3.2)
Version : 3.2
Mod. Data : Jun 6, 2010
Changes Made : 1. Provide capability to read/write bytes (when GPIO larger than 8 bits wide)
2. Provide capability to use a 32-bit or 8-bit data bus on the WISHBONE slave port
3. Perform a big-endian to little-endian conversion in hardware
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 // ------------------------------------------------------------------
4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5 // ALL RIGHTS RESERVED
6 // ------------------------------------------------------------------
7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 //
10 // Permission:
11 //
12 // Lattice Semiconductor grants permission to use this code
13 // pursuant to the terms of the Lattice Semiconductor Corporation
14 // Open Source License Agreement.
15 //
16 // Disclaimer:
17 //
18 // Lattice Semiconductor provides no warranty regarding the use or
19 // functionality of this code. It is the user's responsibility to
20 // verify the user’s design for consistency and functionality through
21 // the use of formal verification methods.
22 //
23 // --------------------------------------------------------------------
24 //
25 // Lattice Semiconductor Corporation
26 // 5555 NE Moore Court
27 // Hillsboro, OR 97214
28 // U.S.A
29 //
30 // TEL: 1-800-Lattice (USA and Canada)
31 // 503-286-8001 (other locations)
32 //
33 // web: http://www.latticesemi.com/
34 // email: techsupport@latticesemi.com
35 //
36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : GPIO for LM32
39 // File : gpio.v
40 // Title : General Purpose IO Component
41 // Dependencies : system_conf.v
42 // Description : Implements the logic to interface general purpuse IO with
43 // Wishbone bus.
44 // =============================================================================
45 // REVISION HISTORY
46 // Version : 7.0
47 // Mod. Date : Jun 27, 2005
48 // Changes Made : Initial Creation
49 //
50 // Version : 7.0SP2, 3.0
51 // Mod. Date : 20 Nov. 2007
52 // Changes Made : Code clean up.
53 //
54 // Version : 3.1
55 // Mod. Date : 11 Oct. 2008
56 // Changes Made : Update the Edge Capture Register clean method
57 // Make IRQ Mask register readable
58 //
59 // Version : 3.2
60 // Mod. Data : Jun 6, 2010
61 // Changes Made : 1. Provide capability to read/write bytes (when GPIO larger
62 // than 8 bits wide)
63 // 2. Provide capability to use a 32-bit or 8-bit data bus on
64 // the WISHBONE slave port
65 // 3. Perform a big-endian to little-endian conversion in
66 // hardware
67 // =============================================================================
68 `ifndef GPIO_V
69 `define GPIO_V
70 `timescale 1ns/100 ps
71 `include "system_conf.v"
72 module gpio
73 #(
74 parameter GPIO_WB_DAT_WIDTH = 32,
75 parameter GPIO_WB_ADR_WIDTH = 4,
76 parameter DATA_WIDTH = 16,
77 parameter INPUT_WIDTH = 16,
78 parameter OUTPUT_WIDTH = 16,
79 parameter IRQ_MODE = 0,
80 parameter LEVEL = 0,
81 parameter EDGE = 0,
82 parameter POSE_EDGE_IRQ = 0,
83 parameter NEGE_EDGE_IRQ = 0,
84 parameter EITHER_EDGE_IRQ = 0,
85 parameter INPUT_PORTS_ONLY = 1,
86 parameter OUTPUT_PORTS_ONLY = 0,
87 parameter BOTH_INPUT_AND_OUTPUT = 0,
88 parameter TRISTATE_PORTS = 0
89 )
90 (
91 // system clock and reset
92 input CLK_I,
93 input RST_I,
95 // wishbone interface signals
96 input GPIO_CYC_I,
97 input GPIO_STB_I,
98 input GPIO_WE_I,
99 input GPIO_LOCK_I,
100 input [2:0] GPIO_CTI_I,
101 input [1:0] GPIO_BTE_I,
102 input [GPIO_WB_ADR_WIDTH-1:0] GPIO_ADR_I,
103 input [GPIO_WB_DAT_WIDTH-1:0] GPIO_DAT_I,
104 input [GPIO_WB_DAT_WIDTH/8-1:0] GPIO_SEL_I,
105 output reg GPIO_ACK_O,
106 output GPIO_ERR_O,
107 output GPIO_RTY_O,
108 output [GPIO_WB_DAT_WIDTH-1:0] GPIO_DAT_O,
110 output IRQ_O,
112 // PIO side
113 input [DATA_WIDTH-1:0] PIO_IN,
114 input [INPUT_WIDTH-1:0] PIO_BOTH_IN,
115 output [DATA_WIDTH-1:0] PIO_OUT,
116 output [OUTPUT_WIDTH-1:0] PIO_BOTH_OUT,
117 inout [DATA_WIDTH-1:0] PIO_IO
118 );
120 // The incoming data bus is big-endian and the internal memory-mapped registers of GPIO
121 // component are little-endian. Performing a big-endian to little-endian conversion!
122 wire [GPIO_WB_DAT_WIDTH-1:0] GPIO_DAT_I_switch, GPIO_DAT_O_switch;
123 wire [GPIO_WB_DAT_WIDTH/8-1:0] GPIO_SEL_I_switch;
124 generate
125 if (GPIO_WB_DAT_WIDTH == 8) begin
126 assign GPIO_DAT_I_switch = GPIO_DAT_I;
127 assign GPIO_SEL_I_switch = GPIO_SEL_I;
128 assign GPIO_DAT_O = GPIO_DAT_O_switch;
129 end
130 else begin
131 assign GPIO_DAT_I_switch = {GPIO_DAT_I[7:0], GPIO_DAT_I[15:8], GPIO_DAT_I[23:16], GPIO_DAT_I[31:24]};
132 assign GPIO_SEL_I_switch = {GPIO_SEL_I[0], GPIO_SEL_I[1], GPIO_SEL_I[2], GPIO_SEL_I[3]};
133 assign GPIO_DAT_O = {GPIO_DAT_O_switch[7:0], GPIO_DAT_O_switch[15:8], GPIO_DAT_O_switch[23:16], GPIO_DAT_O_switch[31:24]};
134 end
135 endgenerate
137 reg [OUTPUT_WIDTH-1:0] PIO_DATAO;
138 reg [INPUT_WIDTH-1:0] PIO_DATAI;
139 wire ADR_0, ADR_4, ADR_8, ADR_C;
140 wire [DATA_WIDTH-1:0] tpio_out;
142 wire PIO_DATA_WR_EN;
143 wire PIO_DATA_WR_EN_0, PIO_DATA_WR_EN_1, PIO_DATA_WR_EN_2, PIO_DATA_WR_EN_3;
145 wire PIO_TRI_WR_EN;
146 wire PIO_TRI_WR_EN_0, PIO_TRI_WR_EN_1, PIO_TRI_WR_EN_2, PIO_TRI_WR_EN_3;
148 wire IRQ_MASK_WR_EN;
149 wire IRQ_MASK_WR_EN_0, IRQ_MASK_WR_EN_1, IRQ_MASK_WR_EN_2, IRQ_MASK_WR_EN_3;
151 wire EDGE_CAP_WR_EN;
152 wire EDGE_CAP_WR_EN_0, EDGE_CAP_WR_EN_1, EDGE_CAP_WR_EN_2, EDGE_CAP_WR_EN_3;
154 wire PIO_DATA_RE_EN;
155 wire PIO_TRI_RE_EN;
156 wire IRQ_MASK_RE_EN;
157 wire [DATA_WIDTH-1:0] IRQ_TRI_TEMP;
158 reg [DATA_WIDTH-1:0] PIO_DATA;
159 reg [DATA_WIDTH-1:0] IRQ_MASK;
160 reg [INPUT_WIDTH-1:0] IRQ_MASK_BOTH;
161 reg [DATA_WIDTH-1:0] IRQ_TEMP;
162 reg [INPUT_WIDTH-1:0] IRQ_TEMP_BOTH;
163 reg [DATA_WIDTH-1:0] EDGE_CAPTURE;
164 reg [INPUT_WIDTH-1:0] EDGE_CAPTURE_BOTH;
165 reg [DATA_WIDTH-1:0] PIO_DATA_DLY;
166 reg [INPUT_WIDTH-1:0] PIO_DATA_DLY_BOTH;
168 parameter UDLY = 1;
170 assign GPIO_RTY_O = 1'b0;
171 assign GPIO_ERR_O = 1'b0;
172 assign ADR_0 = (GPIO_ADR_I[3:2] == 4'b00 ? 1'b1 : 0); // IO Data
173 assign ADR_4 = (GPIO_ADR_I[3:2] == 4'b01 ? 1'b1 : 0); // Tri-state Control
174 assign ADR_8 = (GPIO_ADR_I[3:2] == 4'b10 ? 1'b1 : 0); // IRQ Mask
175 assign ADR_C = (GPIO_ADR_I[3:2] == 4'b11 ? 1'b1 : 0); // Edge Capture
177 always @(posedge CLK_I or posedge RST_I)
178 if(RST_I)
179 GPIO_ACK_O <= #UDLY 1'b0;
180 else if(GPIO_STB_I && (GPIO_ACK_O == 1'b0))
181 GPIO_ACK_O <= #UDLY 1'b1;
182 else
183 GPIO_ACK_O <= #UDLY 1'b0;
186 generate
187 if (INPUT_PORTS_ONLY == 1) begin
188 always @(posedge CLK_I or posedge RST_I)
189 if (RST_I)
190 PIO_DATA <= #UDLY 0;
191 else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:2] == 2'b00)
192 PIO_DATA <= #UDLY PIO_IN;
193 end
194 endgenerate
196 generate
197 if (OUTPUT_PORTS_ONLY == 1) begin
198 if (GPIO_WB_DAT_WIDTH == 8) begin
199 genvar ipd_idx;
200 for (ipd_idx = 0; (ipd_idx < DATA_WIDTH) && (ipd_idx < 8); ipd_idx = ipd_idx + 1)
201 begin
202 always @(posedge CLK_I or posedge RST_I)
203 if (RST_I)
204 PIO_DATA[ipd_idx] <= #UDLY 0;
205 else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000)
206 PIO_DATA[ipd_idx] <= #UDLY GPIO_DAT_I_switch[ipd_idx];
207 end
208 if (DATA_WIDTH > 8) begin
209 genvar jpd_idx;
210 for (jpd_idx = 8; (jpd_idx < DATA_WIDTH) && (jpd_idx < 16); jpd_idx = jpd_idx + 1)
211 begin
212 always @(posedge CLK_I or posedge RST_I)
213 if (RST_I)
214 PIO_DATA[jpd_idx] <= #UDLY 0;
215 else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001)
216 PIO_DATA[jpd_idx] <= #UDLY GPIO_DAT_I_switch[jpd_idx-8];
217 end
218 end
219 if (DATA_WIDTH > 16) begin
220 genvar kpd_idx;
221 for (kpd_idx = 16; (kpd_idx < DATA_WIDTH) && (kpd_idx < 24); kpd_idx = kpd_idx + 1)
222 begin
223 always @(posedge CLK_I or posedge RST_I)
224 if (RST_I)
225 PIO_DATA[kpd_idx] <= #UDLY 0;
226 else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010)
227 PIO_DATA[kpd_idx] <= #UDLY GPIO_DAT_I_switch[kpd_idx-16];
228 end
229 end
230 if (DATA_WIDTH > 24) begin
231 genvar lpd_idx;
232 for (lpd_idx = 24; (lpd_idx < DATA_WIDTH) && (lpd_idx < 32); lpd_idx = lpd_idx + 1)
233 begin
234 always @(posedge CLK_I or posedge RST_I)
235 if (RST_I)
236 PIO_DATA[lpd_idx] <= #UDLY 0;
237 else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011)
238 PIO_DATA[lpd_idx] <= #UDLY GPIO_DAT_I_switch[lpd_idx-24];
239 end
240 end
241 end // if (GPIO_WB_DAT_WIDTH == 8)
243 else if (GPIO_WB_DAT_WIDTH == 32) begin
244 genvar ipd_idx;
245 for (ipd_idx = 0; (ipd_idx < DATA_WIDTH) && (ipd_idx < 8); ipd_idx = ipd_idx + 1)
246 begin
247 always @(posedge CLK_I or posedge RST_I)
248 if (RST_I)
249 PIO_DATA[ipd_idx] <= #UDLY 0;
250 else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[0])
251 PIO_DATA[ipd_idx] <= #UDLY GPIO_DAT_I_switch[ipd_idx];
252 end
253 if (DATA_WIDTH > 8) begin
254 genvar jpd_idx;
255 for (jpd_idx = 8; (jpd_idx < DATA_WIDTH) && (jpd_idx < 16); jpd_idx = jpd_idx + 1)
256 begin
257 always @(posedge CLK_I or posedge RST_I)
258 if (RST_I)
259 PIO_DATA[jpd_idx] <= #UDLY 0;
260 else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[1])
261 PIO_DATA[jpd_idx] <= #UDLY GPIO_DAT_I_switch[jpd_idx];
262 end
263 end
264 if (DATA_WIDTH > 16) begin
265 genvar kpd_idx;
266 for (kpd_idx = 16; (kpd_idx < DATA_WIDTH) && (kpd_idx < 24); kpd_idx = kpd_idx + 1)
267 begin
268 always @(posedge CLK_I or posedge RST_I)
269 if (RST_I)
270 PIO_DATA[kpd_idx] <= #UDLY 0;
271 else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[2])
272 PIO_DATA[kpd_idx] <= #UDLY GPIO_DAT_I_switch[kpd_idx];
273 end
274 end
275 if (DATA_WIDTH > 24) begin
276 genvar lpd_idx;
277 for (lpd_idx = 24; (lpd_idx < DATA_WIDTH) && (lpd_idx < 32); lpd_idx = lpd_idx + 1)
278 begin
279 always @(posedge CLK_I or posedge RST_I)
280 if (RST_I)
281 PIO_DATA[lpd_idx] <= #UDLY 0;
282 else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[3])
283 PIO_DATA[lpd_idx] <= #UDLY GPIO_DAT_I_switch[lpd_idx];
284 end
285 end
286 end // if (GPIO_WB_DAT_WIDTH == 32)
288 assign PIO_OUT = PIO_DATA;
289 end
290 endgenerate
292 generate
293 if (BOTH_INPUT_AND_OUTPUT == 1) begin
294 if (GPIO_WB_DAT_WIDTH == 8) begin
295 genvar iopd_idx;
296 for (iopd_idx = 0; (iopd_idx < OUTPUT_WIDTH) && (iopd_idx < 8); iopd_idx = iopd_idx + 1)
297 begin
298 always @(posedge CLK_I or posedge RST_I)
299 if (RST_I)
300 begin
301 PIO_DATAI[iopd_idx] <= #UDLY 0;
302 PIO_DATAO[iopd_idx] <= #UDLY 0;
303 end
304 else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000)
305 PIO_DATAI[iopd_idx] <= #UDLY PIO_BOTH_IN[iopd_idx];
306 else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000)
307 PIO_DATAO[iopd_idx] <= #UDLY GPIO_DAT_I_switch[iopd_idx];
308 end
309 if (OUTPUT_WIDTH > 8) begin
310 genvar jopd_idx;
311 for (jopd_idx = 8; (jopd_idx < OUTPUT_WIDTH) && (jopd_idx < 16); jopd_idx = jopd_idx + 1)
312 begin
313 always @(posedge CLK_I or posedge RST_I)
314 if (RST_I)
315 begin
316 PIO_DATAI[jopd_idx] <= #UDLY 0;
317 PIO_DATAO[jopd_idx] <= #UDLY 0;
318 end
319 else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001)
320 PIO_DATAI[jopd_idx] <= #UDLY PIO_BOTH_IN[jopd_idx];
321 else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001)
322 PIO_DATAO[jopd_idx] <= #UDLY GPIO_DAT_I_switch[jopd_idx-8];
323 end
324 end
325 if (OUTPUT_WIDTH > 16) begin
326 genvar kopd_idx;
327 for (kopd_idx = 16; (kopd_idx < OUTPUT_WIDTH) && (kopd_idx < 24); kopd_idx = kopd_idx + 1)
328 begin
329 always @(posedge CLK_I or posedge RST_I)
330 if (RST_I)
331 begin
332 PIO_DATAI[kopd_idx] <= #UDLY 0;
333 PIO_DATAO[kopd_idx] <= #UDLY 0;
334 end
335 else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010)
336 PIO_DATAI[kopd_idx] <= #UDLY PIO_BOTH_IN[kopd_idx];
337 else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010)
338 PIO_DATAO[kopd_idx] <= #UDLY GPIO_DAT_I_switch[kopd_idx-16];
339 end
340 end
341 if (OUTPUT_WIDTH > 24) begin
342 genvar lopd_idx;
343 for (lopd_idx = 24; (lopd_idx < OUTPUT_WIDTH) && (lopd_idx < 32); lopd_idx = lopd_idx + 1)
344 begin
345 always @(posedge CLK_I or posedge RST_I)
346 if (RST_I)
347 begin
348 PIO_DATAI[lopd_idx] <= #UDLY 0;
349 PIO_DATAO[lopd_idx] <= #UDLY 0;
350 end
351 else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011)
352 PIO_DATAI[lopd_idx] <= #UDLY PIO_BOTH_IN[lopd_idx];
353 else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011)
354 PIO_DATAO[lopd_idx] <= #UDLY GPIO_DAT_I_switch[lopd_idx-24];
355 end
356 end
357 end // if (GPIO_WB_DAT_WIDTH == 8)
359 else if (GPIO_WB_DAT_WIDTH == 32) begin
360 genvar iopd_idx;
361 for (iopd_idx = 0; (iopd_idx < OUTPUT_WIDTH) && (iopd_idx < 8); iopd_idx = iopd_idx + 1)
362 begin
363 always @(posedge CLK_I or posedge RST_I)
364 if (RST_I)
365 begin
366 PIO_DATAI[iopd_idx] <= #UDLY 0;
367 PIO_DATAO[iopd_idx] <= #UDLY 0;
368 end
369 else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[0])
370 PIO_DATAI[iopd_idx] <= #UDLY PIO_BOTH_IN[iopd_idx];
371 else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[0])
372 PIO_DATAO[iopd_idx] <= #UDLY GPIO_DAT_I_switch[iopd_idx];
373 end
374 if (OUTPUT_WIDTH > 8) begin
375 genvar jopd_idx;
376 for (jopd_idx = 8; (jopd_idx < OUTPUT_WIDTH) && (jopd_idx < 16); jopd_idx = jopd_idx + 1)
377 begin
378 always @(posedge CLK_I or posedge RST_I)
379 if (RST_I)
380 begin
381 PIO_DATAI[jopd_idx] <= #UDLY 0;
382 PIO_DATAO[jopd_idx] <= #UDLY 0;
383 end
384 else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[1])
385 PIO_DATAI[jopd_idx] <= #UDLY PIO_BOTH_IN[jopd_idx];
386 else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[1])
387 PIO_DATAO[jopd_idx] <= #UDLY GPIO_DAT_I_switch[jopd_idx];
388 end
389 end
390 if (OUTPUT_WIDTH > 16) begin
391 genvar kopd_idx;
392 for (kopd_idx = 16; (kopd_idx < OUTPUT_WIDTH) && (kopd_idx < 24); kopd_idx = kopd_idx + 1)
393 begin
394 always @(posedge CLK_I or posedge RST_I)
395 if (RST_I)
396 begin
397 PIO_DATAI[kopd_idx] <= #UDLY 0;
398 PIO_DATAO[kopd_idx] <= #UDLY 0;
399 end
400 else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[2])
401 PIO_DATAI[kopd_idx] <= #UDLY PIO_BOTH_IN[kopd_idx];
402 else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[2])
403 PIO_DATAO[kopd_idx] <= #UDLY GPIO_DAT_I_switch[kopd_idx];
404 end
405 end
406 if (OUTPUT_WIDTH > 24) begin
407 genvar lopd_idx;
408 for (lopd_idx = 24; (lopd_idx < OUTPUT_WIDTH) && (lopd_idx < 32); lopd_idx = lopd_idx + 1)
409 begin
410 always @(posedge CLK_I or posedge RST_I)
411 if (RST_I)
412 begin
413 PIO_DATAI[lopd_idx] <= #UDLY 0;
414 PIO_DATAO[lopd_idx] <= #UDLY 0;
415 end
416 else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[3])
417 PIO_DATAI[lopd_idx] <= #UDLY PIO_BOTH_IN[lopd_idx];
418 else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[3])
419 PIO_DATAO[lopd_idx] <= #UDLY GPIO_DAT_I_switch[lopd_idx];
420 end
421 end
422 end // if (GPIO_WB_DAT_WIDTH == 32)
424 assign PIO_BOTH_OUT = PIO_DATAO[OUTPUT_WIDTH-1:0];
425 end
426 endgenerate
428 assign PIO_DATA_RE_EN = GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b00);
430 assign PIO_TRI_RE_EN = GPIO_STB_I && GPIO_ACK_O && !GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b01);
432 assign IRQ_MASK_RE_EN = GPIO_STB_I && GPIO_ACK_O && !GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b10);
434 assign PIO_DATA_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b00);
435 generate
436 if (GPIO_WB_DAT_WIDTH == 8) begin
437 assign PIO_DATA_WR_EN_0 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000;
438 assign PIO_DATA_WR_EN_1 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001;
439 assign PIO_DATA_WR_EN_2 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010;
440 assign PIO_DATA_WR_EN_3 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011;
441 end
442 endgenerate
444 assign PIO_TRI_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (GPIO_ADR_I[3:2] == 4'b01);
445 generate
446 if (GPIO_WB_DAT_WIDTH == 8) begin
447 assign PIO_TRI_WR_EN_0 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0100;
448 assign PIO_TRI_WR_EN_1 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0101;
449 assign PIO_TRI_WR_EN_2 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0110;
450 assign PIO_TRI_WR_EN_3 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0111;
451 end
452 endgenerate
454 assign IRQ_MASK_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b10);
455 generate
456 if (GPIO_WB_DAT_WIDTH == 8) begin
457 assign IRQ_MASK_WR_EN_0 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1000;
458 assign IRQ_MASK_WR_EN_1 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1001;
459 assign IRQ_MASK_WR_EN_2 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1010;
460 assign IRQ_MASK_WR_EN_3 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1011;
461 end
462 endgenerate
464 assign EDGE_CAP_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b11);
465 generate
466 if (GPIO_WB_DAT_WIDTH == 8) begin
467 assign EDGE_CAP_WR_EN_0 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1100;
468 assign EDGE_CAP_WR_EN_1 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1101;
469 assign EDGE_CAP_WR_EN_2 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1110;
470 assign EDGE_CAP_WR_EN_3 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1111;
471 end
472 endgenerate
474 generate
476 if (GPIO_WB_DAT_WIDTH == 8) begin
478 genvar iti;
479 for (iti = 0; (iti < DATA_WIDTH) && (iti < 8); iti = iti + 1)
480 begin : itio_inst
481 TRI_PIO
482 #(.DATA_WIDTH(1),
483 .IRQ_MODE(IRQ_MODE),
484 .LEVEL(LEVEL),
485 .EDGE(EDGE),
486 .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
487 .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
488 .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
489 TP
490 (.CLK_I(CLK_I),
491 .RST_I(RST_I),
492 .DAT_I(GPIO_DAT_I_switch[iti]),
493 .DAT_O(tpio_out[iti]),
494 .PIO_IO(PIO_IO[iti]),
495 .IRQ_O(IRQ_TRI_TEMP[iti]),
496 .PIO_TRI_WR_EN(PIO_TRI_WR_EN_0),
497 .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
498 .PIO_DATA_WR_EN(PIO_DATA_WR_EN_0),
499 .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
500 .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_0),
501 .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
502 .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_0));
503 end
504 if (DATA_WIDTH > 8) begin
505 genvar jti;
506 for (jti = 8; (jti < DATA_WIDTH) && (jti < 16); jti = jti + 1)
507 begin : jtio_inst
508 TRI_PIO
509 #(.DATA_WIDTH(1),
510 .IRQ_MODE(IRQ_MODE),
511 .LEVEL(LEVEL),
512 .EDGE(EDGE),
513 .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
514 .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
515 .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
516 TP
517 (.CLK_I(CLK_I),
518 .RST_I(RST_I),
519 .DAT_I(GPIO_DAT_I_switch[jti-8]),
520 .DAT_O(tpio_out[jti]),
521 .PIO_IO(PIO_IO[jti]),
522 .IRQ_O(IRQ_TRI_TEMP[jti]),
523 .PIO_TRI_WR_EN(PIO_TRI_WR_EN_1),
524 .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
525 .PIO_DATA_WR_EN(PIO_DATA_WR_EN_1),
526 .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
527 .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_1),
528 .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
529 .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_1));
530 end
531 end
532 if (DATA_WIDTH > 16) begin
533 genvar kti;
534 for (kti = 16; (kti < DATA_WIDTH) && (kti < 24); kti = kti + 1)
535 begin : ktio_inst
536 TRI_PIO
537 #(.DATA_WIDTH(1),
538 .IRQ_MODE(IRQ_MODE),
539 .LEVEL(LEVEL),
540 .EDGE(EDGE),
541 .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
542 .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
543 .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
544 TP
545 (.CLK_I(CLK_I),
546 .RST_I(RST_I),
547 .DAT_I(GPIO_DAT_I_switch[kti-16]),
548 .DAT_O(tpio_out[kti]),
549 .PIO_IO(PIO_IO[kti]),
550 .IRQ_O(IRQ_TRI_TEMP[kti]),
551 .PIO_TRI_WR_EN(PIO_TRI_WR_EN_2),
552 .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
553 .PIO_DATA_WR_EN(PIO_DATA_WR_EN_2),
554 .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
555 .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_2),
556 .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
557 .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_2));
558 end
559 end
560 if (DATA_WIDTH > 24) begin
561 genvar lti;
562 for (lti = 24; (lti < DATA_WIDTH) && (lti < 32); lti = lti + 1)
563 begin : ltio_inst
564 TRI_PIO
565 #(.DATA_WIDTH(1),
566 .IRQ_MODE(IRQ_MODE),
567 .LEVEL(LEVEL),
568 .EDGE(EDGE),
569 .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
570 .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
571 .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
572 TP
573 (.CLK_I(CLK_I),
574 .RST_I(RST_I),
575 .DAT_I(GPIO_DAT_I_switch[lti-24]),
576 .DAT_O(tpio_out[lti]),
577 .PIO_IO(PIO_IO[lti]),
578 .IRQ_O(IRQ_TRI_TEMP[lti]),
579 .PIO_TRI_WR_EN(PIO_TRI_WR_EN_3),
580 .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
581 .PIO_DATA_WR_EN(PIO_DATA_WR_EN_3),
582 .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
583 .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_3),
584 .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
585 .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_3));
586 end
587 end
589 end // if (GPIO_WB_DAT_WIDTH == 8)
591 else if (GPIO_WB_DAT_WIDTH == 32) begin
593 genvar iti;
594 for (iti = 0; (iti < DATA_WIDTH) && (iti < 8); iti = iti + 1)
595 begin : itio_inst
596 TRI_PIO
597 #(.DATA_WIDTH(1),
598 .IRQ_MODE(IRQ_MODE),
599 .LEVEL(LEVEL),
600 .EDGE(EDGE),
601 .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
602 .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
603 .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
604 TP
605 (.CLK_I(CLK_I),
606 .RST_I(RST_I),
607 .DAT_I(GPIO_DAT_I_switch[iti]),
608 .DAT_O(tpio_out[iti]),
609 .PIO_IO(PIO_IO[iti]),
610 .IRQ_O(IRQ_TRI_TEMP[iti]),
611 .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[0]),
612 .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
613 .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[0]),
614 .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
615 .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[0]),
616 .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
617 .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[0]));
618 end
619 if (DATA_WIDTH > 8) begin
620 genvar jti;
621 for (jti = 8; (jti < DATA_WIDTH) && (jti < 16); jti = jti + 1)
622 begin : jtio_inst
623 TRI_PIO
624 #(.DATA_WIDTH(1),
625 .IRQ_MODE(IRQ_MODE),
626 .LEVEL(LEVEL),
627 .EDGE(EDGE),
628 .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
629 .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
630 .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
631 TP
632 (.CLK_I(CLK_I),
633 .RST_I(RST_I),
634 .DAT_I(GPIO_DAT_I_switch[jti]),
635 .DAT_O(tpio_out[jti]),
636 .PIO_IO(PIO_IO[jti]),
637 .IRQ_O(IRQ_TRI_TEMP[jti]),
638 .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[1]),
639 .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
640 .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[1]),
641 .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
642 .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[1]),
643 .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
644 .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[1]));
645 end
646 end
647 if (DATA_WIDTH > 16) begin
648 genvar kti;
649 for (kti = 16; (kti < DATA_WIDTH) && (kti < 24); kti = kti + 1)
650 begin : ktio_inst
651 TRI_PIO
652 #(.DATA_WIDTH(1),
653 .IRQ_MODE(IRQ_MODE),
654 .LEVEL(LEVEL),
655 .EDGE(EDGE),
656 .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
657 .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
658 .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
659 TP
660 (.CLK_I(CLK_I),
661 .RST_I(RST_I),
662 .DAT_I(GPIO_DAT_I_switch[kti]),
663 .DAT_O(tpio_out[kti]),
664 .PIO_IO(PIO_IO[kti]),
665 .IRQ_O(IRQ_TRI_TEMP[kti]),
666 .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[2]),
667 .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
668 .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[2]),
669 .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
670 .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[2]),
671 .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
672 .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[2]));
673 end
674 end
675 if (DATA_WIDTH > 24) begin
676 genvar lti;
677 for (lti = 24; (lti < DATA_WIDTH) && (lti < 32); lti = lti + 1)
678 begin : ltio_inst
679 TRI_PIO
680 #(.DATA_WIDTH(1),
681 .IRQ_MODE(IRQ_MODE),
682 .LEVEL(LEVEL),
683 .EDGE(EDGE),
684 .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
685 .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
686 .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
687 TP
688 (.CLK_I(CLK_I),
689 .RST_I(RST_I),
690 .DAT_I(GPIO_DAT_I_switch[lti]),
691 .DAT_O(tpio_out[lti]),
692 .PIO_IO(PIO_IO[lti]),
693 .IRQ_O(IRQ_TRI_TEMP[lti]),
694 .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[3]),
695 .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
696 .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[3]),
697 .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
698 .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[3]),
699 .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
700 .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[3]));
701 end
702 end
704 end // if (GPIO_WB_DAT_WIDTH == 32)
706 endgenerate
709 wire read_addr_0, read_addr_4, read_addr_8, read_addr_C;
710 assign read_addr_0 = (ADR_0 & GPIO_STB_I & ~GPIO_WE_I) ;
711 assign read_addr_4 = (ADR_4 & GPIO_STB_I & ~GPIO_WE_I) ;
712 assign read_addr_8 = (IRQ_MODE == 1 && (ADR_8 & GPIO_STB_I & ~GPIO_WE_I));
713 assign read_addr_C = (IRQ_MODE == 1 && (ADR_C & GPIO_STB_I & ~GPIO_WE_I));
715 wire read_byte_0, read_byte_1, read_byte_2, read_byte_3;
716 wire read_byte_4, read_byte_5, read_byte_6, read_byte_7;
717 wire read_byte_8, read_byte_9, read_byte_A, read_byte_B;
718 wire read_byte_C, read_byte_D, read_byte_E, read_byte_F;
719 assign read_byte_0 = ((GPIO_ADR_I[3:0] == 4'b0000) & GPIO_STB_I & ~GPIO_WE_I) ;
720 assign read_byte_1 = ((GPIO_ADR_I[3:0] == 4'b0001) & GPIO_STB_I & ~GPIO_WE_I) ;
721 assign read_byte_2 = ((GPIO_ADR_I[3:0] == 4'b0010) & GPIO_STB_I & ~GPIO_WE_I) ;
722 assign read_byte_3 = ((GPIO_ADR_I[3:0] == 4'b0011) & GPIO_STB_I & ~GPIO_WE_I) ;
723 assign read_byte_4 = ((GPIO_ADR_I[3:0] == 4'b0100) & GPIO_STB_I & ~GPIO_WE_I) ;
724 assign read_byte_5 = ((GPIO_ADR_I[3:0] == 4'b0101) & GPIO_STB_I & ~GPIO_WE_I) ;
725 assign read_byte_6 = ((GPIO_ADR_I[3:0] == 4'b0110) & GPIO_STB_I & ~GPIO_WE_I) ;
726 assign read_byte_7 = ((GPIO_ADR_I[3:0] == 4'b0111) & GPIO_STB_I & ~GPIO_WE_I) ;
727 assign read_byte_8 = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1000) & GPIO_STB_I & ~GPIO_WE_I));
728 assign read_byte_9 = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1001) & GPIO_STB_I & ~GPIO_WE_I));
729 assign read_byte_A = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1010) & GPIO_STB_I & ~GPIO_WE_I));
730 assign read_byte_B = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1011) & GPIO_STB_I & ~GPIO_WE_I));
731 assign read_byte_C = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1100) & GPIO_STB_I & ~GPIO_WE_I));
732 assign read_byte_D = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1101) & GPIO_STB_I & ~GPIO_WE_I));
733 assign read_byte_E = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1110) & GPIO_STB_I & ~GPIO_WE_I));
734 assign read_byte_F = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1111) & GPIO_STB_I & ~GPIO_WE_I));
736 generate
738 if (GPIO_WB_DAT_WIDTH == 8) begin
740 if (INPUT_PORTS_ONLY == 1) begin
741 if (DATA_WIDTH > 24)
742 assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[ 7: 0] :
743 read_byte_1 ? PIO_DATA[15: 8] :
744 read_byte_2 ? PIO_DATA[23:16] :
745 read_byte_3 ? PIO_DATA[DATA_WIDTH-1:24] :
746 read_byte_8 ? IRQ_MASK[ 7: 0] :
747 read_byte_9 ? IRQ_MASK[15: 8] :
748 read_byte_A ? IRQ_MASK[23:16] :
749 read_byte_B ? IRQ_MASK[DATA_WIDTH-1:24] :
750 read_byte_C ? EDGE_CAPTURE[ 7: 0] :
751 read_byte_D ? EDGE_CAPTURE[15: 8] :
752 read_byte_E ? EDGE_CAPTURE[23:16] :
753 read_byte_F ? EDGE_CAPTURE[DATA_WIDTH-1:24] :
754 0;
755 else if (DATA_WIDTH > 16)
756 assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[ 7: 0] :
757 read_byte_1 ? PIO_DATA[15: 8] :
758 read_byte_2 ? PIO_DATA[DATA_WIDTH-1:16] :
759 read_byte_3 ? 8'h00 :
760 read_byte_8 ? IRQ_MASK[ 7: 0] :
761 read_byte_9 ? IRQ_MASK[15: 8] :
762 read_byte_A ? IRQ_MASK[DATA_WIDTH-1:16] :
763 read_byte_B ? 8'h00 :
764 read_byte_C ? EDGE_CAPTURE[ 7: 0] :
765 read_byte_D ? EDGE_CAPTURE[15: 8] :
766 read_byte_E ? EDGE_CAPTURE[DATA_WIDTH-1:16] :
767 read_byte_F ? 8'h00 :
768 0;
769 else if (DATA_WIDTH > 8)
770 assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[ 7: 0] :
771 read_byte_1 ? PIO_DATA[DATA_WIDTH-1: 8] :
772 read_byte_2 ? 8'h00 :
773 read_byte_3 ? 8'h00 :
774 read_byte_8 ? IRQ_MASK[ 7: 0] :
775 read_byte_9 ? IRQ_MASK[DATA_WIDTH-1: 8] :
776 read_byte_A ? 8'h00 :
777 read_byte_B ? 8'h00 :
778 read_byte_C ? EDGE_CAPTURE[ 7: 0] :
779 read_byte_D ? EDGE_CAPTURE[DATA_WIDTH-1: 8] :
780 read_byte_E ? 8'h00 :
781 read_byte_F ? 8'h00 :
782 0;
783 else
784 assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[DATA_WIDTH-1: 0] :
785 read_byte_1 ? 8'h00 :
786 read_byte_2 ? 8'h00 :
787 read_byte_3 ? 8'h00 :
788 read_byte_8 ? IRQ_MASK[DATA_WIDTH-1: 0] :
789 read_byte_9 ? 8'h00 :
790 read_byte_A ? 8'h00 :
791 read_byte_B ? 8'h00 :
792 read_byte_C ? EDGE_CAPTURE[DATA_WIDTH-1: 0] :
793 read_byte_D ? 8'h00 :
794 read_byte_E ? 8'h00 :
795 read_byte_F ? 8'h00 :
796 0;
797 end
798 else if (BOTH_INPUT_AND_OUTPUT == 1) begin
799 if (INPUT_WIDTH > 24)
800 assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[ 7: 0] :
801 read_byte_1 ? PIO_DATAI[15: 8] :
802 read_byte_2 ? PIO_DATAI[23:16] :
803 read_byte_3 ? PIO_DATAI[INPUT_WIDTH-1:24] :
804 read_byte_8 ? IRQ_MASK_BOTH[ 7: 0] :
805 read_byte_9 ? IRQ_MASK_BOTH[15: 8] :
806 read_byte_A ? IRQ_MASK_BOTH[23:16] :
807 read_byte_B ? IRQ_MASK_BOTH[INPUT_WIDTH-1:24] :
808 read_byte_C ? EDGE_CAPTURE_BOTH[ 7: 0] :
809 read_byte_D ? EDGE_CAPTURE_BOTH[15: 8] :
810 read_byte_E ? EDGE_CAPTURE_BOTH[23:16] :
811 read_byte_F ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1:24] :
812 0;
813 else if (INPUT_WIDTH > 16)
814 assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[ 7: 0] :
815 read_byte_1 ? PIO_DATAI[15: 8] :
816 read_byte_2 ? PIO_DATAI[INPUT_WIDTH-1:16] :
817 read_byte_3 ? 8'h00 :
818 read_byte_8 ? IRQ_MASK_BOTH[ 7: 0] :
819 read_byte_9 ? IRQ_MASK_BOTH[15: 8] :
820 read_byte_A ? IRQ_MASK_BOTH[INPUT_WIDTH-1:16] :
821 read_byte_B ? 8'h00 :
822 read_byte_C ? EDGE_CAPTURE_BOTH[ 7: 0] :
823 read_byte_D ? EDGE_CAPTURE_BOTH[15: 8] :
824 read_byte_E ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1:16] :
825 read_byte_F ? 8'h00 :
826 0;
827 else if (INPUT_WIDTH > 8)
828 assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[ 7: 0] :
829 read_byte_1 ? PIO_DATAI[INPUT_WIDTH-1: 8] :
830 read_byte_2 ? 8'h00 :
831 read_byte_3 ? 8'h00 :
832 read_byte_8 ? IRQ_MASK_BOTH[ 7: 0] :
833 read_byte_9 ? IRQ_MASK_BOTH[INPUT_WIDTH-1: 8] :
834 read_byte_A ? 8'h00 :
835 read_byte_B ? 8'h00 :
836 read_byte_C ? EDGE_CAPTURE_BOTH[ 7: 0] :
837 read_byte_D ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1: 8] :
838 read_byte_E ? 8'h00 :
839 read_byte_F ? 8'h00 :
840 0;
841 else
842 assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[INPUT_WIDTH-1: 0] :
843 read_byte_1 ? 8'h00 :
844 read_byte_2 ? 8'h00 :
845 read_byte_3 ? 8'h00 :
846 read_byte_8 ? IRQ_MASK_BOTH[INPUT_WIDTH-1: 0] :
847 read_byte_9 ? 8'h00 :
848 read_byte_A ? 8'h00 :
849 read_byte_B ? 8'h00 :
850 read_byte_C ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1: 0] :
851 read_byte_D ? 8'h00 :
852 read_byte_E ? 8'h00 :
853 read_byte_F ? 8'h00 :
854 0;
855 end
856 else if (TRISTATE_PORTS == 1) begin
857 if (DATA_WIDTH > 24)
858 assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[ 7: 0] :
859 read_byte_1 ? tpio_out[15: 8] :
860 read_byte_2 ? tpio_out[23:16] :
861 read_byte_3 ? tpio_out[DATA_WIDTH-1:24] :
862 read_byte_4 ? tpio_out[ 7: 0] :
863 read_byte_5 ? tpio_out[15: 8] :
864 read_byte_6 ? tpio_out[23:16] :
865 read_byte_7 ? tpio_out[DATA_WIDTH-1:24] :
866 read_byte_8 ? tpio_out[ 7: 0] :
867 read_byte_9 ? tpio_out[15: 8] :
868 read_byte_A ? tpio_out[23:16] :
869 read_byte_B ? tpio_out[DATA_WIDTH-1:24] :
870 read_byte_C ? IRQ_TRI_TEMP[ 7: 0] :
871 read_byte_D ? IRQ_TRI_TEMP[15: 8] :
872 read_byte_E ? IRQ_TRI_TEMP[23:16] :
873 read_byte_F ? IRQ_TRI_TEMP[DATA_WIDTH-1:24] :
874 0;
875 else if (DATA_WIDTH > 16)
876 assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[ 7: 0] :
877 read_byte_1 ? tpio_out[15: 8] :
878 read_byte_2 ? tpio_out[DATA_WIDTH-1:16] :
879 read_byte_3 ? 8'h00 :
880 read_byte_4 ? tpio_out[ 7: 0] :
881 read_byte_5 ? tpio_out[15: 8] :
882 read_byte_6 ? tpio_out[DATA_WIDTH-1:16] :
883 read_byte_7 ? 8'h00 :
884 read_byte_8 ? tpio_out[ 7: 0] :
885 read_byte_9 ? tpio_out[15: 8] :
886 read_byte_A ? tpio_out[DATA_WIDTH-1:16] :
887 read_byte_B ? 8'h00 :
888 read_byte_C ? IRQ_TRI_TEMP[ 7: 0] :
889 read_byte_D ? IRQ_TRI_TEMP[15: 8] :
890 read_byte_E ? IRQ_TRI_TEMP[DATA_WIDTH-1:16] :
891 read_byte_F ? 8'h00 :
892 0;
893 else if (DATA_WIDTH > 8)
894 assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[ 7: 0] :
895 read_byte_1 ? tpio_out[DATA_WIDTH-1: 8] :
896 read_byte_2 ? 8'h00 :
897 read_byte_3 ? 8'h00 :
898 read_byte_4 ? tpio_out[ 7: 0] :
899 read_byte_5 ? tpio_out[DATA_WIDTH-1: 8] :
900 read_byte_6 ? 8'h00 :
901 read_byte_7 ? 8'h00 :
902 read_byte_8 ? tpio_out[ 7: 0] :
903 read_byte_9 ? tpio_out[DATA_WIDTH-1: 8] :
904 read_byte_A ? 8'h00 :
905 read_byte_B ? 8'h00 :
906 read_byte_C ? IRQ_TRI_TEMP[ 7: 0] :
907 read_byte_D ? IRQ_TRI_TEMP[DATA_WIDTH-1: 8] :
908 read_byte_E ? 8'h00 :
909 read_byte_F ? 8'h00 :
910 0;
911 else
912 assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[DATA_WIDTH-1: 0] :
913 read_byte_1 ? 8'h00 :
914 read_byte_2 ? 8'h00 :
915 read_byte_3 ? 8'h00 :
916 read_byte_4 ? tpio_out[DATA_WIDTH-1: 0] :
917 read_byte_5 ? 8'h00 :
918 read_byte_6 ? 8'h00 :
919 read_byte_7 ? 8'h00 :
920 read_byte_8 ? tpio_out[DATA_WIDTH-1: 0] :
921 read_byte_9 ? 8'h00 :
922 read_byte_A ? 8'h00 :
923 read_byte_B ? 8'h00 :
924 read_byte_C ? IRQ_TRI_TEMP[DATA_WIDTH-1: 0] :
925 read_byte_D ? 8'h00 :
926 read_byte_E ? 8'h00 :
927 read_byte_F ? 8'h00 :
928 0;
929 end
930 else
931 assign GPIO_DAT_O_switch = 0;
933 end // if (GPIO_WB_DAT_WIDTH == 8)
935 else if (GPIO_WB_DAT_WIDTH == 32) begin
937 if (INPUT_PORTS_ONLY == 1)
938 assign GPIO_DAT_O_switch = read_addr_0 ? PIO_DATA :
939 read_addr_8 ? IRQ_MASK :
940 read_addr_C ? EDGE_CAPTURE :
941 0;
942 else if (BOTH_INPUT_AND_OUTPUT == 1)
943 assign GPIO_DAT_O_switch = read_addr_0 ? PIO_DATAI :
944 read_addr_8 ? IRQ_MASK_BOTH :
945 read_addr_C ? EDGE_CAPTURE_BOTH :
946 0;
947 else if (TRISTATE_PORTS == 1)
948 assign GPIO_DAT_O_switch = read_addr_0 ? tpio_out :
949 read_addr_4 ? tpio_out :
950 read_addr_8 ? tpio_out :
951 read_addr_C ? IRQ_TRI_TEMP :
952 0;
953 else
954 assign GPIO_DAT_O_switch = 0;
956 end // if (GPIO_WB_DAT_WIDTH == 32)
958 endgenerate
962 //-----------------------------------------------------------------------------
963 //-------------------------------IRQ Generation--------------------------------
964 //-----------------------------------------------------------------------------
965 generate
967 if (IRQ_MODE == 1) begin
969 if (GPIO_WB_DAT_WIDTH == 8) begin
971 genvar im_idx;
972 for (im_idx = 0; (im_idx < DATA_WIDTH) && (im_idx < 8); im_idx = im_idx + 1)
973 begin
974 always @(posedge CLK_I or posedge RST_I)
975 if (RST_I)
976 IRQ_MASK[im_idx] <= #UDLY 0;
977 else if (IRQ_MASK_WR_EN_0)
978 IRQ_MASK[im_idx] <= #UDLY GPIO_DAT_I_switch[im_idx];
979 end
980 if (DATA_WIDTH > 8) begin
981 genvar jm_idx;
982 for (jm_idx = 8; (jm_idx < DATA_WIDTH) && (jm_idx < 16); jm_idx = jm_idx + 1)
983 begin
984 always @(posedge CLK_I or posedge RST_I)
985 if (RST_I)
986 IRQ_MASK[jm_idx] <= #UDLY 0;
987 else if (IRQ_MASK_WR_EN_1)
988 IRQ_MASK[jm_idx] <= #UDLY GPIO_DAT_I_switch[jm_idx-8];
989 end
990 end
991 if (DATA_WIDTH > 16) begin
992 genvar km_idx;
993 for (km_idx = 16; (km_idx < DATA_WIDTH) && (km_idx < 24); km_idx = km_idx + 1)
994 begin
995 always @(posedge CLK_I or posedge RST_I)
996 if (RST_I)
997 IRQ_MASK[km_idx] <= #UDLY 0;
998 else if (IRQ_MASK_WR_EN_2)
999 IRQ_MASK[km_idx] <= #UDLY GPIO_DAT_I_switch[km_idx-16];
1000 end
1001 end
1002 if (DATA_WIDTH > 24) begin
1003 genvar lm_idx;
1004 for (lm_idx = 24; (lm_idx < DATA_WIDTH) && (lm_idx < 32); lm_idx = lm_idx + 1)
1005 begin
1006 always @(posedge CLK_I or posedge RST_I)
1007 if (RST_I)
1008 IRQ_MASK[lm_idx] <= #UDLY 0;
1009 else if (IRQ_MASK_WR_EN_3)
1010 IRQ_MASK[lm_idx] <= #UDLY GPIO_DAT_I_switch[lm_idx-24];
1011 end
1012 end
1014 genvar imb_idx;
1015 for (imb_idx = 0; (imb_idx < INPUT_WIDTH) && (imb_idx < 8); imb_idx = imb_idx + 1)
1016 begin
1017 always @(posedge CLK_I or posedge RST_I)
1018 if (RST_I)
1019 IRQ_MASK_BOTH[imb_idx] <= #UDLY 0;
1020 else if (IRQ_MASK_WR_EN_0)
1021 IRQ_MASK_BOTH[imb_idx] <= #UDLY GPIO_DAT_I_switch[imb_idx];
1022 end
1023 if (INPUT_WIDTH > 8) begin
1024 genvar jmb_idx;
1025 for (jmb_idx = 8; (jmb_idx < INPUT_WIDTH) && (jmb_idx < 16); jmb_idx = jmb_idx + 1)
1026 begin
1027 always @(posedge CLK_I or posedge RST_I)
1028 if (RST_I)
1029 IRQ_MASK_BOTH[jmb_idx] <= #UDLY 0;
1030 else if (IRQ_MASK_WR_EN_1)
1031 IRQ_MASK_BOTH[jmb_idx] <= #UDLY GPIO_DAT_I_switch[jmb_idx-8];
1032 end
1033 end
1034 if (INPUT_WIDTH > 16) begin
1035 genvar kmb_idx;
1036 for (kmb_idx = 16; (kmb_idx < INPUT_WIDTH) && (kmb_idx < 24); kmb_idx = kmb_idx + 1)
1037 begin
1038 always @(posedge CLK_I or posedge RST_I)
1039 if (RST_I)
1040 IRQ_MASK_BOTH[kmb_idx] <= #UDLY 0;
1041 else if (IRQ_MASK_WR_EN_2)
1042 IRQ_MASK_BOTH[kmb_idx] <= #UDLY GPIO_DAT_I_switch[kmb_idx-16];
1043 end
1044 end
1045 if (INPUT_WIDTH > 24) begin
1046 genvar lmb_idx;
1047 for (lmb_idx = 24; (lmb_idx < INPUT_WIDTH) && (lmb_idx < 32); lmb_idx = lmb_idx + 1)
1048 begin
1049 always @(posedge CLK_I or posedge RST_I)
1050 if (RST_I)
1051 IRQ_MASK_BOTH[lmb_idx] <= #UDLY 0;
1052 else if (IRQ_MASK_WR_EN_3)
1053 IRQ_MASK_BOTH[lmb_idx] <= #UDLY GPIO_DAT_I_switch[lmb_idx-24];
1054 end
1055 end
1057 end // if (GPIO_WB_DAT_WIDTH == 8)
1058 else if (GPIO_WB_DAT_WIDTH == 32) begin
1060 genvar im_idx;
1061 for (im_idx = 0; (im_idx < DATA_WIDTH) && (im_idx < 8); im_idx = im_idx + 1)
1062 begin
1063 always @(posedge CLK_I or posedge RST_I)
1064 if (RST_I)
1065 IRQ_MASK[im_idx] <= #UDLY 0;
1066 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0])
1067 IRQ_MASK[im_idx] <= #UDLY GPIO_DAT_I_switch[im_idx];
1068 end
1069 if (DATA_WIDTH > 8) begin
1070 genvar jm_idx;
1071 for (jm_idx = 8; (jm_idx < DATA_WIDTH) && (jm_idx < 16); jm_idx = jm_idx + 1)
1072 begin
1073 always @(posedge CLK_I or posedge RST_I)
1074 if (RST_I)
1075 IRQ_MASK[jm_idx] <= #UDLY 0;
1076 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1])
1077 IRQ_MASK[jm_idx] <= #UDLY GPIO_DAT_I_switch[jm_idx];
1078 end
1079 end
1080 if (DATA_WIDTH > 16) begin
1081 genvar km_idx;
1082 for (km_idx = 16; (km_idx < DATA_WIDTH) && (km_idx < 24); km_idx = km_idx + 1)
1083 begin
1084 always @(posedge CLK_I or posedge RST_I)
1085 if (RST_I)
1086 IRQ_MASK[km_idx] <= #UDLY 0;
1087 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2])
1088 IRQ_MASK[km_idx] <= #UDLY GPIO_DAT_I_switch[km_idx];
1089 end
1090 end
1091 if (DATA_WIDTH > 24) begin
1092 genvar lm_idx;
1093 for (lm_idx = 24; (lm_idx < DATA_WIDTH) && (lm_idx < 32); lm_idx = lm_idx + 1)
1094 begin
1095 always @(posedge CLK_I or posedge RST_I)
1096 if (RST_I)
1097 IRQ_MASK[lm_idx] <= #UDLY 0;
1098 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3])
1099 IRQ_MASK[lm_idx] <= #UDLY GPIO_DAT_I_switch[lm_idx];
1100 end
1101 end
1103 genvar imb_idx;
1104 for (imb_idx = 0; (imb_idx < INPUT_WIDTH) && (imb_idx < 8); imb_idx = imb_idx + 1)
1105 begin
1106 always @(posedge CLK_I or posedge RST_I)
1107 if (RST_I)
1108 IRQ_MASK_BOTH[imb_idx] <= #UDLY 0;
1109 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0])
1110 IRQ_MASK_BOTH[imb_idx] <= #UDLY GPIO_DAT_I_switch[imb_idx];
1111 end
1112 if (INPUT_WIDTH > 8) begin
1113 genvar jmb_idx;
1114 for (jmb_idx = 8; (jmb_idx < INPUT_WIDTH) && (jmb_idx < 16); jmb_idx = jmb_idx + 1)
1115 begin
1116 always @(posedge CLK_I or posedge RST_I)
1117 if (RST_I)
1118 IRQ_MASK_BOTH[jmb_idx] <= #UDLY 0;
1119 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1])
1120 IRQ_MASK_BOTH[jmb_idx] <= #UDLY GPIO_DAT_I_switch[jmb_idx];
1121 end
1122 end
1123 if (INPUT_WIDTH > 16) begin
1124 genvar kmb_idx;
1125 for (kmb_idx = 16; (kmb_idx < INPUT_WIDTH) && (kmb_idx < 24); kmb_idx = kmb_idx + 1)
1126 begin
1127 always @(posedge CLK_I or posedge RST_I)
1128 if (RST_I)
1129 IRQ_MASK_BOTH[kmb_idx] <= #UDLY 0;
1130 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2])
1131 IRQ_MASK_BOTH[kmb_idx] <= #UDLY GPIO_DAT_I_switch[kmb_idx];
1132 end
1133 end
1134 if (INPUT_WIDTH > 24) begin
1135 genvar lmb_idx;
1136 for (lmb_idx = 24; (lmb_idx < INPUT_WIDTH) && (lmb_idx < 32); lmb_idx = lmb_idx + 1)
1137 begin
1138 always @(posedge CLK_I or posedge RST_I)
1139 if (RST_I)
1140 IRQ_MASK_BOTH[lmb_idx] <= #UDLY 0;
1141 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3])
1142 IRQ_MASK_BOTH[lmb_idx] <= #UDLY GPIO_DAT_I_switch[lmb_idx];
1143 end
1144 end
1146 end // if (GPIO_WB_DAT_WIDTH == 32)
1148 end // if (IRQ_MODE == 1)
1150 endgenerate
1154 generate
1155 //--------------------------------
1156 //--INPUT_PORTS_ONLY MODE IRQ
1157 //--------------------------------
1158 if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (LEVEL == 1)) begin
1159 // level mode IRQ
1161 if (GPIO_WB_DAT_WIDTH == 8) begin
1163 genvar i;
1164 for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1)
1165 begin
1166 always @(posedge CLK_I or posedge RST_I)
1167 if (RST_I)
1168 IRQ_TEMP[i] <= #UDLY 0;
1169 else if (IRQ_MASK_WR_EN_0)
1170 IRQ_TEMP[i] <= #UDLY IRQ_TEMP[i] & GPIO_DAT_I_switch[i];
1171 else
1172 IRQ_TEMP[i] <= #UDLY PIO_IN[i] & IRQ_MASK[i];
1173 end
1174 if (DATA_WIDTH > 8) begin
1175 genvar j;
1176 for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1)
1177 begin
1178 always @(posedge CLK_I or posedge RST_I)
1179 if (RST_I)
1180 IRQ_TEMP[j] <= #UDLY 0;
1181 else if (IRQ_MASK_WR_EN_1)
1182 IRQ_TEMP[j] <= #UDLY IRQ_TEMP[j] & GPIO_DAT_I_switch[j-8];
1183 else
1184 IRQ_TEMP[j] <= #UDLY PIO_IN[j] & IRQ_MASK[j];
1185 end
1186 end
1187 if (DATA_WIDTH > 16) begin
1188 genvar k;
1189 for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1)
1190 begin
1191 always @(posedge CLK_I or posedge RST_I)
1192 if (RST_I)
1193 IRQ_TEMP[k] <= #UDLY 0;
1194 else if (IRQ_MASK_WR_EN_2)
1195 IRQ_TEMP[k] <= #UDLY IRQ_TEMP[k] & GPIO_DAT_I_switch[k-16];
1196 else
1197 IRQ_TEMP[k] <= #UDLY PIO_IN[k] & IRQ_MASK[k];
1198 end
1199 end
1200 if (DATA_WIDTH > 24) begin
1201 genvar l;
1202 for (l = 24; (l < DATA_WIDTH) && (l < 32); l = l + 1)
1203 begin
1204 always @(posedge CLK_I or posedge RST_I)
1205 if (RST_I)
1206 IRQ_TEMP[l] <= #UDLY 0;
1207 else if (IRQ_MASK_WR_EN_3)
1208 IRQ_TEMP[l] <= #UDLY IRQ_TEMP[l] & GPIO_DAT_I_switch[l-24];
1209 else
1210 IRQ_TEMP[l] <= #UDLY PIO_IN[l] & IRQ_MASK[l];
1211 end
1212 end
1214 end // if (GPIO_WB_DAT_WIDTH == 8)
1216 else if (GPIO_WB_DAT_WIDTH == 32) begin
1218 genvar i;
1219 for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1)
1220 begin
1221 always @(posedge CLK_I or posedge RST_I)
1222 if (RST_I)
1223 IRQ_TEMP[i] <= #UDLY 0;
1224 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0])
1225 IRQ_TEMP[i] <= #UDLY IRQ_TEMP[i] & GPIO_DAT_I_switch[i];
1226 else
1227 IRQ_TEMP[i] <= #UDLY PIO_IN[i] & IRQ_MASK[i];
1228 end
1229 if (DATA_WIDTH > 8) begin
1230 genvar j;
1231 for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1)
1232 begin
1233 always @(posedge CLK_I or posedge RST_I)
1234 if (RST_I)
1235 IRQ_TEMP[j] <= #UDLY 0;
1236 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1])
1237 IRQ_TEMP[j] <= #UDLY IRQ_TEMP[j] & GPIO_DAT_I_switch[j];
1238 else
1239 IRQ_TEMP[j] <= #UDLY PIO_IN[j] & IRQ_MASK[j];
1240 end
1241 end
1242 if (DATA_WIDTH > 16) begin
1243 genvar k;
1244 for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1)
1245 begin
1246 always @(posedge CLK_I or posedge RST_I)
1247 if (RST_I)
1248 IRQ_TEMP[k] <= #UDLY 0;
1249 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2])
1250 IRQ_TEMP[k] <= #UDLY IRQ_TEMP[k] & GPIO_DAT_I_switch[k];
1251 else
1252 IRQ_TEMP[k] <= #UDLY PIO_IN[k] & IRQ_MASK[k];
1253 end
1254 end
1255 if (DATA_WIDTH > 24) begin
1256 genvar l;
1257 for (l = 24; (l < DATA_WIDTH) && (l < 32); l = l + 1)
1258 begin
1259 always @(posedge CLK_I or posedge RST_I)
1260 if (RST_I)
1261 IRQ_TEMP[l] <= #UDLY 0;
1262 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3])
1263 IRQ_TEMP[l] <= #UDLY IRQ_TEMP[l] & GPIO_DAT_I_switch[l];
1264 else
1265 IRQ_TEMP[l] <= #UDLY PIO_IN[l] & IRQ_MASK[l];
1266 end
1267 end
1269 end // if (GPIO_WB_DAT_WIDTH == 32)
1271 assign IRQ_O = |IRQ_TEMP;
1273 end // if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (LEVEL == 1))
1275 else if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (EDGE == 1)) begin
1276 // edge mode IRQ
1278 always @(posedge CLK_I or posedge RST_I)
1279 if (RST_I)
1280 PIO_DATA_DLY <= #UDLY 0;
1281 else
1282 PIO_DATA_DLY <= PIO_IN;
1284 // edge-capture register bits are treated as individual bits.
1285 if (GPIO_WB_DAT_WIDTH == 8) begin
1287 genvar i;
1288 for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1)
1289 begin
1290 always @(posedge CLK_I or posedge RST_I)
1291 if (RST_I)
1292 EDGE_CAPTURE[i] <= #UDLY 0;
1293 else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (POSE_EDGE_IRQ == 1))
1294 EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i];
1295 else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (NEGE_EDGE_IRQ == 1))
1296 EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i];
1297 else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1))
1298 EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i];
1299 else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1))
1300 EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i];
1301 else if ( (~IRQ_MASK[i]) & GPIO_DAT_I_switch[i] & IRQ_MASK_WR_EN_0)
1302 // interrupt mask is being set, so clear edge-capture
1303 EDGE_CAPTURE[i] <= #UDLY 0;
1304 else if (EDGE_CAP_WR_EN_0)
1305 // user's writing to the edge register, so update edge capture
1306 // register
1307 EDGE_CAPTURE[i] <= #UDLY EDGE_CAPTURE[i] & GPIO_DAT_I_switch[i];
1308 end
1310 if (DATA_WIDTH > 8) begin
1311 genvar j;
1312 for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1)
1313 begin
1314 always @(posedge CLK_I or posedge RST_I)
1315 if (RST_I)
1316 EDGE_CAPTURE[j] <= #UDLY 0;
1317 else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (POSE_EDGE_IRQ == 1))
1318 EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j];
1319 else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (NEGE_EDGE_IRQ == 1))
1320 EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j];
1321 else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1))
1322 EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j];
1323 else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1))
1324 EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j];
1325 else if ( (~IRQ_MASK[j]) & GPIO_DAT_I_switch[j-8] & IRQ_MASK_WR_EN_1)
1326 // interrupt mask is being set, so clear edge-capture
1327 EDGE_CAPTURE[j] <= #UDLY 0;
1328 else if (EDGE_CAP_WR_EN_1)
1329 // user's writing to the edge register, so update edge capture
1330 // register
1331 EDGE_CAPTURE[j] <= #UDLY EDGE_CAPTURE[j] & GPIO_DAT_I_switch[j-8];
1332 end
1333 end
1335 if (DATA_WIDTH > 16) begin
1336 genvar k;
1337 for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1)
1338 begin
1339 always @(posedge CLK_I or posedge RST_I)
1340 if (RST_I)
1341 EDGE_CAPTURE[k] <= #UDLY 0;
1342 else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (POSE_EDGE_IRQ == 1))
1343 EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k];
1344 else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (NEGE_EDGE_IRQ == 1))
1345 EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k];
1346 else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1))
1347 EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k];
1348 else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1))
1349 EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k];
1350 else if ( (~IRQ_MASK[k]) & GPIO_DAT_I_switch[k-16] & IRQ_MASK_WR_EN_2)
1351 // interrupt mask is being set, so clear edge-capture
1352 EDGE_CAPTURE[k] <= #UDLY 0;
1353 else if (EDGE_CAP_WR_EN_2)
1354 // user's writing to the edge register, so update edge capture
1355 // register
1356 EDGE_CAPTURE[k] <= #UDLY EDGE_CAPTURE[k] & GPIO_DAT_I_switch[k-16];
1357 end
1358 end
1360 if (DATA_WIDTH > 24) begin
1361 genvar l;
1362 for (l = 24; l < DATA_WIDTH; l = l + 1)
1363 begin
1364 always @(posedge CLK_I or posedge RST_I)
1365 if (RST_I)
1366 EDGE_CAPTURE[l] <= #UDLY 0;
1367 else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (POSE_EDGE_IRQ == 1))
1368 EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l];
1369 else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (NEGE_EDGE_IRQ == 1))
1370 EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l];
1371 else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1))
1372 EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l];
1373 else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1))
1374 EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l];
1375 else if ( (~IRQ_MASK[l]) & GPIO_DAT_I_switch[l-24] & IRQ_MASK_WR_EN_3)
1376 // interrupt mask is being set, so clear edge-capture
1377 EDGE_CAPTURE[l] <= #UDLY 0;
1378 else if (EDGE_CAP_WR_EN_3)
1379 // user's writing to the edge register, so update edge capture
1380 // register
1381 EDGE_CAPTURE[l] <= #UDLY EDGE_CAPTURE[l] & GPIO_DAT_I_switch[l-24];
1382 end
1383 end
1385 end // if (GPIO_WB_DAT_WIDTH == 8)
1386 else if (GPIO_WB_DAT_WIDTH == 32) begin
1388 genvar i;
1389 for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1)
1390 begin
1391 always @(posedge CLK_I or posedge RST_I)
1392 if (RST_I)
1393 EDGE_CAPTURE[i] <= #UDLY 0;
1394 else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (POSE_EDGE_IRQ == 1))
1395 EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i];
1396 else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (NEGE_EDGE_IRQ == 1))
1397 EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i];
1398 else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1))
1399 EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i];
1400 else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1))
1401 EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i];
1402 else if ( (~IRQ_MASK[i]) & GPIO_DAT_I_switch[i] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0])
1403 // interrupt mask is being set, so clear edge-capture
1404 EDGE_CAPTURE[i] <= #UDLY 0;
1405 else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[0])
1406 // user's writing to the edge register, so update edge capture
1407 // register
1408 EDGE_CAPTURE[i] <= #UDLY EDGE_CAPTURE[i] & GPIO_DAT_I_switch[i];
1409 end
1411 if (DATA_WIDTH > 8) begin
1412 genvar j;
1413 for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1)
1414 begin
1415 always @(posedge CLK_I or posedge RST_I)
1416 if (RST_I)
1417 EDGE_CAPTURE[j] <= #UDLY 0;
1418 else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (POSE_EDGE_IRQ == 1))
1419 EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j];
1420 else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (NEGE_EDGE_IRQ == 1))
1421 EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j];
1422 else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1))
1423 EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j];
1424 else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1))
1425 EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j];
1426 else if ( (~IRQ_MASK[j]) & GPIO_DAT_I_switch[j-8] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0])
1427 // interrupt mask is being set, so clear edge-capture
1428 EDGE_CAPTURE[j] <= #UDLY 0;
1429 else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[0])
1430 // user's writing to the edge register, so update edge capture
1431 // register
1432 EDGE_CAPTURE[j] <= #UDLY EDGE_CAPTURE[j] & GPIO_DAT_I_switch[j];
1433 end
1434 end
1436 if (DATA_WIDTH > 16) begin
1437 genvar k;
1438 for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1)
1439 begin
1440 always @(posedge CLK_I or posedge RST_I)
1441 if (RST_I)
1442 EDGE_CAPTURE[k] <= #UDLY 0;
1443 else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (POSE_EDGE_IRQ == 1))
1444 EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k];
1445 else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (NEGE_EDGE_IRQ == 1))
1446 EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k];
1447 else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1))
1448 EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k];
1449 else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1))
1450 EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k];
1451 else if ( (~IRQ_MASK[k]) & GPIO_DAT_I_switch[k-16] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2])
1452 // interrupt mask is being set, so clear edge-capture
1453 EDGE_CAPTURE[k] <= #UDLY 0;
1454 else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[2])
1455 // user's writing to the edge register, so update edge capture
1456 // register
1457 EDGE_CAPTURE[k] <= #UDLY EDGE_CAPTURE[k] & GPIO_DAT_I_switch[k];
1458 end
1459 end
1461 if (DATA_WIDTH > 24) begin
1462 genvar l;
1463 for (l = 24; l < DATA_WIDTH; l = l + 1)
1464 begin
1465 always @(posedge CLK_I or posedge RST_I)
1466 if (RST_I)
1467 EDGE_CAPTURE[l] <= #UDLY 0;
1468 else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (POSE_EDGE_IRQ == 1))
1469 EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l];
1470 else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (NEGE_EDGE_IRQ == 1))
1471 EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l];
1472 else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1))
1473 EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l];
1474 else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1))
1475 EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l];
1476 else if ( (~IRQ_MASK[l]) & GPIO_DAT_I_switch[l-24] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3])
1477 // interrupt mask is being set, so clear edge-capture
1478 EDGE_CAPTURE[l] <= #UDLY 0;
1479 else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[3])
1480 // user's writing to the edge register, so update edge capture
1481 // register
1482 EDGE_CAPTURE[l] <= #UDLY EDGE_CAPTURE[l] & GPIO_DAT_I_switch[l];
1483 end
1484 end
1486 end // if (GPIO_WB_DAT_WIDTH == 32)
1488 assign IRQ_O = |(EDGE_CAPTURE[DATA_WIDTH-1:0] & IRQ_MASK[DATA_WIDTH-1:0]);
1490 end // if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (EDGE == 1))
1492 //----------------------------------
1493 //--BOTH_INPUT_AND_OUTPUT MODE IRQ
1494 //----------------------------------
1495 else if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (LEVEL == 1)) begin
1497 if (GPIO_WB_DAT_WIDTH == 8) begin
1499 genvar iitb_idx;
1500 for (iitb_idx = 0; (iitb_idx < INPUT_WIDTH) && (iitb_idx < 8); iitb_idx = iitb_idx + 1)
1501 begin
1502 always @(posedge CLK_I or posedge RST_I)
1503 if (RST_I)
1504 IRQ_TEMP_BOTH[iitb_idx] <= #UDLY 0;
1505 else if (IRQ_MASK_WR_EN_0)
1506 IRQ_TEMP_BOTH[iitb_idx] <= #UDLY IRQ_TEMP_BOTH[iitb_idx] & GPIO_DAT_I_switch[iitb_idx];
1507 else
1508 IRQ_TEMP_BOTH[iitb_idx] <= #UDLY PIO_BOTH_IN[iitb_idx] & IRQ_MASK_BOTH[iitb_idx];
1509 end
1510 if (INPUT_WIDTH > 8) begin
1511 genvar jitb_idx;
1512 for (jitb_idx = 8; (jitb_idx < INPUT_WIDTH) && (jitb_idx < 16); jitb_idx = jitb_idx + 1)
1513 begin
1514 always @(posedge CLK_I or posedge RST_I)
1515 if (RST_I)
1516 IRQ_TEMP_BOTH[jitb_idx] <= #UDLY 0;
1517 else if (IRQ_MASK_WR_EN_1)
1518 IRQ_TEMP_BOTH[jitb_idx] <= #UDLY IRQ_TEMP_BOTH[jitb_idx] & GPIO_DAT_I_switch[jitb_idx - 8];
1519 else
1520 IRQ_TEMP_BOTH[jitb_idx] <= #UDLY PIO_BOTH_IN[jitb_idx] & IRQ_MASK_BOTH[jitb_idx];
1521 end
1522 end
1523 if (INPUT_WIDTH > 16) begin
1524 genvar kitb_idx;
1525 for (kitb_idx = 16; (kitb_idx < INPUT_WIDTH) && (kitb_idx < 24); kitb_idx = kitb_idx + 1)
1526 begin
1527 always @(posedge CLK_I or posedge RST_I)
1528 if (RST_I)
1529 IRQ_TEMP_BOTH[kitb_idx] <= #UDLY 0;
1530 else if (IRQ_MASK_WR_EN_2)
1531 IRQ_TEMP_BOTH[kitb_idx] <= #UDLY IRQ_TEMP_BOTH[kitb_idx] & GPIO_DAT_I_switch[kitb_idx - 16];
1532 else
1533 IRQ_TEMP_BOTH[kitb_idx] <= #UDLY PIO_BOTH_IN[kitb_idx] & IRQ_MASK_BOTH[kitb_idx];
1534 end
1535 end
1536 if (INPUT_WIDTH > 24) begin
1537 genvar litb_idx;
1538 for (litb_idx = 24; (litb_idx < INPUT_WIDTH) && (litb_idx < 24); litb_idx = litb_idx + 1)
1539 begin
1540 always @(posedge CLK_I or posedge RST_I)
1541 if (RST_I)
1542 IRQ_TEMP_BOTH[litb_idx] <= #UDLY 0;
1543 else if (IRQ_MASK_WR_EN_3)
1544 IRQ_TEMP_BOTH[litb_idx] <= #UDLY IRQ_TEMP_BOTH[litb_idx] & GPIO_DAT_I_switch[litb_idx - 24];
1545 else
1546 IRQ_TEMP_BOTH[litb_idx] <= #UDLY PIO_BOTH_IN[litb_idx] & IRQ_MASK_BOTH[litb_idx];
1547 end
1548 end
1550 end // if (GPIO_WB_DAT_WIDTH == 8)
1552 else if (GPIO_WB_DAT_WIDTH == 32) begin
1554 genvar iitb_idx;
1555 for (iitb_idx = 0; (iitb_idx < INPUT_WIDTH) && (iitb_idx < 8); iitb_idx = iitb_idx + 1)
1556 begin
1557 always @(posedge CLK_I or posedge RST_I)
1558 if (RST_I)
1559 IRQ_TEMP_BOTH[iitb_idx] <= #UDLY 0;
1560 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0])
1561 IRQ_TEMP_BOTH[iitb_idx] <= #UDLY IRQ_TEMP_BOTH[iitb_idx] & GPIO_DAT_I_switch[iitb_idx];
1562 else
1563 IRQ_TEMP_BOTH[iitb_idx] <= #UDLY PIO_BOTH_IN[iitb_idx] & IRQ_MASK_BOTH[iitb_idx];
1564 end
1565 if (INPUT_WIDTH > 8) begin
1566 genvar jitb_idx;
1567 for (jitb_idx = 8; (jitb_idx < INPUT_WIDTH) && (jitb_idx < 16); jitb_idx = jitb_idx + 1)
1568 begin
1569 always @(posedge CLK_I or posedge RST_I)
1570 if (RST_I)
1571 IRQ_TEMP_BOTH[jitb_idx] <= #UDLY 0;
1572 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1])
1573 IRQ_TEMP_BOTH[jitb_idx] <= #UDLY IRQ_TEMP_BOTH[jitb_idx] & GPIO_DAT_I_switch[jitb_idx];
1574 else
1575 IRQ_TEMP_BOTH[jitb_idx] <= #UDLY PIO_BOTH_IN[jitb_idx] & IRQ_MASK_BOTH[jitb_idx];
1576 end
1577 end
1578 if (INPUT_WIDTH > 16) begin
1579 genvar kitb_idx;
1580 for (kitb_idx = 16; (kitb_idx < INPUT_WIDTH) && (kitb_idx < 24); kitb_idx = kitb_idx + 1)
1581 begin
1582 always @(posedge CLK_I or posedge RST_I)
1583 if (RST_I)
1584 IRQ_TEMP_BOTH[kitb_idx] <= #UDLY 0;
1585 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2])
1586 IRQ_TEMP_BOTH[kitb_idx] <= #UDLY IRQ_TEMP_BOTH[kitb_idx] & GPIO_DAT_I_switch[kitb_idx];
1587 else
1588 IRQ_TEMP_BOTH[kitb_idx] <= #UDLY PIO_BOTH_IN[kitb_idx] & IRQ_MASK_BOTH[kitb_idx];
1589 end
1590 end
1591 if (INPUT_WIDTH > 24) begin
1592 genvar litb_idx;
1593 for (litb_idx = 24; (litb_idx < INPUT_WIDTH) && (litb_idx < 24); litb_idx = litb_idx + 1)
1594 begin
1595 always @(posedge CLK_I or posedge RST_I)
1596 if (RST_I)
1597 IRQ_TEMP_BOTH[litb_idx] <= #UDLY 0;
1598 else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3])
1599 IRQ_TEMP_BOTH[litb_idx] <= #UDLY IRQ_TEMP_BOTH[litb_idx] & GPIO_DAT_I_switch[litb_idx];
1600 else
1601 IRQ_TEMP_BOTH[litb_idx] <= #UDLY PIO_BOTH_IN[litb_idx] & IRQ_MASK_BOTH[litb_idx];
1602 end
1603 end
1605 end // if (GPIO_WB_DAT_WIDTH == 32)
1607 assign IRQ_O = |IRQ_TEMP_BOTH;
1609 end // if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (LEVEL == 1))
1611 // edge mode IRQ
1612 else if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (EDGE == 1)) begin
1614 always @(posedge CLK_I or posedge RST_I)
1615 if (RST_I)
1616 PIO_DATA_DLY_BOTH <= #UDLY 0;
1617 else
1618 PIO_DATA_DLY_BOTH <= PIO_BOTH_IN;
1620 // edge-capture register bits are treated as individual bits.
1621 if (GPIO_WB_DAT_WIDTH == 8) begin
1623 genvar i_both;
1624 for (i_both = 0; (i_both < INPUT_WIDTH) && (i_both < 8); i_both = i_both + 1)
1625 begin
1626 always @(posedge CLK_I or posedge RST_I)
1627 if (RST_I)
1628 EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0;
1629 else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && POSE_EDGE_IRQ == 1)
1630 EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both];
1631 else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && NEGE_EDGE_IRQ == 1)
1632 EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both];
1633 else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1)
1634 EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both];
1635 else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1)
1636 EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both];
1637 else if ( (~IRQ_MASK_BOTH[i_both]) & GPIO_DAT_I_switch[i_both] & IRQ_MASK_WR_EN_0 )
1638 // interrupt mask is being set, so clear edge-capture
1639 EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0;
1640 else if (EDGE_CAP_WR_EN_0)
1641 // user's writing to the edge register, so update edge capture
1642 // register
1643 EDGE_CAPTURE_BOTH[i_both] <= #UDLY EDGE_CAPTURE_BOTH[i_both] & GPIO_DAT_I_switch[i_both];
1644 end
1645 if (INPUT_WIDTH > 8) begin
1646 genvar j_both;
1647 for (j_both = 8; (j_both < INPUT_WIDTH) && (j_both < 16); j_both = j_both + 1)
1648 begin
1649 always @(posedge CLK_I or posedge RST_I)
1650 if (RST_I)
1651 EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0;
1652 else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && POSE_EDGE_IRQ == 1)
1653 EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both];
1654 else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) && NEGE_EDGE_IRQ == 1)
1655 EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both];
1656 else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1)
1657 EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both];
1658 else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1)
1659 EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both];
1660 else if ( (~IRQ_MASK_BOTH[j_both]) & GPIO_DAT_I_switch[j_both-8] & IRQ_MASK_WR_EN_1 )
1661 // interrupt mask is being set, so clear edge-capture
1662 EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0;
1663 else if (EDGE_CAP_WR_EN_1)
1664 // user's writing to the edge register, so update edge capture
1665 // register
1666 EDGE_CAPTURE_BOTH[j_both] <= #UDLY EDGE_CAPTURE_BOTH[j_both] & GPIO_DAT_I_switch[j_both-8];
1667 end
1668 end
1669 if (INPUT_WIDTH > 16) begin
1670 genvar k_both;
1671 for (k_both = 16; (k_both < INPUT_WIDTH) && (k_both < 24); k_both = k_both + 1)
1672 begin
1673 always @(posedge CLK_I or posedge RST_I)
1674 if (RST_I)
1675 EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0;
1676 else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && POSE_EDGE_IRQ == 1)
1677 EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both];
1678 else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) && NEGE_EDGE_IRQ == 1)
1679 EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both];
1680 else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1)
1681 EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both];
1682 else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1)
1683 EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both];
1684 else if ( (~IRQ_MASK_BOTH[k_both]) & GPIO_DAT_I_switch[k_both-16] & IRQ_MASK_WR_EN_2 )
1685 // interrupt mask is being set, so clear edge-capture
1686 EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0;
1687 else if (EDGE_CAP_WR_EN_2)
1688 // user's writing to the edge register, so update edge capture
1689 // register
1690 EDGE_CAPTURE_BOTH[k_both] <= #UDLY EDGE_CAPTURE_BOTH[k_both] & GPIO_DAT_I_switch[k_both-16];
1691 end
1692 end
1693 if (INPUT_WIDTH > 24) begin
1694 genvar l_both;
1695 for (l_both = 24; (l_both < INPUT_WIDTH) && (l_both < 32); l_both = l_both + 1)
1696 begin
1697 always @(posedge CLK_I or posedge RST_I)
1698 if (RST_I)
1699 EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0;
1700 else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && POSE_EDGE_IRQ == 1)
1701 EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both];
1702 else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) && NEGE_EDGE_IRQ == 1)
1703 EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both];
1704 else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1)
1705 EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both];
1706 else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1)
1707 EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both];
1708 else if ( (~IRQ_MASK_BOTH[l_both]) & GPIO_DAT_I_switch[l_both-24] & IRQ_MASK_WR_EN_3 )
1709 // interrupt mask is being set, so clear edge-capture
1710 EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0;
1711 else if (EDGE_CAP_WR_EN_3)
1712 // user's writing to the edge register, so update edge capture
1713 // register
1714 EDGE_CAPTURE_BOTH[l_both] <= #UDLY EDGE_CAPTURE_BOTH[l_both] & GPIO_DAT_I_switch[l_both-24];
1715 end
1716 end
1718 end // if (GPIO_WB_DAT_WIDTH == 8)
1719 else if (GPIO_WB_DAT_WIDTH == 32) begin
1721 genvar i_both;
1722 for (i_both = 0; (i_both < INPUT_WIDTH) && (i_both < 8); i_both = i_both + 1)
1723 begin
1724 always @(posedge CLK_I or posedge RST_I)
1725 if (RST_I)
1726 EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0;
1727 else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && POSE_EDGE_IRQ == 1)
1728 EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both];
1729 else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && NEGE_EDGE_IRQ == 1)
1730 EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both];
1731 else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1)
1732 EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both];
1733 else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1)
1734 EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both];
1735 else if ( (~IRQ_MASK_BOTH[i_both]) & GPIO_DAT_I_switch[i_both] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0])
1736 // interrupt mask is being set, so clear edge-capture
1737 EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0;
1738 else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[0])
1739 // user's writing to the edge register, so update edge capture
1740 // register
1741 EDGE_CAPTURE_BOTH[i_both] <= #UDLY EDGE_CAPTURE_BOTH[i_both] & GPIO_DAT_I_switch[i_both];
1742 end
1743 if (INPUT_WIDTH > 8) begin
1744 genvar j_both;
1745 for (j_both = 8; (j_both < INPUT_WIDTH) && (j_both < 16); j_both = j_both + 1)
1746 begin
1747 always @(posedge CLK_I or posedge RST_I)
1748 if (RST_I)
1749 EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0;
1750 else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && POSE_EDGE_IRQ == 1)
1751 EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both];
1752 else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) && NEGE_EDGE_IRQ == 1)
1753 EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both];
1754 else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1)
1755 EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both];
1756 else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1)
1757 EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both];
1758 else if ( (~IRQ_MASK_BOTH[j_both]) & GPIO_DAT_I_switch[j_both-8] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1])
1759 // interrupt mask is being set, so clear edge-capture
1760 EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0;
1761 else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[1])
1762 // user's writing to the edge register, so update edge capture
1763 // register
1764 EDGE_CAPTURE_BOTH[j_both] <= #UDLY EDGE_CAPTURE_BOTH[j_both] & GPIO_DAT_I_switch[j_both];
1765 end
1766 end
1767 if (INPUT_WIDTH > 16) begin
1768 genvar k_both;
1769 for (k_both = 16; (k_both < INPUT_WIDTH) && (k_both < 24); k_both = k_both + 1)
1770 begin
1771 always @(posedge CLK_I or posedge RST_I)
1772 if (RST_I)
1773 EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0;
1774 else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && POSE_EDGE_IRQ == 1)
1775 EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both];
1776 else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) && NEGE_EDGE_IRQ == 1)
1777 EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both];
1778 else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1)
1779 EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both];
1780 else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1)
1781 EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both];
1782 else if ( (~IRQ_MASK_BOTH[k_both]) & GPIO_DAT_I_switch[k_both-16] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2])
1783 // interrupt mask is being set, so clear edge-capture
1784 EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0;
1785 else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[2])
1786 // user's writing to the edge register, so update edge capture
1787 // register
1788 EDGE_CAPTURE_BOTH[k_both] <= #UDLY EDGE_CAPTURE_BOTH[k_both] & GPIO_DAT_I_switch[k_both];
1789 end
1790 end
1791 if (INPUT_WIDTH > 24) begin
1792 genvar l_both;
1793 for (l_both = 24; (l_both < INPUT_WIDTH) && (l_both < 32); l_both = l_both + 1)
1794 begin
1795 always @(posedge CLK_I or posedge RST_I)
1796 if (RST_I)
1797 EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0;
1798 else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && POSE_EDGE_IRQ == 1)
1799 EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both];
1800 else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) && NEGE_EDGE_IRQ == 1)
1801 EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both];
1802 else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1)
1803 EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both];
1804 else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1)
1805 EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both];
1806 else if ( (~IRQ_MASK_BOTH[l_both]) & GPIO_DAT_I_switch[l_both-24] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3])
1807 // interrupt mask is being set, so clear edge-capture
1808 EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0;
1809 else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[3])
1810 // user's writing to the edge register, so update edge capture
1811 // register
1812 EDGE_CAPTURE_BOTH[l_both] <= #UDLY EDGE_CAPTURE_BOTH[l_both] & GPIO_DAT_I_switch[l_both];
1813 end
1814 end
1816 end // if (GPIO_WB_DAT_WIDTH == 32)
1818 assign IRQ_O = |(EDGE_CAPTURE_BOTH & IRQ_MASK_BOTH);
1820 end // if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (EDGE == 1))
1822 else if (IRQ_MODE == 1 && TRISTATE_PORTS == 1) begin
1824 assign IRQ_O = |IRQ_TRI_TEMP;
1825 end
1827 else begin
1829 assign IRQ_O = 1'b0;
1830 end
1832 endgenerate
1835 endmodule
1836 `endif // GPIO_V