1.1 --- a/rtl/verilog/gpio.v Fri Aug 13 10:41:29 2010 +0100 1.2 +++ b/rtl/verilog/gpio.v Sat Aug 06 01:43:24 2011 +0100 1.3 @@ -1,18 +1,39 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2004 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 +// ================================================================== 1.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.15 +// ------------------------------------------------------------------ 1.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.17 +// ALL RIGHTS RESERVED 1.18 +// ------------------------------------------------------------------ 1.19 +// 1.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.21 +// 1.22 +// Permission: 1.23 +// 1.24 +// Lattice Semiconductor grants permission to use this code 1.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.26 +// Open Source License Agreement. 1.27 +// 1.28 +// Disclaimer: 1.29 // 1.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.33 -// U.S.A email: techsupport@latticesemi.com 1.34 -// =============================================================================/ 1.35 +// Lattice Semiconductor provides no warranty regarding the use or 1.36 +// functionality of this code. It is the user's responsibility to 1.37 +// verify the user’s design for consistency and functionality through 1.38 +// the use of formal verification methods. 1.39 +// 1.40 +// -------------------------------------------------------------------- 1.41 +// 1.42 +// Lattice Semiconductor Corporation 1.43 +// 5555 NE Moore Court 1.44 +// Hillsboro, OR 97214 1.45 +// U.S.A 1.46 +// 1.47 +// TEL: 1-800-Lattice (USA and Canada) 1.48 +// 503-286-8001 (other locations) 1.49 +// 1.50 +// web: http://www.latticesemi.com/ 1.51 +// email: techsupport@latticesemi.com 1.52 +// 1.53 +// -------------------------------------------------------------------- 1.54 // FILE DETAILS 1.55 // Project : GPIO for LM32 1.56 // File : gpio.v 1.57 @@ -34,346 +55,1782 @@ 1.58 // Mod. Date : 11 Oct. 2008 1.59 // Changes Made : Update the Edge Capture Register clean method 1.60 // Make IRQ Mask register readable 1.61 +// 1.62 +// Version : 3.2 1.63 +// Mod. Data : Jun 6, 2010 1.64 +// Changes Made : 1. Provide capability to read/write bytes (when GPIO larger 1.65 +// than 8 bits wide) 1.66 +// 2. Provide capability to use a 32-bit or 8-bit data bus on 1.67 +// the WISHBONE slave port 1.68 +// 3. Perform a big-endian to little-endian conversion in 1.69 +// hardware 1.70 // ============================================================================= 1.71 `ifndef GPIO_V 1.72 `define GPIO_V 1.73 `timescale 1ns/100 ps 1.74 `include "system_conf.v" 1.75 -module gpio #(parameter DATA_WIDTH = 16, 1.76 - parameter INPUT_WIDTH = 16, 1.77 - parameter OUTPUT_WIDTH = 16, 1.78 - parameter IRQ_MODE = 0, 1.79 - parameter LEVEL = 0, 1.80 - parameter EDGE = 0, 1.81 - parameter POSE_EDGE_IRQ = 0, 1.82 - parameter NEGE_EDGE_IRQ = 0, 1.83 - parameter EITHER_EDGE_IRQ = 0, 1.84 - parameter INPUT_PORTS_ONLY = 1, 1.85 - parameter OUTPUT_PORTS_ONLY = 0, 1.86 - parameter BOTH_INPUT_AND_OUTPUT = 0, 1.87 - parameter TRISTATE_PORTS = 0) 1.88 - ( 1.89 - //system clock and reset 1.90 - CLK_I, 1.91 - RST_I, 1.92 - //wishbone interface signals 1.93 - GPIO_ADR_I, 1.94 - GPIO_CYC_I, 1.95 - GPIO_DAT_I, 1.96 - GPIO_SEL_I, 1.97 - GPIO_STB_I, 1.98 - GPIO_WE_I, 1.99 - GPIO_LOCK_I, 1.100 - GPIO_CTI_I, 1.101 - GPIO_BTE_I, 1.102 - GPIO_ACK_O, 1.103 - GPIO_RTY_O, 1.104 - GPIO_DAT_O, 1.105 - GPIO_ERR_O, 1.106 - IRQ_O, //bit_or of all IRQs 1.107 - //PIO side 1.108 - PIO_IN, 1.109 - PIO_OUT, 1.110 - PIO_IO, 1.111 - PIO_BOTH_IN, 1.112 - PIO_BOTH_OUT 1.113 - ); 1.114 - 1.115 -//--------------------------------------------------------------------- 1.116 -// inputs 1.117 - // 1.118 - input CLK_I; 1.119 - input RST_I; 1.120 - input [31:0] GPIO_ADR_I; 1.121 - input GPIO_CYC_I; 1.122 - input [31:0] GPIO_DAT_I; 1.123 - input [3:0] GPIO_SEL_I; 1.124 - input GPIO_STB_I; 1.125 - input GPIO_WE_I; 1.126 - input GPIO_LOCK_I; 1.127 - input [2:0] GPIO_CTI_I; 1.128 - input [1:0] GPIO_BTE_I; 1.129 - input [DATA_WIDTH-1:0] PIO_IN; 1.130 - input [INPUT_WIDTH-1:0] PIO_BOTH_IN; 1.131 -//--------------------------------------------------------------------- 1.132 -// outputs 1.133 -// 1.134 - output GPIO_ACK_O; 1.135 - output GPIO_RTY_O; 1.136 - output [31:0] GPIO_DAT_O; 1.137 - output GPIO_ERR_O; 1.138 - output IRQ_O; 1.139 - output [DATA_WIDTH-1:0] PIO_OUT; 1.140 - output [OUTPUT_WIDTH-1:0] PIO_BOTH_OUT; 1.141 -//---------------- 1.142 -//inout mode 1.143 - inout [DATA_WIDTH-1:0] PIO_IO; 1.144 -//---------------- 1.145 -//process 1.146 +module gpio 1.147 + #( 1.148 + parameter GPIO_WB_DAT_WIDTH = 32, 1.149 + parameter GPIO_WB_ADR_WIDTH = 4, 1.150 + parameter DATA_WIDTH = 16, 1.151 + parameter INPUT_WIDTH = 16, 1.152 + parameter OUTPUT_WIDTH = 16, 1.153 + parameter IRQ_MODE = 0, 1.154 + parameter LEVEL = 0, 1.155 + parameter EDGE = 0, 1.156 + parameter POSE_EDGE_IRQ = 0, 1.157 + parameter NEGE_EDGE_IRQ = 0, 1.158 + parameter EITHER_EDGE_IRQ = 0, 1.159 + parameter INPUT_PORTS_ONLY = 1, 1.160 + parameter OUTPUT_PORTS_ONLY = 0, 1.161 + parameter BOTH_INPUT_AND_OUTPUT = 0, 1.162 + parameter TRISTATE_PORTS = 0 1.163 + ) 1.164 + ( 1.165 + // system clock and reset 1.166 + input CLK_I, 1.167 + input RST_I, 1.168 + 1.169 + // wishbone interface signals 1.170 + input GPIO_CYC_I, 1.171 + input GPIO_STB_I, 1.172 + input GPIO_WE_I, 1.173 + input GPIO_LOCK_I, 1.174 + input [2:0] GPIO_CTI_I, 1.175 + input [1:0] GPIO_BTE_I, 1.176 + input [GPIO_WB_ADR_WIDTH-1:0] GPIO_ADR_I, 1.177 + input [GPIO_WB_DAT_WIDTH-1:0] GPIO_DAT_I, 1.178 + input [GPIO_WB_DAT_WIDTH/8-1:0] GPIO_SEL_I, 1.179 + output reg GPIO_ACK_O, 1.180 + output GPIO_ERR_O, 1.181 + output GPIO_RTY_O, 1.182 + output [GPIO_WB_DAT_WIDTH-1:0] GPIO_DAT_O, 1.183 + 1.184 + output IRQ_O, 1.185 + 1.186 + // PIO side 1.187 + input [DATA_WIDTH-1:0] PIO_IN, 1.188 + input [INPUT_WIDTH-1:0] PIO_BOTH_IN, 1.189 + output [DATA_WIDTH-1:0] PIO_OUT, 1.190 + output [OUTPUT_WIDTH-1:0] PIO_BOTH_OUT, 1.191 + inout [DATA_WIDTH-1:0] PIO_IO 1.192 + ); 1.193 1.194 - parameter UDLY = 1; 1.195 + // The incoming data bus is big-endian and the internal memory-mapped registers of GPIO 1.196 + // component are little-endian. Performing a big-endian to little-endian conversion! 1.197 + wire [GPIO_WB_DAT_WIDTH-1:0] GPIO_DAT_I_switch, GPIO_DAT_O_switch; 1.198 + wire [GPIO_WB_DAT_WIDTH/8-1:0] GPIO_SEL_I_switch; 1.199 + generate 1.200 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.201 + assign GPIO_DAT_I_switch = GPIO_DAT_I; 1.202 + assign GPIO_SEL_I_switch = GPIO_SEL_I; 1.203 + assign GPIO_DAT_O = GPIO_DAT_O_switch; 1.204 + end 1.205 + else begin 1.206 + assign GPIO_DAT_I_switch = {GPIO_DAT_I[7:0], GPIO_DAT_I[15:8], GPIO_DAT_I[23:16], GPIO_DAT_I[31:24]}; 1.207 + assign GPIO_SEL_I_switch = {GPIO_SEL_I[0], GPIO_SEL_I[1], GPIO_SEL_I[2], GPIO_SEL_I[3]}; 1.208 + assign GPIO_DAT_O = {GPIO_DAT_O_switch[7:0], GPIO_DAT_O_switch[15:8], GPIO_DAT_O_switch[23:16], GPIO_DAT_O_switch[31:24]}; 1.209 + end 1.210 + endgenerate 1.211 + 1.212 + reg [OUTPUT_WIDTH-1:0] PIO_DATAO; 1.213 + reg [INPUT_WIDTH-1:0] PIO_DATAI; 1.214 + wire ADR_0, ADR_4, ADR_8, ADR_C; 1.215 + wire [DATA_WIDTH-1:0] tpio_out; 1.216 + 1.217 + wire PIO_DATA_WR_EN; 1.218 + wire PIO_DATA_WR_EN_0, PIO_DATA_WR_EN_1, PIO_DATA_WR_EN_2, PIO_DATA_WR_EN_3; 1.219 1.220 - wire ADR_0; 1.221 - wire ADR_4; 1.222 - wire ADR_8; 1.223 - wire ADR_C; 1.224 - wire read_addr_0; 1.225 - wire read_addr_4; 1.226 - wire read_addr_8; 1.227 - wire read_addr_C; 1.228 - wire GPIO_RTY_O; 1.229 - wire GPIO_ERR_O; 1.230 - wire [31:0] GPIO_DAT_O; 1.231 - wire IRQ_O; 1.232 - wire [DATA_WIDTH-1:0] PIO_OUT; 1.233 - wire [OUTPUT_WIDTH-1:0] PIO_BOTH_OUT; 1.234 - wire [DATA_WIDTH-1:0] tpio_out; 1.235 - wire PIO_DATA_WR_EN; 1.236 - wire PIO_TRI_WR_EN; 1.237 - wire IRQ_MASK_WR_EN; 1.238 - wire EDGE_CAP_WR_EN; 1.239 - wire PIO_DATA_RE_EN; 1.240 - wire PIO_TRI_RE_EN; 1.241 - wire IRQ_MASK_RE_EN; 1.242 - wire [DATA_WIDTH-1:0] IRQ_TRI_TEMP; 1.243 - reg [DATA_WIDTH-1:0] PIO_DATA; 1.244 - reg [DATA_WIDTH-1:0] IRQ_MASK; 1.245 - reg [INPUT_WIDTH-1:0] IRQ_MASK_BOTH; 1.246 - reg [DATA_WIDTH-1:0] IRQ_TEMP; 1.247 - reg [INPUT_WIDTH-1:0] IRQ_TEMP_BOTH; 1.248 - reg [DATA_WIDTH-1:0] EDGE_CAPTURE; 1.249 - reg [INPUT_WIDTH-1:0] EDGE_CAPTURE_BOTH; 1.250 - reg [DATA_WIDTH-1:0] PIO_DATA_DLY; 1.251 - reg [INPUT_WIDTH-1:0] PIO_DATA_DLY_BOTH; 1.252 - reg [OUTPUT_WIDTH-1:0] PIO_DATAO; 1.253 - reg [INPUT_WIDTH-1 :0] PIO_DATAI; 1.254 - reg GPIO_ACK_O; 1.255 - 1.256 + wire PIO_TRI_WR_EN; 1.257 + wire PIO_TRI_WR_EN_0, PIO_TRI_WR_EN_1, PIO_TRI_WR_EN_2, PIO_TRI_WR_EN_3; 1.258 + 1.259 + wire IRQ_MASK_WR_EN; 1.260 + wire IRQ_MASK_WR_EN_0, IRQ_MASK_WR_EN_1, IRQ_MASK_WR_EN_2, IRQ_MASK_WR_EN_3; 1.261 + 1.262 + wire EDGE_CAP_WR_EN; 1.263 + wire EDGE_CAP_WR_EN_0, EDGE_CAP_WR_EN_1, EDGE_CAP_WR_EN_2, EDGE_CAP_WR_EN_3; 1.264 + 1.265 + wire PIO_DATA_RE_EN; 1.266 + wire PIO_TRI_RE_EN; 1.267 + wire IRQ_MASK_RE_EN; 1.268 + wire [DATA_WIDTH-1:0] IRQ_TRI_TEMP; 1.269 + reg [DATA_WIDTH-1:0] PIO_DATA; 1.270 + reg [DATA_WIDTH-1:0] IRQ_MASK; 1.271 + reg [INPUT_WIDTH-1:0] IRQ_MASK_BOTH; 1.272 + reg [DATA_WIDTH-1:0] IRQ_TEMP; 1.273 + reg [INPUT_WIDTH-1:0] IRQ_TEMP_BOTH; 1.274 + reg [DATA_WIDTH-1:0] EDGE_CAPTURE; 1.275 + reg [INPUT_WIDTH-1:0] EDGE_CAPTURE_BOTH; 1.276 + reg [DATA_WIDTH-1:0] PIO_DATA_DLY; 1.277 + reg [INPUT_WIDTH-1:0] PIO_DATA_DLY_BOTH; 1.278 + 1.279 + parameter UDLY = 1; 1.280 + 1.281 assign GPIO_RTY_O = 1'b0; 1.282 assign GPIO_ERR_O = 1'b0; 1.283 - assign ADR_0 = (GPIO_ADR_I[3:0] == 4'b0000 ? 1'b1 : 0); // IO Data 1.284 - assign ADR_4 = (GPIO_ADR_I[3:0] == 4'b0100 ? 1'b1 : 0); // Tri-state Control 1.285 - assign ADR_8 = (GPIO_ADR_I[3:0] == 4'b1000 ? 1'b1 : 0); // IRQ Mask 1.286 - assign ADR_C = (GPIO_ADR_I[3:0] == 4'b1100 ? 1'b1 : 0); // Edge Capture 1.287 + assign ADR_0 = (GPIO_ADR_I[3:2] == 4'b00 ? 1'b1 : 0); // IO Data 1.288 + assign ADR_4 = (GPIO_ADR_I[3:2] == 4'b01 ? 1'b1 : 0); // Tri-state Control 1.289 + assign ADR_8 = (GPIO_ADR_I[3:2] == 4'b10 ? 1'b1 : 0); // IRQ Mask 1.290 + assign ADR_C = (GPIO_ADR_I[3:2] == 4'b11 ? 1'b1 : 0); // Edge Capture 1.291 + 1.292 + always @(posedge CLK_I or posedge RST_I) 1.293 + if(RST_I) 1.294 + GPIO_ACK_O <= #UDLY 1'b0; 1.295 + else if(GPIO_STB_I && (GPIO_ACK_O == 1'b0)) 1.296 + GPIO_ACK_O <= #UDLY 1'b1; 1.297 + else 1.298 + GPIO_ACK_O <= #UDLY 1'b0; 1.299 + 1.300 + 1.301 + generate 1.302 + if (INPUT_PORTS_ONLY == 1) begin 1.303 + always @(posedge CLK_I or posedge RST_I) 1.304 + if (RST_I) 1.305 + PIO_DATA <= #UDLY 0; 1.306 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:2] == 2'b00) 1.307 + PIO_DATA <= #UDLY PIO_IN; 1.308 + end 1.309 + endgenerate 1.310 + 1.311 + generate 1.312 + if (OUTPUT_PORTS_ONLY == 1) begin 1.313 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.314 + genvar ipd_idx; 1.315 + for (ipd_idx = 0; (ipd_idx < DATA_WIDTH) && (ipd_idx < 8); ipd_idx = ipd_idx + 1) 1.316 + begin 1.317 + always @(posedge CLK_I or posedge RST_I) 1.318 + if (RST_I) 1.319 + PIO_DATA[ipd_idx] <= #UDLY 0; 1.320 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000) 1.321 + PIO_DATA[ipd_idx] <= #UDLY GPIO_DAT_I_switch[ipd_idx]; 1.322 + end 1.323 + if (DATA_WIDTH > 8) begin 1.324 + genvar jpd_idx; 1.325 + for (jpd_idx = 8; (jpd_idx < DATA_WIDTH) && (jpd_idx < 16); jpd_idx = jpd_idx + 1) 1.326 + begin 1.327 + always @(posedge CLK_I or posedge RST_I) 1.328 + if (RST_I) 1.329 + PIO_DATA[jpd_idx] <= #UDLY 0; 1.330 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001) 1.331 + PIO_DATA[jpd_idx] <= #UDLY GPIO_DAT_I_switch[jpd_idx-8]; 1.332 + end 1.333 + end 1.334 + if (DATA_WIDTH > 16) begin 1.335 + genvar kpd_idx; 1.336 + for (kpd_idx = 16; (kpd_idx < DATA_WIDTH) && (kpd_idx < 24); kpd_idx = kpd_idx + 1) 1.337 + begin 1.338 + always @(posedge CLK_I or posedge RST_I) 1.339 + if (RST_I) 1.340 + PIO_DATA[kpd_idx] <= #UDLY 0; 1.341 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010) 1.342 + PIO_DATA[kpd_idx] <= #UDLY GPIO_DAT_I_switch[kpd_idx-16]; 1.343 + end 1.344 + end 1.345 + if (DATA_WIDTH > 24) begin 1.346 + genvar lpd_idx; 1.347 + for (lpd_idx = 24; (lpd_idx < DATA_WIDTH) && (lpd_idx < 32); lpd_idx = lpd_idx + 1) 1.348 + begin 1.349 + always @(posedge CLK_I or posedge RST_I) 1.350 + if (RST_I) 1.351 + PIO_DATA[lpd_idx] <= #UDLY 0; 1.352 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011) 1.353 + PIO_DATA[lpd_idx] <= #UDLY GPIO_DAT_I_switch[lpd_idx-24]; 1.354 + end 1.355 + end 1.356 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.357 + 1.358 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.359 + genvar ipd_idx; 1.360 + for (ipd_idx = 0; (ipd_idx < DATA_WIDTH) && (ipd_idx < 8); ipd_idx = ipd_idx + 1) 1.361 + begin 1.362 + always @(posedge CLK_I or posedge RST_I) 1.363 + if (RST_I) 1.364 + PIO_DATA[ipd_idx] <= #UDLY 0; 1.365 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[0]) 1.366 + PIO_DATA[ipd_idx] <= #UDLY GPIO_DAT_I_switch[ipd_idx]; 1.367 + end 1.368 + if (DATA_WIDTH > 8) begin 1.369 + genvar jpd_idx; 1.370 + for (jpd_idx = 8; (jpd_idx < DATA_WIDTH) && (jpd_idx < 16); jpd_idx = jpd_idx + 1) 1.371 + begin 1.372 + always @(posedge CLK_I or posedge RST_I) 1.373 + if (RST_I) 1.374 + PIO_DATA[jpd_idx] <= #UDLY 0; 1.375 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[1]) 1.376 + PIO_DATA[jpd_idx] <= #UDLY GPIO_DAT_I_switch[jpd_idx]; 1.377 + end 1.378 + end 1.379 + if (DATA_WIDTH > 16) begin 1.380 + genvar kpd_idx; 1.381 + for (kpd_idx = 16; (kpd_idx < DATA_WIDTH) && (kpd_idx < 24); kpd_idx = kpd_idx + 1) 1.382 + begin 1.383 + always @(posedge CLK_I or posedge RST_I) 1.384 + if (RST_I) 1.385 + PIO_DATA[kpd_idx] <= #UDLY 0; 1.386 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[2]) 1.387 + PIO_DATA[kpd_idx] <= #UDLY GPIO_DAT_I_switch[kpd_idx]; 1.388 + end 1.389 + end 1.390 + if (DATA_WIDTH > 24) begin 1.391 + genvar lpd_idx; 1.392 + for (lpd_idx = 24; (lpd_idx < DATA_WIDTH) && (lpd_idx < 32); lpd_idx = lpd_idx + 1) 1.393 + begin 1.394 + always @(posedge CLK_I or posedge RST_I) 1.395 + if (RST_I) 1.396 + PIO_DATA[lpd_idx] <= #UDLY 0; 1.397 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[3]) 1.398 + PIO_DATA[lpd_idx] <= #UDLY GPIO_DAT_I_switch[lpd_idx]; 1.399 + end 1.400 + end 1.401 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.402 + 1.403 + assign PIO_OUT = PIO_DATA; 1.404 + end 1.405 + endgenerate 1.406 + 1.407 + generate 1.408 + if (BOTH_INPUT_AND_OUTPUT == 1) begin 1.409 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.410 + genvar iopd_idx; 1.411 + for (iopd_idx = 0; (iopd_idx < OUTPUT_WIDTH) && (iopd_idx < 8); iopd_idx = iopd_idx + 1) 1.412 + begin 1.413 + always @(posedge CLK_I or posedge RST_I) 1.414 + if (RST_I) 1.415 + begin 1.416 + PIO_DATAI[iopd_idx] <= #UDLY 0; 1.417 + PIO_DATAO[iopd_idx] <= #UDLY 0; 1.418 + end 1.419 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000) 1.420 + PIO_DATAI[iopd_idx] <= #UDLY PIO_BOTH_IN[iopd_idx]; 1.421 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000) 1.422 + PIO_DATAO[iopd_idx] <= #UDLY GPIO_DAT_I_switch[iopd_idx]; 1.423 + end 1.424 + if (OUTPUT_WIDTH > 8) begin 1.425 + genvar jopd_idx; 1.426 + for (jopd_idx = 8; (jopd_idx < OUTPUT_WIDTH) && (jopd_idx < 16); jopd_idx = jopd_idx + 1) 1.427 + begin 1.428 + always @(posedge CLK_I or posedge RST_I) 1.429 + if (RST_I) 1.430 + begin 1.431 + PIO_DATAI[jopd_idx] <= #UDLY 0; 1.432 + PIO_DATAO[jopd_idx] <= #UDLY 0; 1.433 + end 1.434 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001) 1.435 + PIO_DATAI[jopd_idx] <= #UDLY PIO_BOTH_IN[jopd_idx]; 1.436 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001) 1.437 + PIO_DATAO[jopd_idx] <= #UDLY GPIO_DAT_I_switch[jopd_idx-8]; 1.438 + end 1.439 + end 1.440 + if (OUTPUT_WIDTH > 16) begin 1.441 + genvar kopd_idx; 1.442 + for (kopd_idx = 16; (kopd_idx < OUTPUT_WIDTH) && (kopd_idx < 24); kopd_idx = kopd_idx + 1) 1.443 + begin 1.444 + always @(posedge CLK_I or posedge RST_I) 1.445 + if (RST_I) 1.446 + begin 1.447 + PIO_DATAI[kopd_idx] <= #UDLY 0; 1.448 + PIO_DATAO[kopd_idx] <= #UDLY 0; 1.449 + end 1.450 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010) 1.451 + PIO_DATAI[kopd_idx] <= #UDLY PIO_BOTH_IN[kopd_idx]; 1.452 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010) 1.453 + PIO_DATAO[kopd_idx] <= #UDLY GPIO_DAT_I_switch[kopd_idx-16]; 1.454 + end 1.455 + end 1.456 + if (OUTPUT_WIDTH > 24) begin 1.457 + genvar lopd_idx; 1.458 + for (lopd_idx = 24; (lopd_idx < OUTPUT_WIDTH) && (lopd_idx < 32); lopd_idx = lopd_idx + 1) 1.459 + begin 1.460 + always @(posedge CLK_I or posedge RST_I) 1.461 + if (RST_I) 1.462 + begin 1.463 + PIO_DATAI[lopd_idx] <= #UDLY 0; 1.464 + PIO_DATAO[lopd_idx] <= #UDLY 0; 1.465 + end 1.466 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011) 1.467 + PIO_DATAI[lopd_idx] <= #UDLY PIO_BOTH_IN[lopd_idx]; 1.468 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011) 1.469 + PIO_DATAO[lopd_idx] <= #UDLY GPIO_DAT_I_switch[lopd_idx-24]; 1.470 + end 1.471 + end 1.472 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.473 + 1.474 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.475 + genvar iopd_idx; 1.476 + for (iopd_idx = 0; (iopd_idx < OUTPUT_WIDTH) && (iopd_idx < 8); iopd_idx = iopd_idx + 1) 1.477 + begin 1.478 + always @(posedge CLK_I or posedge RST_I) 1.479 + if (RST_I) 1.480 + begin 1.481 + PIO_DATAI[iopd_idx] <= #UDLY 0; 1.482 + PIO_DATAO[iopd_idx] <= #UDLY 0; 1.483 + end 1.484 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[0]) 1.485 + PIO_DATAI[iopd_idx] <= #UDLY PIO_BOTH_IN[iopd_idx]; 1.486 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[0]) 1.487 + PIO_DATAO[iopd_idx] <= #UDLY GPIO_DAT_I_switch[iopd_idx]; 1.488 + end 1.489 + if (OUTPUT_WIDTH > 8) begin 1.490 + genvar jopd_idx; 1.491 + for (jopd_idx = 8; (jopd_idx < OUTPUT_WIDTH) && (jopd_idx < 16); jopd_idx = jopd_idx + 1) 1.492 + begin 1.493 + always @(posedge CLK_I or posedge RST_I) 1.494 + if (RST_I) 1.495 + begin 1.496 + PIO_DATAI[jopd_idx] <= #UDLY 0; 1.497 + PIO_DATAO[jopd_idx] <= #UDLY 0; 1.498 + end 1.499 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[1]) 1.500 + PIO_DATAI[jopd_idx] <= #UDLY PIO_BOTH_IN[jopd_idx]; 1.501 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[1]) 1.502 + PIO_DATAO[jopd_idx] <= #UDLY GPIO_DAT_I_switch[jopd_idx]; 1.503 + end 1.504 + end 1.505 + if (OUTPUT_WIDTH > 16) begin 1.506 + genvar kopd_idx; 1.507 + for (kopd_idx = 16; (kopd_idx < OUTPUT_WIDTH) && (kopd_idx < 24); kopd_idx = kopd_idx + 1) 1.508 + begin 1.509 + always @(posedge CLK_I or posedge RST_I) 1.510 + if (RST_I) 1.511 + begin 1.512 + PIO_DATAI[kopd_idx] <= #UDLY 0; 1.513 + PIO_DATAO[kopd_idx] <= #UDLY 0; 1.514 + end 1.515 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[2]) 1.516 + PIO_DATAI[kopd_idx] <= #UDLY PIO_BOTH_IN[kopd_idx]; 1.517 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[2]) 1.518 + PIO_DATAO[kopd_idx] <= #UDLY GPIO_DAT_I_switch[kopd_idx]; 1.519 + end 1.520 + end 1.521 + if (OUTPUT_WIDTH > 24) begin 1.522 + genvar lopd_idx; 1.523 + for (lopd_idx = 24; (lopd_idx < OUTPUT_WIDTH) && (lopd_idx < 32); lopd_idx = lopd_idx + 1) 1.524 + begin 1.525 + always @(posedge CLK_I or posedge RST_I) 1.526 + if (RST_I) 1.527 + begin 1.528 + PIO_DATAI[lopd_idx] <= #UDLY 0; 1.529 + PIO_DATAO[lopd_idx] <= #UDLY 0; 1.530 + end 1.531 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[3]) 1.532 + PIO_DATAI[lopd_idx] <= #UDLY PIO_BOTH_IN[lopd_idx]; 1.533 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[3]) 1.534 + PIO_DATAO[lopd_idx] <= #UDLY GPIO_DAT_I_switch[lopd_idx]; 1.535 + end 1.536 + end 1.537 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.538 + 1.539 + assign PIO_BOTH_OUT = PIO_DATAO[OUTPUT_WIDTH-1:0]; 1.540 + end 1.541 + endgenerate 1.542 + 1.543 + assign PIO_DATA_RE_EN = GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b00); 1.544 + 1.545 + assign PIO_TRI_RE_EN = GPIO_STB_I && GPIO_ACK_O && !GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b01); 1.546 + 1.547 + assign IRQ_MASK_RE_EN = GPIO_STB_I && GPIO_ACK_O && !GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b10); 1.548 + 1.549 + assign PIO_DATA_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b00); 1.550 + generate 1.551 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.552 + assign PIO_DATA_WR_EN_0 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000; 1.553 + assign PIO_DATA_WR_EN_1 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001; 1.554 + assign PIO_DATA_WR_EN_2 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010; 1.555 + assign PIO_DATA_WR_EN_3 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011; 1.556 + end 1.557 + endgenerate 1.558 + 1.559 + assign PIO_TRI_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (GPIO_ADR_I[3:2] == 4'b01); 1.560 + generate 1.561 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.562 + assign PIO_TRI_WR_EN_0 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0100; 1.563 + assign PIO_TRI_WR_EN_1 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0101; 1.564 + assign PIO_TRI_WR_EN_2 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0110; 1.565 + assign PIO_TRI_WR_EN_3 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0111; 1.566 + end 1.567 + endgenerate 1.568 + 1.569 + assign IRQ_MASK_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b10); 1.570 + generate 1.571 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.572 + assign IRQ_MASK_WR_EN_0 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1000; 1.573 + assign IRQ_MASK_WR_EN_1 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1001; 1.574 + assign IRQ_MASK_WR_EN_2 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1010; 1.575 + assign IRQ_MASK_WR_EN_3 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1011; 1.576 + end 1.577 + endgenerate 1.578 + 1.579 + assign EDGE_CAP_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b11); 1.580 + generate 1.581 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.582 + assign EDGE_CAP_WR_EN_0 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1100; 1.583 + assign EDGE_CAP_WR_EN_1 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1101; 1.584 + assign EDGE_CAP_WR_EN_2 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1110; 1.585 + assign EDGE_CAP_WR_EN_3 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1111; 1.586 + end 1.587 + endgenerate 1.588 + 1.589 + generate 1.590 + 1.591 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.592 + 1.593 + genvar iti; 1.594 + for (iti = 0; (iti < DATA_WIDTH) && (iti < 8); iti = iti + 1) 1.595 + begin : itio_inst 1.596 + TRI_PIO 1.597 + #(.DATA_WIDTH(1), 1.598 + .IRQ_MODE(IRQ_MODE), 1.599 + .LEVEL(LEVEL), 1.600 + .EDGE(EDGE), 1.601 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.602 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.603 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.604 + TP 1.605 + (.CLK_I(CLK_I), 1.606 + .RST_I(RST_I), 1.607 + .DAT_I(GPIO_DAT_I_switch[iti]), 1.608 + .DAT_O(tpio_out[iti]), 1.609 + .PIO_IO(PIO_IO[iti]), 1.610 + .IRQ_O(IRQ_TRI_TEMP[iti]), 1.611 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN_0), 1.612 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.613 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN_0), 1.614 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.615 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_0), 1.616 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.617 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_0)); 1.618 + end 1.619 + if (DATA_WIDTH > 8) begin 1.620 + genvar jti; 1.621 + for (jti = 8; (jti < DATA_WIDTH) && (jti < 16); jti = jti + 1) 1.622 + begin : jtio_inst 1.623 + TRI_PIO 1.624 + #(.DATA_WIDTH(1), 1.625 + .IRQ_MODE(IRQ_MODE), 1.626 + .LEVEL(LEVEL), 1.627 + .EDGE(EDGE), 1.628 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.629 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.630 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.631 + TP 1.632 + (.CLK_I(CLK_I), 1.633 + .RST_I(RST_I), 1.634 + .DAT_I(GPIO_DAT_I_switch[jti-8]), 1.635 + .DAT_O(tpio_out[jti]), 1.636 + .PIO_IO(PIO_IO[jti]), 1.637 + .IRQ_O(IRQ_TRI_TEMP[jti]), 1.638 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN_1), 1.639 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.640 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN_1), 1.641 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.642 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_1), 1.643 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.644 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_1)); 1.645 + end 1.646 + end 1.647 + if (DATA_WIDTH > 16) begin 1.648 + genvar kti; 1.649 + for (kti = 16; (kti < DATA_WIDTH) && (kti < 24); kti = kti + 1) 1.650 + begin : ktio_inst 1.651 + TRI_PIO 1.652 + #(.DATA_WIDTH(1), 1.653 + .IRQ_MODE(IRQ_MODE), 1.654 + .LEVEL(LEVEL), 1.655 + .EDGE(EDGE), 1.656 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.657 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.658 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.659 + TP 1.660 + (.CLK_I(CLK_I), 1.661 + .RST_I(RST_I), 1.662 + .DAT_I(GPIO_DAT_I_switch[kti-16]), 1.663 + .DAT_O(tpio_out[kti]), 1.664 + .PIO_IO(PIO_IO[kti]), 1.665 + .IRQ_O(IRQ_TRI_TEMP[kti]), 1.666 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN_2), 1.667 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.668 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN_2), 1.669 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.670 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_2), 1.671 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.672 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_2)); 1.673 + end 1.674 + end 1.675 + if (DATA_WIDTH > 24) begin 1.676 + genvar lti; 1.677 + for (lti = 24; (lti < DATA_WIDTH) && (lti < 32); lti = lti + 1) 1.678 + begin : ltio_inst 1.679 + TRI_PIO 1.680 + #(.DATA_WIDTH(1), 1.681 + .IRQ_MODE(IRQ_MODE), 1.682 + .LEVEL(LEVEL), 1.683 + .EDGE(EDGE), 1.684 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.685 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.686 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.687 + TP 1.688 + (.CLK_I(CLK_I), 1.689 + .RST_I(RST_I), 1.690 + .DAT_I(GPIO_DAT_I_switch[lti-24]), 1.691 + .DAT_O(tpio_out[lti]), 1.692 + .PIO_IO(PIO_IO[lti]), 1.693 + .IRQ_O(IRQ_TRI_TEMP[lti]), 1.694 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN_3), 1.695 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.696 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN_3), 1.697 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.698 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_3), 1.699 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.700 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_3)); 1.701 + end 1.702 + end 1.703 + 1.704 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.705 + 1.706 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.707 + 1.708 + genvar iti; 1.709 + for (iti = 0; (iti < DATA_WIDTH) && (iti < 8); iti = iti + 1) 1.710 + begin : itio_inst 1.711 + TRI_PIO 1.712 + #(.DATA_WIDTH(1), 1.713 + .IRQ_MODE(IRQ_MODE), 1.714 + .LEVEL(LEVEL), 1.715 + .EDGE(EDGE), 1.716 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.717 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.718 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.719 + TP 1.720 + (.CLK_I(CLK_I), 1.721 + .RST_I(RST_I), 1.722 + .DAT_I(GPIO_DAT_I_switch[iti]), 1.723 + .DAT_O(tpio_out[iti]), 1.724 + .PIO_IO(PIO_IO[iti]), 1.725 + .IRQ_O(IRQ_TRI_TEMP[iti]), 1.726 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[0]), 1.727 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.728 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[0]), 1.729 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.730 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[0]), 1.731 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.732 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[0])); 1.733 + end 1.734 + if (DATA_WIDTH > 8) begin 1.735 + genvar jti; 1.736 + for (jti = 8; (jti < DATA_WIDTH) && (jti < 16); jti = jti + 1) 1.737 + begin : jtio_inst 1.738 + TRI_PIO 1.739 + #(.DATA_WIDTH(1), 1.740 + .IRQ_MODE(IRQ_MODE), 1.741 + .LEVEL(LEVEL), 1.742 + .EDGE(EDGE), 1.743 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.744 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.745 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.746 + TP 1.747 + (.CLK_I(CLK_I), 1.748 + .RST_I(RST_I), 1.749 + .DAT_I(GPIO_DAT_I_switch[jti]), 1.750 + .DAT_O(tpio_out[jti]), 1.751 + .PIO_IO(PIO_IO[jti]), 1.752 + .IRQ_O(IRQ_TRI_TEMP[jti]), 1.753 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[1]), 1.754 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.755 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[1]), 1.756 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.757 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[1]), 1.758 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.759 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[1])); 1.760 + end 1.761 + end 1.762 + if (DATA_WIDTH > 16) begin 1.763 + genvar kti; 1.764 + for (kti = 16; (kti < DATA_WIDTH) && (kti < 24); kti = kti + 1) 1.765 + begin : ktio_inst 1.766 + TRI_PIO 1.767 + #(.DATA_WIDTH(1), 1.768 + .IRQ_MODE(IRQ_MODE), 1.769 + .LEVEL(LEVEL), 1.770 + .EDGE(EDGE), 1.771 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.772 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.773 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.774 + TP 1.775 + (.CLK_I(CLK_I), 1.776 + .RST_I(RST_I), 1.777 + .DAT_I(GPIO_DAT_I_switch[kti]), 1.778 + .DAT_O(tpio_out[kti]), 1.779 + .PIO_IO(PIO_IO[kti]), 1.780 + .IRQ_O(IRQ_TRI_TEMP[kti]), 1.781 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[2]), 1.782 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.783 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[2]), 1.784 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.785 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[2]), 1.786 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.787 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[2])); 1.788 + end 1.789 + end 1.790 + if (DATA_WIDTH > 24) begin 1.791 + genvar lti; 1.792 + for (lti = 24; (lti < DATA_WIDTH) && (lti < 32); lti = lti + 1) 1.793 + begin : ltio_inst 1.794 + TRI_PIO 1.795 + #(.DATA_WIDTH(1), 1.796 + .IRQ_MODE(IRQ_MODE), 1.797 + .LEVEL(LEVEL), 1.798 + .EDGE(EDGE), 1.799 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.800 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.801 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.802 + TP 1.803 + (.CLK_I(CLK_I), 1.804 + .RST_I(RST_I), 1.805 + .DAT_I(GPIO_DAT_I_switch[lti]), 1.806 + .DAT_O(tpio_out[lti]), 1.807 + .PIO_IO(PIO_IO[lti]), 1.808 + .IRQ_O(IRQ_TRI_TEMP[lti]), 1.809 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[3]), 1.810 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.811 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[3]), 1.812 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.813 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[3]), 1.814 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.815 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[3])); 1.816 + end 1.817 + end 1.818 + 1.819 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.820 + 1.821 + endgenerate 1.822 + 1.823 + 1.824 + wire read_addr_0, read_addr_4, read_addr_8, read_addr_C; 1.825 assign read_addr_0 = (ADR_0 & GPIO_STB_I & ~GPIO_WE_I) ; 1.826 assign read_addr_4 = (ADR_4 & GPIO_STB_I & ~GPIO_WE_I) ; 1.827 assign read_addr_8 = (IRQ_MODE == 1 && (ADR_8 & GPIO_STB_I & ~GPIO_WE_I)); 1.828 - assign read_addr_C = (IRQ_MODE == 1 && (ADR_C & GPIO_STB_I & ~GPIO_WE_I)); 1.829 - 1.830 - always @(posedge CLK_I or posedge RST_I) 1.831 - if(RST_I) 1.832 - GPIO_ACK_O <= #UDLY 1'b0; 1.833 - else if( GPIO_STB_I && !GPIO_ACK_O) 1.834 - GPIO_ACK_O <= #UDLY 1'b1; 1.835 - else 1.836 - GPIO_ACK_O <= #UDLY 1'b0; 1.837 - 1.838 - generate 1.839 - if (INPUT_PORTS_ONLY == 1) begin 1.840 - always @(posedge CLK_I or posedge RST_I) 1.841 - if (RST_I) 1.842 - PIO_DATA <= #UDLY 0; 1.843 - else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I == 4'b1111) 1.844 - PIO_DATA <= #UDLY PIO_IN; 1.845 - end 1.846 - endgenerate 1.847 - 1.848 - generate 1.849 - if (OUTPUT_PORTS_ONLY == 1) begin 1.850 - always @(posedge CLK_I or posedge RST_I) 1.851 - if (RST_I) 1.852 - PIO_DATA <= #UDLY 0; 1.853 - else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I == 4'b1111) 1.854 - PIO_DATA <= #UDLY GPIO_DAT_I[DATA_WIDTH-1:0]; 1.855 - 1.856 - assign PIO_OUT = PIO_DATA; 1.857 - end 1.858 - endgenerate 1.859 + assign read_addr_C = (IRQ_MODE == 1 && (ADR_C & GPIO_STB_I & ~GPIO_WE_I)); 1.860 1.861 - generate 1.862 - if (BOTH_INPUT_AND_OUTPUT == 1) begin 1.863 - always @(posedge CLK_I or posedge RST_I) 1.864 - if (RST_I) begin 1.865 - PIO_DATAI <= #UDLY 0; 1.866 - PIO_DATAO <= #UDLY 0; 1.867 - end else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111) 1.868 - PIO_DATAI <= #UDLY PIO_BOTH_IN; 1.869 - else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111) 1.870 - PIO_DATAO <= #UDLY GPIO_DAT_I[OUTPUT_WIDTH-1:0]; 1.871 - 1.872 - assign PIO_BOTH_OUT = PIO_DATAO[OUTPUT_WIDTH-1:0]; 1.873 - end 1.874 - endgenerate 1.875 - 1.876 - assign PIO_DATA_RE_EN = GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111; 1.877 - assign PIO_TRI_RE_EN = GPIO_STB_I && GPIO_ACK_O && !GPIO_WE_I && (ADR_4 == 1'b1) && GPIO_SEL_I == 4'b1111; 1.878 - assign IRQ_MASK_RE_EN = GPIO_STB_I && GPIO_ACK_O && !GPIO_WE_I && (ADR_8 == 1'b1) && GPIO_SEL_I == 4'b1111; 1.879 - assign PIO_DATA_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111; 1.880 - assign PIO_TRI_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (ADR_4 == 1'b1) && GPIO_SEL_I == 4'b1111; 1.881 - assign IRQ_MASK_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (ADR_8 == 1'b1) && GPIO_SEL_I == 4'b1111; 1.882 - assign EDGE_CAP_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (ADR_C == 1'b1) && GPIO_SEL_I == 4'b1111; 1.883 + wire read_byte_0, read_byte_1, read_byte_2, read_byte_3; 1.884 + wire read_byte_4, read_byte_5, read_byte_6, read_byte_7; 1.885 + wire read_byte_8, read_byte_9, read_byte_A, read_byte_B; 1.886 + wire read_byte_C, read_byte_D, read_byte_E, read_byte_F; 1.887 + assign read_byte_0 = ((GPIO_ADR_I[3:0] == 4'b0000) & GPIO_STB_I & ~GPIO_WE_I) ; 1.888 + assign read_byte_1 = ((GPIO_ADR_I[3:0] == 4'b0001) & GPIO_STB_I & ~GPIO_WE_I) ; 1.889 + assign read_byte_2 = ((GPIO_ADR_I[3:0] == 4'b0010) & GPIO_STB_I & ~GPIO_WE_I) ; 1.890 + assign read_byte_3 = ((GPIO_ADR_I[3:0] == 4'b0011) & GPIO_STB_I & ~GPIO_WE_I) ; 1.891 + assign read_byte_4 = ((GPIO_ADR_I[3:0] == 4'b0100) & GPIO_STB_I & ~GPIO_WE_I) ; 1.892 + assign read_byte_5 = ((GPIO_ADR_I[3:0] == 4'b0101) & GPIO_STB_I & ~GPIO_WE_I) ; 1.893 + assign read_byte_6 = ((GPIO_ADR_I[3:0] == 4'b0110) & GPIO_STB_I & ~GPIO_WE_I) ; 1.894 + assign read_byte_7 = ((GPIO_ADR_I[3:0] == 4'b0111) & GPIO_STB_I & ~GPIO_WE_I) ; 1.895 + assign read_byte_8 = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1000) & GPIO_STB_I & ~GPIO_WE_I)); 1.896 + assign read_byte_9 = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1001) & GPIO_STB_I & ~GPIO_WE_I)); 1.897 + assign read_byte_A = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1010) & GPIO_STB_I & ~GPIO_WE_I)); 1.898 + assign read_byte_B = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1011) & GPIO_STB_I & ~GPIO_WE_I)); 1.899 + assign read_byte_C = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1100) & GPIO_STB_I & ~GPIO_WE_I)); 1.900 + assign read_byte_D = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1101) & GPIO_STB_I & ~GPIO_WE_I)); 1.901 + assign read_byte_E = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1110) & GPIO_STB_I & ~GPIO_WE_I)); 1.902 + assign read_byte_F = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1111) & GPIO_STB_I & ~GPIO_WE_I)); 1.903 1.904 generate 1.905 - genvar ti; 1.906 - for (ti = 0 ; ti < DATA_WIDTH; ti = ti + 1) 1.907 - begin : tio_inst 1.908 - TRI_PIO #(.DATA_WIDTH(DATA_WIDTH), 1.909 - .IRQ_MODE(IRQ_MODE), 1.910 - .LEVEL(LEVEL), 1.911 - .EDGE(EDGE), 1.912 - .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.913 - .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.914 - .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.915 - TP (.CLK_I(CLK_I), 1.916 - .RST_I(RST_I), 1.917 - .DAT_I(GPIO_DAT_I[ti]), 1.918 - .DAT_O(tpio_out[ti]), 1.919 - .PIO_IO(PIO_IO[ti]), 1.920 - .IRQ_O(IRQ_TRI_TEMP[ti]), 1.921 - .PIO_TRI_WR_EN(PIO_TRI_WR_EN), 1.922 - .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.923 - .PIO_DATA_WR_EN(PIO_DATA_WR_EN), 1.924 - .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.925 - .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN), 1.926 - .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.927 - .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN)); 1.928 - end 1.929 - endgenerate 1.930 1.931 - generate 1.932 - if (INPUT_PORTS_ONLY == 1) 1.933 - assign GPIO_DAT_O = read_addr_0 ? PIO_DATA : 1.934 - read_addr_8 ? IRQ_MASK : 1.935 - read_addr_C ? EDGE_CAPTURE : 1.936 - 0; 1.937 - else if (BOTH_INPUT_AND_OUTPUT == 1) 1.938 - assign GPIO_DAT_O = read_addr_0 ? PIO_DATAI : 1.939 - read_addr_8 ? IRQ_MASK_BOTH : 1.940 - read_addr_C ? EDGE_CAPTURE_BOTH : 1.941 - 0; 1.942 - else if (TRISTATE_PORTS == 1) 1.943 - assign GPIO_DAT_O = read_addr_0 ? tpio_out : 1.944 - read_addr_4 ? tpio_out : 1.945 - read_addr_8 ? tpio_out : 1.946 - read_addr_C ? IRQ_TRI_TEMP : 1.947 - 0; 1.948 - else 1.949 - assign GPIO_DAT_O = 0; 1.950 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.951 + 1.952 + if (INPUT_PORTS_ONLY == 1) begin 1.953 + if (DATA_WIDTH > 24) 1.954 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[ 7: 0] : 1.955 + read_byte_1 ? PIO_DATA[15: 8] : 1.956 + read_byte_2 ? PIO_DATA[23:16] : 1.957 + read_byte_3 ? PIO_DATA[DATA_WIDTH-1:24] : 1.958 + read_byte_8 ? IRQ_MASK[ 7: 0] : 1.959 + read_byte_9 ? IRQ_MASK[15: 8] : 1.960 + read_byte_A ? IRQ_MASK[23:16] : 1.961 + read_byte_B ? IRQ_MASK[DATA_WIDTH-1:24] : 1.962 + read_byte_C ? EDGE_CAPTURE[ 7: 0] : 1.963 + read_byte_D ? EDGE_CAPTURE[15: 8] : 1.964 + read_byte_E ? EDGE_CAPTURE[23:16] : 1.965 + read_byte_F ? EDGE_CAPTURE[DATA_WIDTH-1:24] : 1.966 + 0; 1.967 + else if (DATA_WIDTH > 16) 1.968 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[ 7: 0] : 1.969 + read_byte_1 ? PIO_DATA[15: 8] : 1.970 + read_byte_2 ? PIO_DATA[DATA_WIDTH-1:16] : 1.971 + read_byte_3 ? 8'h00 : 1.972 + read_byte_8 ? IRQ_MASK[ 7: 0] : 1.973 + read_byte_9 ? IRQ_MASK[15: 8] : 1.974 + read_byte_A ? IRQ_MASK[DATA_WIDTH-1:16] : 1.975 + read_byte_B ? 8'h00 : 1.976 + read_byte_C ? EDGE_CAPTURE[ 7: 0] : 1.977 + read_byte_D ? EDGE_CAPTURE[15: 8] : 1.978 + read_byte_E ? EDGE_CAPTURE[DATA_WIDTH-1:16] : 1.979 + read_byte_F ? 8'h00 : 1.980 + 0; 1.981 + else if (DATA_WIDTH > 8) 1.982 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[ 7: 0] : 1.983 + read_byte_1 ? PIO_DATA[DATA_WIDTH-1: 8] : 1.984 + read_byte_2 ? 8'h00 : 1.985 + read_byte_3 ? 8'h00 : 1.986 + read_byte_8 ? IRQ_MASK[ 7: 0] : 1.987 + read_byte_9 ? IRQ_MASK[DATA_WIDTH-1: 8] : 1.988 + read_byte_A ? 8'h00 : 1.989 + read_byte_B ? 8'h00 : 1.990 + read_byte_C ? EDGE_CAPTURE[ 7: 0] : 1.991 + read_byte_D ? EDGE_CAPTURE[DATA_WIDTH-1: 8] : 1.992 + read_byte_E ? 8'h00 : 1.993 + read_byte_F ? 8'h00 : 1.994 + 0; 1.995 + else 1.996 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[DATA_WIDTH-1: 0] : 1.997 + read_byte_1 ? 8'h00 : 1.998 + read_byte_2 ? 8'h00 : 1.999 + read_byte_3 ? 8'h00 : 1.1000 + read_byte_8 ? IRQ_MASK[DATA_WIDTH-1: 0] : 1.1001 + read_byte_9 ? 8'h00 : 1.1002 + read_byte_A ? 8'h00 : 1.1003 + read_byte_B ? 8'h00 : 1.1004 + read_byte_C ? EDGE_CAPTURE[DATA_WIDTH-1: 0] : 1.1005 + read_byte_D ? 8'h00 : 1.1006 + read_byte_E ? 8'h00 : 1.1007 + read_byte_F ? 8'h00 : 1.1008 + 0; 1.1009 + end 1.1010 + else if (BOTH_INPUT_AND_OUTPUT == 1) begin 1.1011 + if (INPUT_WIDTH > 24) 1.1012 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[ 7: 0] : 1.1013 + read_byte_1 ? PIO_DATAI[15: 8] : 1.1014 + read_byte_2 ? PIO_DATAI[23:16] : 1.1015 + read_byte_3 ? PIO_DATAI[INPUT_WIDTH-1:24] : 1.1016 + read_byte_8 ? IRQ_MASK_BOTH[ 7: 0] : 1.1017 + read_byte_9 ? IRQ_MASK_BOTH[15: 8] : 1.1018 + read_byte_A ? IRQ_MASK_BOTH[23:16] : 1.1019 + read_byte_B ? IRQ_MASK_BOTH[INPUT_WIDTH-1:24] : 1.1020 + read_byte_C ? EDGE_CAPTURE_BOTH[ 7: 0] : 1.1021 + read_byte_D ? EDGE_CAPTURE_BOTH[15: 8] : 1.1022 + read_byte_E ? EDGE_CAPTURE_BOTH[23:16] : 1.1023 + read_byte_F ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1:24] : 1.1024 + 0; 1.1025 + else if (INPUT_WIDTH > 16) 1.1026 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[ 7: 0] : 1.1027 + read_byte_1 ? PIO_DATAI[15: 8] : 1.1028 + read_byte_2 ? PIO_DATAI[INPUT_WIDTH-1:16] : 1.1029 + read_byte_3 ? 8'h00 : 1.1030 + read_byte_8 ? IRQ_MASK_BOTH[ 7: 0] : 1.1031 + read_byte_9 ? IRQ_MASK_BOTH[15: 8] : 1.1032 + read_byte_A ? IRQ_MASK_BOTH[INPUT_WIDTH-1:16] : 1.1033 + read_byte_B ? 8'h00 : 1.1034 + read_byte_C ? EDGE_CAPTURE_BOTH[ 7: 0] : 1.1035 + read_byte_D ? EDGE_CAPTURE_BOTH[15: 8] : 1.1036 + read_byte_E ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1:16] : 1.1037 + read_byte_F ? 8'h00 : 1.1038 + 0; 1.1039 + else if (INPUT_WIDTH > 8) 1.1040 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[ 7: 0] : 1.1041 + read_byte_1 ? PIO_DATAI[INPUT_WIDTH-1: 8] : 1.1042 + read_byte_2 ? 8'h00 : 1.1043 + read_byte_3 ? 8'h00 : 1.1044 + read_byte_8 ? IRQ_MASK_BOTH[ 7: 0] : 1.1045 + read_byte_9 ? IRQ_MASK_BOTH[INPUT_WIDTH-1: 8] : 1.1046 + read_byte_A ? 8'h00 : 1.1047 + read_byte_B ? 8'h00 : 1.1048 + read_byte_C ? EDGE_CAPTURE_BOTH[ 7: 0] : 1.1049 + read_byte_D ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1: 8] : 1.1050 + read_byte_E ? 8'h00 : 1.1051 + read_byte_F ? 8'h00 : 1.1052 + 0; 1.1053 + else 1.1054 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[INPUT_WIDTH-1: 0] : 1.1055 + read_byte_1 ? 8'h00 : 1.1056 + read_byte_2 ? 8'h00 : 1.1057 + read_byte_3 ? 8'h00 : 1.1058 + read_byte_8 ? IRQ_MASK_BOTH[INPUT_WIDTH-1: 0] : 1.1059 + read_byte_9 ? 8'h00 : 1.1060 + read_byte_A ? 8'h00 : 1.1061 + read_byte_B ? 8'h00 : 1.1062 + read_byte_C ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1: 0] : 1.1063 + read_byte_D ? 8'h00 : 1.1064 + read_byte_E ? 8'h00 : 1.1065 + read_byte_F ? 8'h00 : 1.1066 + 0; 1.1067 + end 1.1068 + else if (TRISTATE_PORTS == 1) begin 1.1069 + if (DATA_WIDTH > 24) 1.1070 + assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[ 7: 0] : 1.1071 + read_byte_1 ? tpio_out[15: 8] : 1.1072 + read_byte_2 ? tpio_out[23:16] : 1.1073 + read_byte_3 ? tpio_out[DATA_WIDTH-1:24] : 1.1074 + read_byte_4 ? tpio_out[ 7: 0] : 1.1075 + read_byte_5 ? tpio_out[15: 8] : 1.1076 + read_byte_6 ? tpio_out[23:16] : 1.1077 + read_byte_7 ? tpio_out[DATA_WIDTH-1:24] : 1.1078 + read_byte_8 ? tpio_out[ 7: 0] : 1.1079 + read_byte_9 ? tpio_out[15: 8] : 1.1080 + read_byte_A ? tpio_out[23:16] : 1.1081 + read_byte_B ? tpio_out[DATA_WIDTH-1:24] : 1.1082 + read_byte_C ? IRQ_TRI_TEMP[ 7: 0] : 1.1083 + read_byte_D ? IRQ_TRI_TEMP[15: 8] : 1.1084 + read_byte_E ? IRQ_TRI_TEMP[23:16] : 1.1085 + read_byte_F ? IRQ_TRI_TEMP[DATA_WIDTH-1:24] : 1.1086 + 0; 1.1087 + else if (DATA_WIDTH > 16) 1.1088 + assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[ 7: 0] : 1.1089 + read_byte_1 ? tpio_out[15: 8] : 1.1090 + read_byte_2 ? tpio_out[DATA_WIDTH-1:16] : 1.1091 + read_byte_3 ? 8'h00 : 1.1092 + read_byte_4 ? tpio_out[ 7: 0] : 1.1093 + read_byte_5 ? tpio_out[15: 8] : 1.1094 + read_byte_6 ? tpio_out[DATA_WIDTH-1:16] : 1.1095 + read_byte_7 ? 8'h00 : 1.1096 + read_byte_8 ? tpio_out[ 7: 0] : 1.1097 + read_byte_9 ? tpio_out[15: 8] : 1.1098 + read_byte_A ? tpio_out[DATA_WIDTH-1:16] : 1.1099 + read_byte_B ? 8'h00 : 1.1100 + read_byte_C ? IRQ_TRI_TEMP[ 7: 0] : 1.1101 + read_byte_D ? IRQ_TRI_TEMP[15: 8] : 1.1102 + read_byte_E ? IRQ_TRI_TEMP[DATA_WIDTH-1:16] : 1.1103 + read_byte_F ? 8'h00 : 1.1104 + 0; 1.1105 + else if (DATA_WIDTH > 8) 1.1106 + assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[ 7: 0] : 1.1107 + read_byte_1 ? tpio_out[DATA_WIDTH-1: 8] : 1.1108 + read_byte_2 ? 8'h00 : 1.1109 + read_byte_3 ? 8'h00 : 1.1110 + read_byte_4 ? tpio_out[ 7: 0] : 1.1111 + read_byte_5 ? tpio_out[DATA_WIDTH-1: 8] : 1.1112 + read_byte_6 ? 8'h00 : 1.1113 + read_byte_7 ? 8'h00 : 1.1114 + read_byte_8 ? tpio_out[ 7: 0] : 1.1115 + read_byte_9 ? tpio_out[DATA_WIDTH-1: 8] : 1.1116 + read_byte_A ? 8'h00 : 1.1117 + read_byte_B ? 8'h00 : 1.1118 + read_byte_C ? IRQ_TRI_TEMP[ 7: 0] : 1.1119 + read_byte_D ? IRQ_TRI_TEMP[DATA_WIDTH-1: 8] : 1.1120 + read_byte_E ? 8'h00 : 1.1121 + read_byte_F ? 8'h00 : 1.1122 + 0; 1.1123 + else 1.1124 + assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[DATA_WIDTH-1: 0] : 1.1125 + read_byte_1 ? 8'h00 : 1.1126 + read_byte_2 ? 8'h00 : 1.1127 + read_byte_3 ? 8'h00 : 1.1128 + read_byte_4 ? tpio_out[DATA_WIDTH-1: 0] : 1.1129 + read_byte_5 ? 8'h00 : 1.1130 + read_byte_6 ? 8'h00 : 1.1131 + read_byte_7 ? 8'h00 : 1.1132 + read_byte_8 ? tpio_out[DATA_WIDTH-1: 0] : 1.1133 + read_byte_9 ? 8'h00 : 1.1134 + read_byte_A ? 8'h00 : 1.1135 + read_byte_B ? 8'h00 : 1.1136 + read_byte_C ? IRQ_TRI_TEMP[DATA_WIDTH-1: 0] : 1.1137 + read_byte_D ? 8'h00 : 1.1138 + read_byte_E ? 8'h00 : 1.1139 + read_byte_F ? 8'h00 : 1.1140 + 0; 1.1141 + end 1.1142 + else 1.1143 + assign GPIO_DAT_O_switch = 0; 1.1144 + 1.1145 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.1146 + 1.1147 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.1148 + 1.1149 + if (INPUT_PORTS_ONLY == 1) 1.1150 + assign GPIO_DAT_O_switch = read_addr_0 ? PIO_DATA : 1.1151 + read_addr_8 ? IRQ_MASK : 1.1152 + read_addr_C ? EDGE_CAPTURE : 1.1153 + 0; 1.1154 + else if (BOTH_INPUT_AND_OUTPUT == 1) 1.1155 + assign GPIO_DAT_O_switch = read_addr_0 ? PIO_DATAI : 1.1156 + read_addr_8 ? IRQ_MASK_BOTH : 1.1157 + read_addr_C ? EDGE_CAPTURE_BOTH : 1.1158 + 0; 1.1159 + else if (TRISTATE_PORTS == 1) 1.1160 + assign GPIO_DAT_O_switch = read_addr_0 ? tpio_out : 1.1161 + read_addr_4 ? tpio_out : 1.1162 + read_addr_8 ? tpio_out : 1.1163 + read_addr_C ? IRQ_TRI_TEMP : 1.1164 + 0; 1.1165 + else 1.1166 + assign GPIO_DAT_O_switch = 0; 1.1167 + 1.1168 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.1169 + 1.1170 endgenerate 1.1171 1.1172 -//----------------------------------------------------------------------------- 1.1173 -//-------------------------------IRQ Generation-------------------------------- 1.1174 -//----------------------------------------------------------------------------- 1.1175 + 1.1176 + 1.1177 + //----------------------------------------------------------------------------- 1.1178 + //-------------------------------IRQ Generation-------------------------------- 1.1179 + //----------------------------------------------------------------------------- 1.1180 generate 1.1181 + 1.1182 if (IRQ_MODE == 1) begin 1.1183 - always @(posedge CLK_I or posedge RST_I) 1.1184 - if (RST_I) begin 1.1185 - IRQ_MASK <= #UDLY 0; 1.1186 - IRQ_MASK_BOTH <= #UDLY 0; 1.1187 - end else if (IRQ_MASK_WR_EN) begin 1.1188 - IRQ_MASK <= #UDLY GPIO_DAT_I[DATA_WIDTH-1:0]; 1.1189 - IRQ_MASK_BOTH <= #UDLY GPIO_DAT_I[INPUT_WIDTH-1:0]; 1.1190 - end 1.1191 - end 1.1192 + 1.1193 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.1194 + 1.1195 + genvar im_idx; 1.1196 + for (im_idx = 0; (im_idx < DATA_WIDTH) && (im_idx < 8); im_idx = im_idx + 1) 1.1197 + begin 1.1198 + always @(posedge CLK_I or posedge RST_I) 1.1199 + if (RST_I) 1.1200 + IRQ_MASK[im_idx] <= #UDLY 0; 1.1201 + else if (IRQ_MASK_WR_EN_0) 1.1202 + IRQ_MASK[im_idx] <= #UDLY GPIO_DAT_I_switch[im_idx]; 1.1203 + end 1.1204 + if (DATA_WIDTH > 8) begin 1.1205 + genvar jm_idx; 1.1206 + for (jm_idx = 8; (jm_idx < DATA_WIDTH) && (jm_idx < 16); jm_idx = jm_idx + 1) 1.1207 + begin 1.1208 + always @(posedge CLK_I or posedge RST_I) 1.1209 + if (RST_I) 1.1210 + IRQ_MASK[jm_idx] <= #UDLY 0; 1.1211 + else if (IRQ_MASK_WR_EN_1) 1.1212 + IRQ_MASK[jm_idx] <= #UDLY GPIO_DAT_I_switch[jm_idx-8]; 1.1213 + end 1.1214 + end 1.1215 + if (DATA_WIDTH > 16) begin 1.1216 + genvar km_idx; 1.1217 + for (km_idx = 16; (km_idx < DATA_WIDTH) && (km_idx < 24); km_idx = km_idx + 1) 1.1218 + begin 1.1219 + always @(posedge CLK_I or posedge RST_I) 1.1220 + if (RST_I) 1.1221 + IRQ_MASK[km_idx] <= #UDLY 0; 1.1222 + else if (IRQ_MASK_WR_EN_2) 1.1223 + IRQ_MASK[km_idx] <= #UDLY GPIO_DAT_I_switch[km_idx-16]; 1.1224 + end 1.1225 + end 1.1226 + if (DATA_WIDTH > 24) begin 1.1227 + genvar lm_idx; 1.1228 + for (lm_idx = 24; (lm_idx < DATA_WIDTH) && (lm_idx < 32); lm_idx = lm_idx + 1) 1.1229 + begin 1.1230 + always @(posedge CLK_I or posedge RST_I) 1.1231 + if (RST_I) 1.1232 + IRQ_MASK[lm_idx] <= #UDLY 0; 1.1233 + else if (IRQ_MASK_WR_EN_3) 1.1234 + IRQ_MASK[lm_idx] <= #UDLY GPIO_DAT_I_switch[lm_idx-24]; 1.1235 + end 1.1236 + end 1.1237 + 1.1238 + genvar imb_idx; 1.1239 + for (imb_idx = 0; (imb_idx < INPUT_WIDTH) && (imb_idx < 8); imb_idx = imb_idx + 1) 1.1240 + begin 1.1241 + always @(posedge CLK_I or posedge RST_I) 1.1242 + if (RST_I) 1.1243 + IRQ_MASK_BOTH[imb_idx] <= #UDLY 0; 1.1244 + else if (IRQ_MASK_WR_EN_0) 1.1245 + IRQ_MASK_BOTH[imb_idx] <= #UDLY GPIO_DAT_I_switch[imb_idx]; 1.1246 + end 1.1247 + if (INPUT_WIDTH > 8) begin 1.1248 + genvar jmb_idx; 1.1249 + for (jmb_idx = 8; (jmb_idx < INPUT_WIDTH) && (jmb_idx < 16); jmb_idx = jmb_idx + 1) 1.1250 + begin 1.1251 + always @(posedge CLK_I or posedge RST_I) 1.1252 + if (RST_I) 1.1253 + IRQ_MASK_BOTH[jmb_idx] <= #UDLY 0; 1.1254 + else if (IRQ_MASK_WR_EN_1) 1.1255 + IRQ_MASK_BOTH[jmb_idx] <= #UDLY GPIO_DAT_I_switch[jmb_idx-8]; 1.1256 + end 1.1257 + end 1.1258 + if (INPUT_WIDTH > 16) begin 1.1259 + genvar kmb_idx; 1.1260 + for (kmb_idx = 16; (kmb_idx < INPUT_WIDTH) && (kmb_idx < 24); kmb_idx = kmb_idx + 1) 1.1261 + begin 1.1262 + always @(posedge CLK_I or posedge RST_I) 1.1263 + if (RST_I) 1.1264 + IRQ_MASK_BOTH[kmb_idx] <= #UDLY 0; 1.1265 + else if (IRQ_MASK_WR_EN_2) 1.1266 + IRQ_MASK_BOTH[kmb_idx] <= #UDLY GPIO_DAT_I_switch[kmb_idx-16]; 1.1267 + end 1.1268 + end 1.1269 + if (INPUT_WIDTH > 24) begin 1.1270 + genvar lmb_idx; 1.1271 + for (lmb_idx = 24; (lmb_idx < INPUT_WIDTH) && (lmb_idx < 32); lmb_idx = lmb_idx + 1) 1.1272 + begin 1.1273 + always @(posedge CLK_I or posedge RST_I) 1.1274 + if (RST_I) 1.1275 + IRQ_MASK_BOTH[lmb_idx] <= #UDLY 0; 1.1276 + else if (IRQ_MASK_WR_EN_3) 1.1277 + IRQ_MASK_BOTH[lmb_idx] <= #UDLY GPIO_DAT_I_switch[lmb_idx-24]; 1.1278 + end 1.1279 + end 1.1280 + 1.1281 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.1282 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.1283 + 1.1284 + genvar im_idx; 1.1285 + for (im_idx = 0; (im_idx < DATA_WIDTH) && (im_idx < 8); im_idx = im_idx + 1) 1.1286 + begin 1.1287 + always @(posedge CLK_I or posedge RST_I) 1.1288 + if (RST_I) 1.1289 + IRQ_MASK[im_idx] <= #UDLY 0; 1.1290 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0]) 1.1291 + IRQ_MASK[im_idx] <= #UDLY GPIO_DAT_I_switch[im_idx]; 1.1292 + end 1.1293 + if (DATA_WIDTH > 8) begin 1.1294 + genvar jm_idx; 1.1295 + for (jm_idx = 8; (jm_idx < DATA_WIDTH) && (jm_idx < 16); jm_idx = jm_idx + 1) 1.1296 + begin 1.1297 + always @(posedge CLK_I or posedge RST_I) 1.1298 + if (RST_I) 1.1299 + IRQ_MASK[jm_idx] <= #UDLY 0; 1.1300 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1]) 1.1301 + IRQ_MASK[jm_idx] <= #UDLY GPIO_DAT_I_switch[jm_idx]; 1.1302 + end 1.1303 + end 1.1304 + if (DATA_WIDTH > 16) begin 1.1305 + genvar km_idx; 1.1306 + for (km_idx = 16; (km_idx < DATA_WIDTH) && (km_idx < 24); km_idx = km_idx + 1) 1.1307 + begin 1.1308 + always @(posedge CLK_I or posedge RST_I) 1.1309 + if (RST_I) 1.1310 + IRQ_MASK[km_idx] <= #UDLY 0; 1.1311 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2]) 1.1312 + IRQ_MASK[km_idx] <= #UDLY GPIO_DAT_I_switch[km_idx]; 1.1313 + end 1.1314 + end 1.1315 + if (DATA_WIDTH > 24) begin 1.1316 + genvar lm_idx; 1.1317 + for (lm_idx = 24; (lm_idx < DATA_WIDTH) && (lm_idx < 32); lm_idx = lm_idx + 1) 1.1318 + begin 1.1319 + always @(posedge CLK_I or posedge RST_I) 1.1320 + if (RST_I) 1.1321 + IRQ_MASK[lm_idx] <= #UDLY 0; 1.1322 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3]) 1.1323 + IRQ_MASK[lm_idx] <= #UDLY GPIO_DAT_I_switch[lm_idx]; 1.1324 + end 1.1325 + end 1.1326 + 1.1327 + genvar imb_idx; 1.1328 + for (imb_idx = 0; (imb_idx < INPUT_WIDTH) && (imb_idx < 8); imb_idx = imb_idx + 1) 1.1329 + begin 1.1330 + always @(posedge CLK_I or posedge RST_I) 1.1331 + if (RST_I) 1.1332 + IRQ_MASK_BOTH[imb_idx] <= #UDLY 0; 1.1333 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0]) 1.1334 + IRQ_MASK_BOTH[imb_idx] <= #UDLY GPIO_DAT_I_switch[imb_idx]; 1.1335 + end 1.1336 + if (INPUT_WIDTH > 8) begin 1.1337 + genvar jmb_idx; 1.1338 + for (jmb_idx = 8; (jmb_idx < INPUT_WIDTH) && (jmb_idx < 16); jmb_idx = jmb_idx + 1) 1.1339 + begin 1.1340 + always @(posedge CLK_I or posedge RST_I) 1.1341 + if (RST_I) 1.1342 + IRQ_MASK_BOTH[jmb_idx] <= #UDLY 0; 1.1343 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1]) 1.1344 + IRQ_MASK_BOTH[jmb_idx] <= #UDLY GPIO_DAT_I_switch[jmb_idx]; 1.1345 + end 1.1346 + end 1.1347 + if (INPUT_WIDTH > 16) begin 1.1348 + genvar kmb_idx; 1.1349 + for (kmb_idx = 16; (kmb_idx < INPUT_WIDTH) && (kmb_idx < 24); kmb_idx = kmb_idx + 1) 1.1350 + begin 1.1351 + always @(posedge CLK_I or posedge RST_I) 1.1352 + if (RST_I) 1.1353 + IRQ_MASK_BOTH[kmb_idx] <= #UDLY 0; 1.1354 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2]) 1.1355 + IRQ_MASK_BOTH[kmb_idx] <= #UDLY GPIO_DAT_I_switch[kmb_idx]; 1.1356 + end 1.1357 + end 1.1358 + if (INPUT_WIDTH > 24) begin 1.1359 + genvar lmb_idx; 1.1360 + for (lmb_idx = 24; (lmb_idx < INPUT_WIDTH) && (lmb_idx < 32); lmb_idx = lmb_idx + 1) 1.1361 + begin 1.1362 + always @(posedge CLK_I or posedge RST_I) 1.1363 + if (RST_I) 1.1364 + IRQ_MASK_BOTH[lmb_idx] <= #UDLY 0; 1.1365 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3]) 1.1366 + IRQ_MASK_BOTH[lmb_idx] <= #UDLY GPIO_DAT_I_switch[lmb_idx]; 1.1367 + end 1.1368 + end 1.1369 + 1.1370 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.1371 + 1.1372 + end // if (IRQ_MODE == 1) 1.1373 + 1.1374 endgenerate 1.1375 - 1.1376 + 1.1377 + 1.1378 + 1.1379 generate 1.1380 //-------------------------------- 1.1381 //--INPUT_PORTS_ONLY MODE IRQ 1.1382 //-------------------------------- 1.1383 - if (IRQ_MODE == 1 && INPUT_PORTS_ONLY == 1 && LEVEL == 1) begin 1.1384 - //level mode IRQ 1.1385 - always @(posedge CLK_I or posedge RST_I) 1.1386 - if (RST_I) 1.1387 - IRQ_TEMP <= #UDLY 0; 1.1388 - else if (IRQ_MASK_WR_EN) 1.1389 - IRQ_TEMP <= #UDLY IRQ_TEMP & GPIO_DAT_I[DATA_WIDTH-1:0]; 1.1390 - else 1.1391 - IRQ_TEMP <= #UDLY PIO_IN & IRQ_MASK;//bit-and 1.1392 + if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (LEVEL == 1)) begin 1.1393 + // level mode IRQ 1.1394 + 1.1395 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.1396 + 1.1397 + genvar i; 1.1398 + for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1) 1.1399 + begin 1.1400 + always @(posedge CLK_I or posedge RST_I) 1.1401 + if (RST_I) 1.1402 + IRQ_TEMP[i] <= #UDLY 0; 1.1403 + else if (IRQ_MASK_WR_EN_0) 1.1404 + IRQ_TEMP[i] <= #UDLY IRQ_TEMP[i] & GPIO_DAT_I_switch[i]; 1.1405 + else 1.1406 + IRQ_TEMP[i] <= #UDLY PIO_IN[i] & IRQ_MASK[i]; 1.1407 + end 1.1408 + if (DATA_WIDTH > 8) begin 1.1409 + genvar j; 1.1410 + for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1) 1.1411 + begin 1.1412 + always @(posedge CLK_I or posedge RST_I) 1.1413 + if (RST_I) 1.1414 + IRQ_TEMP[j] <= #UDLY 0; 1.1415 + else if (IRQ_MASK_WR_EN_1) 1.1416 + IRQ_TEMP[j] <= #UDLY IRQ_TEMP[j] & GPIO_DAT_I_switch[j-8]; 1.1417 + else 1.1418 + IRQ_TEMP[j] <= #UDLY PIO_IN[j] & IRQ_MASK[j]; 1.1419 + end 1.1420 + end 1.1421 + if (DATA_WIDTH > 16) begin 1.1422 + genvar k; 1.1423 + for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1) 1.1424 + begin 1.1425 + always @(posedge CLK_I or posedge RST_I) 1.1426 + if (RST_I) 1.1427 + IRQ_TEMP[k] <= #UDLY 0; 1.1428 + else if (IRQ_MASK_WR_EN_2) 1.1429 + IRQ_TEMP[k] <= #UDLY IRQ_TEMP[k] & GPIO_DAT_I_switch[k-16]; 1.1430 + else 1.1431 + IRQ_TEMP[k] <= #UDLY PIO_IN[k] & IRQ_MASK[k]; 1.1432 + end 1.1433 + end 1.1434 + if (DATA_WIDTH > 24) begin 1.1435 + genvar l; 1.1436 + for (l = 24; (l < DATA_WIDTH) && (l < 32); l = l + 1) 1.1437 + begin 1.1438 + always @(posedge CLK_I or posedge RST_I) 1.1439 + if (RST_I) 1.1440 + IRQ_TEMP[l] <= #UDLY 0; 1.1441 + else if (IRQ_MASK_WR_EN_3) 1.1442 + IRQ_TEMP[l] <= #UDLY IRQ_TEMP[l] & GPIO_DAT_I_switch[l-24]; 1.1443 + else 1.1444 + IRQ_TEMP[l] <= #UDLY PIO_IN[l] & IRQ_MASK[l]; 1.1445 + end 1.1446 + end 1.1447 + 1.1448 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.1449 + 1.1450 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.1451 + 1.1452 + genvar i; 1.1453 + for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1) 1.1454 + begin 1.1455 + always @(posedge CLK_I or posedge RST_I) 1.1456 + if (RST_I) 1.1457 + IRQ_TEMP[i] <= #UDLY 0; 1.1458 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0]) 1.1459 + IRQ_TEMP[i] <= #UDLY IRQ_TEMP[i] & GPIO_DAT_I_switch[i]; 1.1460 + else 1.1461 + IRQ_TEMP[i] <= #UDLY PIO_IN[i] & IRQ_MASK[i]; 1.1462 + end 1.1463 + if (DATA_WIDTH > 8) begin 1.1464 + genvar j; 1.1465 + for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1) 1.1466 + begin 1.1467 + always @(posedge CLK_I or posedge RST_I) 1.1468 + if (RST_I) 1.1469 + IRQ_TEMP[j] <= #UDLY 0; 1.1470 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1]) 1.1471 + IRQ_TEMP[j] <= #UDLY IRQ_TEMP[j] & GPIO_DAT_I_switch[j]; 1.1472 + else 1.1473 + IRQ_TEMP[j] <= #UDLY PIO_IN[j] & IRQ_MASK[j]; 1.1474 + end 1.1475 + end 1.1476 + if (DATA_WIDTH > 16) begin 1.1477 + genvar k; 1.1478 + for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1) 1.1479 + begin 1.1480 + always @(posedge CLK_I or posedge RST_I) 1.1481 + if (RST_I) 1.1482 + IRQ_TEMP[k] <= #UDLY 0; 1.1483 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2]) 1.1484 + IRQ_TEMP[k] <= #UDLY IRQ_TEMP[k] & GPIO_DAT_I_switch[k]; 1.1485 + else 1.1486 + IRQ_TEMP[k] <= #UDLY PIO_IN[k] & IRQ_MASK[k]; 1.1487 + end 1.1488 + end 1.1489 + if (DATA_WIDTH > 24) begin 1.1490 + genvar l; 1.1491 + for (l = 24; (l < DATA_WIDTH) && (l < 32); l = l + 1) 1.1492 + begin 1.1493 + always @(posedge CLK_I or posedge RST_I) 1.1494 + if (RST_I) 1.1495 + IRQ_TEMP[l] <= #UDLY 0; 1.1496 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3]) 1.1497 + IRQ_TEMP[l] <= #UDLY IRQ_TEMP[l] & GPIO_DAT_I_switch[l]; 1.1498 + else 1.1499 + IRQ_TEMP[l] <= #UDLY PIO_IN[l] & IRQ_MASK[l]; 1.1500 + end 1.1501 + end 1.1502 + 1.1503 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.1504 + 1.1505 assign IRQ_O = |IRQ_TEMP; 1.1506 - end else if (IRQ_MODE == 1 && INPUT_PORTS_ONLY == 1 && EDGE == 1) begin 1.1507 + 1.1508 + end // if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (LEVEL == 1)) 1.1509 + 1.1510 + else if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (EDGE == 1)) begin 1.1511 + // edge mode IRQ 1.1512 + 1.1513 always @(posedge CLK_I or posedge RST_I) 1.1514 if (RST_I) 1.1515 PIO_DATA_DLY <= #UDLY 0; 1.1516 else 1.1517 PIO_DATA_DLY <= PIO_IN; 1.1518 - 1.1519 + 1.1520 // edge-capture register bits are treated as individual bits. 1.1521 - genvar i; 1.1522 - for( i = 0; i < DATA_WIDTH; i = i + 1) 1.1523 - begin 1.1524 - always @(posedge CLK_I or posedge RST_I) 1.1525 - if (RST_I) 1.1526 - EDGE_CAPTURE[i] <= #UDLY 0; 1.1527 - else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (POSE_EDGE_IRQ == 1)) 1.1528 - EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i]; 1.1529 - else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (NEGE_EDGE_IRQ == 1)) 1.1530 - EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i]; 1.1531 - else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1)) 1.1532 - EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i]; 1.1533 - else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1)) 1.1534 - EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i]; 1.1535 - else if ( (~IRQ_MASK[i]) & GPIO_DAT_I[i] & IRQ_MASK_WR_EN ) 1.1536 - // interrupt mask is being set, so clear edge-capture 1.1537 - EDGE_CAPTURE[i] <= #UDLY 0; 1.1538 - else if (EDGE_CAP_WR_EN) 1.1539 - // user's writing to the edge register, so update edge capture 1.1540 - // register 1.1541 - EDGE_CAPTURE[i] <= #UDLY EDGE_CAPTURE[i] & GPIO_DAT_I[i]; 1.1542 - end 1.1543 - assign IRQ_O = |(EDGE_CAPTURE & IRQ_MASK); 1.1544 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.1545 + 1.1546 + genvar i; 1.1547 + for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1) 1.1548 + begin 1.1549 + always @(posedge CLK_I or posedge RST_I) 1.1550 + if (RST_I) 1.1551 + EDGE_CAPTURE[i] <= #UDLY 0; 1.1552 + else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (POSE_EDGE_IRQ == 1)) 1.1553 + EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i]; 1.1554 + else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (NEGE_EDGE_IRQ == 1)) 1.1555 + EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i]; 1.1556 + else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1)) 1.1557 + EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i]; 1.1558 + else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1)) 1.1559 + EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i]; 1.1560 + else if ( (~IRQ_MASK[i]) & GPIO_DAT_I_switch[i] & IRQ_MASK_WR_EN_0) 1.1561 + // interrupt mask is being set, so clear edge-capture 1.1562 + EDGE_CAPTURE[i] <= #UDLY 0; 1.1563 + else if (EDGE_CAP_WR_EN_0) 1.1564 + // user's writing to the edge register, so update edge capture 1.1565 + // register 1.1566 + EDGE_CAPTURE[i] <= #UDLY EDGE_CAPTURE[i] & GPIO_DAT_I_switch[i]; 1.1567 + end 1.1568 + 1.1569 + if (DATA_WIDTH > 8) begin 1.1570 + genvar j; 1.1571 + for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1) 1.1572 + begin 1.1573 + always @(posedge CLK_I or posedge RST_I) 1.1574 + if (RST_I) 1.1575 + EDGE_CAPTURE[j] <= #UDLY 0; 1.1576 + else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (POSE_EDGE_IRQ == 1)) 1.1577 + EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j]; 1.1578 + else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (NEGE_EDGE_IRQ == 1)) 1.1579 + EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j]; 1.1580 + else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1)) 1.1581 + EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j]; 1.1582 + else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1)) 1.1583 + EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j]; 1.1584 + else if ( (~IRQ_MASK[j]) & GPIO_DAT_I_switch[j-8] & IRQ_MASK_WR_EN_1) 1.1585 + // interrupt mask is being set, so clear edge-capture 1.1586 + EDGE_CAPTURE[j] <= #UDLY 0; 1.1587 + else if (EDGE_CAP_WR_EN_1) 1.1588 + // user's writing to the edge register, so update edge capture 1.1589 + // register 1.1590 + EDGE_CAPTURE[j] <= #UDLY EDGE_CAPTURE[j] & GPIO_DAT_I_switch[j-8]; 1.1591 + end 1.1592 + end 1.1593 + 1.1594 + if (DATA_WIDTH > 16) begin 1.1595 + genvar k; 1.1596 + for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1) 1.1597 + begin 1.1598 + always @(posedge CLK_I or posedge RST_I) 1.1599 + if (RST_I) 1.1600 + EDGE_CAPTURE[k] <= #UDLY 0; 1.1601 + else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (POSE_EDGE_IRQ == 1)) 1.1602 + EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k]; 1.1603 + else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (NEGE_EDGE_IRQ == 1)) 1.1604 + EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k]; 1.1605 + else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1)) 1.1606 + EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k]; 1.1607 + else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1)) 1.1608 + EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k]; 1.1609 + else if ( (~IRQ_MASK[k]) & GPIO_DAT_I_switch[k-16] & IRQ_MASK_WR_EN_2) 1.1610 + // interrupt mask is being set, so clear edge-capture 1.1611 + EDGE_CAPTURE[k] <= #UDLY 0; 1.1612 + else if (EDGE_CAP_WR_EN_2) 1.1613 + // user's writing to the edge register, so update edge capture 1.1614 + // register 1.1615 + EDGE_CAPTURE[k] <= #UDLY EDGE_CAPTURE[k] & GPIO_DAT_I_switch[k-16]; 1.1616 + end 1.1617 + end 1.1618 + 1.1619 + if (DATA_WIDTH > 24) begin 1.1620 + genvar l; 1.1621 + for (l = 24; l < DATA_WIDTH; l = l + 1) 1.1622 + begin 1.1623 + always @(posedge CLK_I or posedge RST_I) 1.1624 + if (RST_I) 1.1625 + EDGE_CAPTURE[l] <= #UDLY 0; 1.1626 + else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (POSE_EDGE_IRQ == 1)) 1.1627 + EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l]; 1.1628 + else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (NEGE_EDGE_IRQ == 1)) 1.1629 + EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l]; 1.1630 + else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1)) 1.1631 + EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l]; 1.1632 + else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1)) 1.1633 + EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l]; 1.1634 + else if ( (~IRQ_MASK[l]) & GPIO_DAT_I_switch[l-24] & IRQ_MASK_WR_EN_3) 1.1635 + // interrupt mask is being set, so clear edge-capture 1.1636 + EDGE_CAPTURE[l] <= #UDLY 0; 1.1637 + else if (EDGE_CAP_WR_EN_3) 1.1638 + // user's writing to the edge register, so update edge capture 1.1639 + // register 1.1640 + EDGE_CAPTURE[l] <= #UDLY EDGE_CAPTURE[l] & GPIO_DAT_I_switch[l-24]; 1.1641 + end 1.1642 + end 1.1643 + 1.1644 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.1645 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.1646 + 1.1647 + genvar i; 1.1648 + for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1) 1.1649 + begin 1.1650 + always @(posedge CLK_I or posedge RST_I) 1.1651 + if (RST_I) 1.1652 + EDGE_CAPTURE[i] <= #UDLY 0; 1.1653 + else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (POSE_EDGE_IRQ == 1)) 1.1654 + EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i]; 1.1655 + else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (NEGE_EDGE_IRQ == 1)) 1.1656 + EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i]; 1.1657 + else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1)) 1.1658 + EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i]; 1.1659 + else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1)) 1.1660 + EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i]; 1.1661 + else if ( (~IRQ_MASK[i]) & GPIO_DAT_I_switch[i] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0]) 1.1662 + // interrupt mask is being set, so clear edge-capture 1.1663 + EDGE_CAPTURE[i] <= #UDLY 0; 1.1664 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[0]) 1.1665 + // user's writing to the edge register, so update edge capture 1.1666 + // register 1.1667 + EDGE_CAPTURE[i] <= #UDLY EDGE_CAPTURE[i] & GPIO_DAT_I_switch[i]; 1.1668 + end 1.1669 + 1.1670 + if (DATA_WIDTH > 8) begin 1.1671 + genvar j; 1.1672 + for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1) 1.1673 + begin 1.1674 + always @(posedge CLK_I or posedge RST_I) 1.1675 + if (RST_I) 1.1676 + EDGE_CAPTURE[j] <= #UDLY 0; 1.1677 + else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (POSE_EDGE_IRQ == 1)) 1.1678 + EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j]; 1.1679 + else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (NEGE_EDGE_IRQ == 1)) 1.1680 + EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j]; 1.1681 + else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1)) 1.1682 + EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j]; 1.1683 + else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1)) 1.1684 + EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j]; 1.1685 + else if ( (~IRQ_MASK[j]) & GPIO_DAT_I_switch[j-8] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0]) 1.1686 + // interrupt mask is being set, so clear edge-capture 1.1687 + EDGE_CAPTURE[j] <= #UDLY 0; 1.1688 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[0]) 1.1689 + // user's writing to the edge register, so update edge capture 1.1690 + // register 1.1691 + EDGE_CAPTURE[j] <= #UDLY EDGE_CAPTURE[j] & GPIO_DAT_I_switch[j]; 1.1692 + end 1.1693 + end 1.1694 + 1.1695 + if (DATA_WIDTH > 16) begin 1.1696 + genvar k; 1.1697 + for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1) 1.1698 + begin 1.1699 + always @(posedge CLK_I or posedge RST_I) 1.1700 + if (RST_I) 1.1701 + EDGE_CAPTURE[k] <= #UDLY 0; 1.1702 + else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (POSE_EDGE_IRQ == 1)) 1.1703 + EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k]; 1.1704 + else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (NEGE_EDGE_IRQ == 1)) 1.1705 + EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k]; 1.1706 + else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1)) 1.1707 + EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k]; 1.1708 + else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1)) 1.1709 + EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k]; 1.1710 + else if ( (~IRQ_MASK[k]) & GPIO_DAT_I_switch[k-16] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2]) 1.1711 + // interrupt mask is being set, so clear edge-capture 1.1712 + EDGE_CAPTURE[k] <= #UDLY 0; 1.1713 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[2]) 1.1714 + // user's writing to the edge register, so update edge capture 1.1715 + // register 1.1716 + EDGE_CAPTURE[k] <= #UDLY EDGE_CAPTURE[k] & GPIO_DAT_I_switch[k]; 1.1717 + end 1.1718 + end 1.1719 + 1.1720 + if (DATA_WIDTH > 24) begin 1.1721 + genvar l; 1.1722 + for (l = 24; l < DATA_WIDTH; l = l + 1) 1.1723 + begin 1.1724 + always @(posedge CLK_I or posedge RST_I) 1.1725 + if (RST_I) 1.1726 + EDGE_CAPTURE[l] <= #UDLY 0; 1.1727 + else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (POSE_EDGE_IRQ == 1)) 1.1728 + EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l]; 1.1729 + else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (NEGE_EDGE_IRQ == 1)) 1.1730 + EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l]; 1.1731 + else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1)) 1.1732 + EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l]; 1.1733 + else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1)) 1.1734 + EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l]; 1.1735 + else if ( (~IRQ_MASK[l]) & GPIO_DAT_I_switch[l-24] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3]) 1.1736 + // interrupt mask is being set, so clear edge-capture 1.1737 + EDGE_CAPTURE[l] <= #UDLY 0; 1.1738 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[3]) 1.1739 + // user's writing to the edge register, so update edge capture 1.1740 + // register 1.1741 + EDGE_CAPTURE[l] <= #UDLY EDGE_CAPTURE[l] & GPIO_DAT_I_switch[l]; 1.1742 + end 1.1743 + end 1.1744 + 1.1745 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.1746 + 1.1747 + assign IRQ_O = |(EDGE_CAPTURE[DATA_WIDTH-1:0] & IRQ_MASK[DATA_WIDTH-1:0]); 1.1748 + 1.1749 + end // if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (EDGE == 1)) 1.1750 + 1.1751 + //---------------------------------- 1.1752 + //--BOTH_INPUT_AND_OUTPUT MODE IRQ 1.1753 + //---------------------------------- 1.1754 + else if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (LEVEL == 1)) begin 1.1755 1.1756 - //---------------------------------- 1.1757 - //--BOTH_INPUT_AND_OUTPUT MODE IRQ 1.1758 - //---------------------------------- 1.1759 - end else if (IRQ_MODE == 1 && BOTH_INPUT_AND_OUTPUT == 1 && LEVEL == 1) begin 1.1760 - always @(posedge CLK_I or posedge RST_I) 1.1761 - if (RST_I) 1.1762 - IRQ_TEMP_BOTH <= #UDLY 0; 1.1763 - else if (IRQ_MASK_WR_EN) 1.1764 - IRQ_TEMP_BOTH <= #UDLY IRQ_TEMP_BOTH & GPIO_DAT_I[INPUT_WIDTH-1:0]; 1.1765 - else 1.1766 - IRQ_TEMP_BOTH <= #UDLY PIO_BOTH_IN & IRQ_MASK_BOTH; 1.1767 - assign IRQ_O = |IRQ_TEMP_BOTH; 1.1768 - 1.1769 - //edge mode IRQ 1.1770 - end else if (IRQ_MODE == 1 && BOTH_INPUT_AND_OUTPUT == 1 && EDGE == 1) begin 1.1771 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.1772 + 1.1773 + genvar iitb_idx; 1.1774 + for (iitb_idx = 0; (iitb_idx < INPUT_WIDTH) && (iitb_idx < 8); iitb_idx = iitb_idx + 1) 1.1775 + begin 1.1776 + always @(posedge CLK_I or posedge RST_I) 1.1777 + if (RST_I) 1.1778 + IRQ_TEMP_BOTH[iitb_idx] <= #UDLY 0; 1.1779 + else if (IRQ_MASK_WR_EN_0) 1.1780 + IRQ_TEMP_BOTH[iitb_idx] <= #UDLY IRQ_TEMP_BOTH[iitb_idx] & GPIO_DAT_I_switch[iitb_idx]; 1.1781 + else 1.1782 + IRQ_TEMP_BOTH[iitb_idx] <= #UDLY PIO_BOTH_IN[iitb_idx] & IRQ_MASK_BOTH[iitb_idx]; 1.1783 + end 1.1784 + if (INPUT_WIDTH > 8) begin 1.1785 + genvar jitb_idx; 1.1786 + for (jitb_idx = 8; (jitb_idx < INPUT_WIDTH) && (jitb_idx < 16); jitb_idx = jitb_idx + 1) 1.1787 + begin 1.1788 + always @(posedge CLK_I or posedge RST_I) 1.1789 + if (RST_I) 1.1790 + IRQ_TEMP_BOTH[jitb_idx] <= #UDLY 0; 1.1791 + else if (IRQ_MASK_WR_EN_1) 1.1792 + IRQ_TEMP_BOTH[jitb_idx] <= #UDLY IRQ_TEMP_BOTH[jitb_idx] & GPIO_DAT_I_switch[jitb_idx - 8]; 1.1793 + else 1.1794 + IRQ_TEMP_BOTH[jitb_idx] <= #UDLY PIO_BOTH_IN[jitb_idx] & IRQ_MASK_BOTH[jitb_idx]; 1.1795 + end 1.1796 + end 1.1797 + if (INPUT_WIDTH > 16) begin 1.1798 + genvar kitb_idx; 1.1799 + for (kitb_idx = 16; (kitb_idx < INPUT_WIDTH) && (kitb_idx < 24); kitb_idx = kitb_idx + 1) 1.1800 + begin 1.1801 + always @(posedge CLK_I or posedge RST_I) 1.1802 + if (RST_I) 1.1803 + IRQ_TEMP_BOTH[kitb_idx] <= #UDLY 0; 1.1804 + else if (IRQ_MASK_WR_EN_2) 1.1805 + IRQ_TEMP_BOTH[kitb_idx] <= #UDLY IRQ_TEMP_BOTH[kitb_idx] & GPIO_DAT_I_switch[kitb_idx - 16]; 1.1806 + else 1.1807 + IRQ_TEMP_BOTH[kitb_idx] <= #UDLY PIO_BOTH_IN[kitb_idx] & IRQ_MASK_BOTH[kitb_idx]; 1.1808 + end 1.1809 + end 1.1810 + if (INPUT_WIDTH > 24) begin 1.1811 + genvar litb_idx; 1.1812 + for (litb_idx = 24; (litb_idx < INPUT_WIDTH) && (litb_idx < 24); litb_idx = litb_idx + 1) 1.1813 + begin 1.1814 + always @(posedge CLK_I or posedge RST_I) 1.1815 + if (RST_I) 1.1816 + IRQ_TEMP_BOTH[litb_idx] <= #UDLY 0; 1.1817 + else if (IRQ_MASK_WR_EN_3) 1.1818 + IRQ_TEMP_BOTH[litb_idx] <= #UDLY IRQ_TEMP_BOTH[litb_idx] & GPIO_DAT_I_switch[litb_idx - 24]; 1.1819 + else 1.1820 + IRQ_TEMP_BOTH[litb_idx] <= #UDLY PIO_BOTH_IN[litb_idx] & IRQ_MASK_BOTH[litb_idx]; 1.1821 + end 1.1822 + end 1.1823 + 1.1824 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.1825 + 1.1826 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.1827 + 1.1828 + genvar iitb_idx; 1.1829 + for (iitb_idx = 0; (iitb_idx < INPUT_WIDTH) && (iitb_idx < 8); iitb_idx = iitb_idx + 1) 1.1830 + begin 1.1831 + always @(posedge CLK_I or posedge RST_I) 1.1832 + if (RST_I) 1.1833 + IRQ_TEMP_BOTH[iitb_idx] <= #UDLY 0; 1.1834 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0]) 1.1835 + IRQ_TEMP_BOTH[iitb_idx] <= #UDLY IRQ_TEMP_BOTH[iitb_idx] & GPIO_DAT_I_switch[iitb_idx]; 1.1836 + else 1.1837 + IRQ_TEMP_BOTH[iitb_idx] <= #UDLY PIO_BOTH_IN[iitb_idx] & IRQ_MASK_BOTH[iitb_idx]; 1.1838 + end 1.1839 + if (INPUT_WIDTH > 8) begin 1.1840 + genvar jitb_idx; 1.1841 + for (jitb_idx = 8; (jitb_idx < INPUT_WIDTH) && (jitb_idx < 16); jitb_idx = jitb_idx + 1) 1.1842 + begin 1.1843 + always @(posedge CLK_I or posedge RST_I) 1.1844 + if (RST_I) 1.1845 + IRQ_TEMP_BOTH[jitb_idx] <= #UDLY 0; 1.1846 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1]) 1.1847 + IRQ_TEMP_BOTH[jitb_idx] <= #UDLY IRQ_TEMP_BOTH[jitb_idx] & GPIO_DAT_I_switch[jitb_idx]; 1.1848 + else 1.1849 + IRQ_TEMP_BOTH[jitb_idx] <= #UDLY PIO_BOTH_IN[jitb_idx] & IRQ_MASK_BOTH[jitb_idx]; 1.1850 + end 1.1851 + end 1.1852 + if (INPUT_WIDTH > 16) begin 1.1853 + genvar kitb_idx; 1.1854 + for (kitb_idx = 16; (kitb_idx < INPUT_WIDTH) && (kitb_idx < 24); kitb_idx = kitb_idx + 1) 1.1855 + begin 1.1856 + always @(posedge CLK_I or posedge RST_I) 1.1857 + if (RST_I) 1.1858 + IRQ_TEMP_BOTH[kitb_idx] <= #UDLY 0; 1.1859 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2]) 1.1860 + IRQ_TEMP_BOTH[kitb_idx] <= #UDLY IRQ_TEMP_BOTH[kitb_idx] & GPIO_DAT_I_switch[kitb_idx]; 1.1861 + else 1.1862 + IRQ_TEMP_BOTH[kitb_idx] <= #UDLY PIO_BOTH_IN[kitb_idx] & IRQ_MASK_BOTH[kitb_idx]; 1.1863 + end 1.1864 + end 1.1865 + if (INPUT_WIDTH > 24) begin 1.1866 + genvar litb_idx; 1.1867 + for (litb_idx = 24; (litb_idx < INPUT_WIDTH) && (litb_idx < 24); litb_idx = litb_idx + 1) 1.1868 + begin 1.1869 + always @(posedge CLK_I or posedge RST_I) 1.1870 + if (RST_I) 1.1871 + IRQ_TEMP_BOTH[litb_idx] <= #UDLY 0; 1.1872 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3]) 1.1873 + IRQ_TEMP_BOTH[litb_idx] <= #UDLY IRQ_TEMP_BOTH[litb_idx] & GPIO_DAT_I_switch[litb_idx]; 1.1874 + else 1.1875 + IRQ_TEMP_BOTH[litb_idx] <= #UDLY PIO_BOTH_IN[litb_idx] & IRQ_MASK_BOTH[litb_idx]; 1.1876 + end 1.1877 + end 1.1878 + 1.1879 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.1880 + 1.1881 + assign IRQ_O = |IRQ_TEMP_BOTH; 1.1882 + 1.1883 + end // if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (LEVEL == 1)) 1.1884 + 1.1885 + // edge mode IRQ 1.1886 + else if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (EDGE == 1)) begin 1.1887 + 1.1888 always @(posedge CLK_I or posedge RST_I) 1.1889 if (RST_I) 1.1890 PIO_DATA_DLY_BOTH <= #UDLY 0; 1.1891 else 1.1892 PIO_DATA_DLY_BOTH <= PIO_BOTH_IN; 1.1893 - 1.1894 + 1.1895 // edge-capture register bits are treated as individual bits. 1.1896 - genvar i_both; 1.1897 - for( i_both = 0; i_both < INPUT_WIDTH; i_both = i_both + 1) 1.1898 - begin 1.1899 - always @(posedge CLK_I or posedge RST_I) 1.1900 - if (RST_I) 1.1901 - EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0; 1.1902 - else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && POSE_EDGE_IRQ == 1) 1.1903 - EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]; 1.1904 - else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && NEGE_EDGE_IRQ == 1) 1.1905 - EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]; 1.1906 - else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1) 1.1907 - EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]; 1.1908 - else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1) 1.1909 - EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]; 1.1910 - else if ( (~IRQ_MASK_BOTH[i_both]) & GPIO_DAT_I[i_both] & IRQ_MASK_WR_EN ) 1.1911 - // interrupt mask is being set, so clear edge-capture 1.1912 - EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0; 1.1913 - else if (EDGE_CAP_WR_EN) 1.1914 - // user's writing to the edge register, so update edge capture 1.1915 - // register 1.1916 - EDGE_CAPTURE_BOTH[i_both] <= #UDLY EDGE_CAPTURE_BOTH[i_both] & GPIO_DAT_I[i_both]; 1.1917 - end 1.1918 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.1919 + 1.1920 + genvar i_both; 1.1921 + for (i_both = 0; (i_both < INPUT_WIDTH) && (i_both < 8); i_both = i_both + 1) 1.1922 + begin 1.1923 + always @(posedge CLK_I or posedge RST_I) 1.1924 + if (RST_I) 1.1925 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0; 1.1926 + else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && POSE_EDGE_IRQ == 1) 1.1927 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]; 1.1928 + else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && NEGE_EDGE_IRQ == 1) 1.1929 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]; 1.1930 + else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1) 1.1931 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]; 1.1932 + else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1) 1.1933 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]; 1.1934 + else if ( (~IRQ_MASK_BOTH[i_both]) & GPIO_DAT_I_switch[i_both] & IRQ_MASK_WR_EN_0 ) 1.1935 + // interrupt mask is being set, so clear edge-capture 1.1936 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0; 1.1937 + else if (EDGE_CAP_WR_EN_0) 1.1938 + // user's writing to the edge register, so update edge capture 1.1939 + // register 1.1940 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY EDGE_CAPTURE_BOTH[i_both] & GPIO_DAT_I_switch[i_both]; 1.1941 + end 1.1942 + if (INPUT_WIDTH > 8) begin 1.1943 + genvar j_both; 1.1944 + for (j_both = 8; (j_both < INPUT_WIDTH) && (j_both < 16); j_both = j_both + 1) 1.1945 + begin 1.1946 + always @(posedge CLK_I or posedge RST_I) 1.1947 + if (RST_I) 1.1948 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0; 1.1949 + else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && POSE_EDGE_IRQ == 1) 1.1950 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]; 1.1951 + else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) && NEGE_EDGE_IRQ == 1) 1.1952 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]; 1.1953 + else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1) 1.1954 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]; 1.1955 + else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1) 1.1956 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]; 1.1957 + else if ( (~IRQ_MASK_BOTH[j_both]) & GPIO_DAT_I_switch[j_both-8] & IRQ_MASK_WR_EN_1 ) 1.1958 + // interrupt mask is being set, so clear edge-capture 1.1959 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0; 1.1960 + else if (EDGE_CAP_WR_EN_1) 1.1961 + // user's writing to the edge register, so update edge capture 1.1962 + // register 1.1963 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY EDGE_CAPTURE_BOTH[j_both] & GPIO_DAT_I_switch[j_both-8]; 1.1964 + end 1.1965 + end 1.1966 + if (INPUT_WIDTH > 16) begin 1.1967 + genvar k_both; 1.1968 + for (k_both = 16; (k_both < INPUT_WIDTH) && (k_both < 24); k_both = k_both + 1) 1.1969 + begin 1.1970 + always @(posedge CLK_I or posedge RST_I) 1.1971 + if (RST_I) 1.1972 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0; 1.1973 + else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && POSE_EDGE_IRQ == 1) 1.1974 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]; 1.1975 + else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) && NEGE_EDGE_IRQ == 1) 1.1976 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]; 1.1977 + else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1) 1.1978 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]; 1.1979 + else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1) 1.1980 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]; 1.1981 + else if ( (~IRQ_MASK_BOTH[k_both]) & GPIO_DAT_I_switch[k_both-16] & IRQ_MASK_WR_EN_2 ) 1.1982 + // interrupt mask is being set, so clear edge-capture 1.1983 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0; 1.1984 + else if (EDGE_CAP_WR_EN_2) 1.1985 + // user's writing to the edge register, so update edge capture 1.1986 + // register 1.1987 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY EDGE_CAPTURE_BOTH[k_both] & GPIO_DAT_I_switch[k_both-16]; 1.1988 + end 1.1989 + end 1.1990 + if (INPUT_WIDTH > 24) begin 1.1991 + genvar l_both; 1.1992 + for (l_both = 24; (l_both < INPUT_WIDTH) && (l_both < 32); l_both = l_both + 1) 1.1993 + begin 1.1994 + always @(posedge CLK_I or posedge RST_I) 1.1995 + if (RST_I) 1.1996 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0; 1.1997 + else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && POSE_EDGE_IRQ == 1) 1.1998 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]; 1.1999 + else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) && NEGE_EDGE_IRQ == 1) 1.2000 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]; 1.2001 + else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1) 1.2002 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]; 1.2003 + else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1) 1.2004 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]; 1.2005 + else if ( (~IRQ_MASK_BOTH[l_both]) & GPIO_DAT_I_switch[l_both-24] & IRQ_MASK_WR_EN_3 ) 1.2006 + // interrupt mask is being set, so clear edge-capture 1.2007 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0; 1.2008 + else if (EDGE_CAP_WR_EN_3) 1.2009 + // user's writing to the edge register, so update edge capture 1.2010 + // register 1.2011 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY EDGE_CAPTURE_BOTH[l_both] & GPIO_DAT_I_switch[l_both-24]; 1.2012 + end 1.2013 + end 1.2014 + 1.2015 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.2016 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.2017 + 1.2018 + genvar i_both; 1.2019 + for (i_both = 0; (i_both < INPUT_WIDTH) && (i_both < 8); i_both = i_both + 1) 1.2020 + begin 1.2021 + always @(posedge CLK_I or posedge RST_I) 1.2022 + if (RST_I) 1.2023 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0; 1.2024 + else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && POSE_EDGE_IRQ == 1) 1.2025 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]; 1.2026 + else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && NEGE_EDGE_IRQ == 1) 1.2027 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]; 1.2028 + else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1) 1.2029 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]; 1.2030 + else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1) 1.2031 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]; 1.2032 + else if ( (~IRQ_MASK_BOTH[i_both]) & GPIO_DAT_I_switch[i_both] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0]) 1.2033 + // interrupt mask is being set, so clear edge-capture 1.2034 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0; 1.2035 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[0]) 1.2036 + // user's writing to the edge register, so update edge capture 1.2037 + // register 1.2038 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY EDGE_CAPTURE_BOTH[i_both] & GPIO_DAT_I_switch[i_both]; 1.2039 + end 1.2040 + if (INPUT_WIDTH > 8) begin 1.2041 + genvar j_both; 1.2042 + for (j_both = 8; (j_both < INPUT_WIDTH) && (j_both < 16); j_both = j_both + 1) 1.2043 + begin 1.2044 + always @(posedge CLK_I or posedge RST_I) 1.2045 + if (RST_I) 1.2046 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0; 1.2047 + else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && POSE_EDGE_IRQ == 1) 1.2048 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]; 1.2049 + else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) && NEGE_EDGE_IRQ == 1) 1.2050 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]; 1.2051 + else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1) 1.2052 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]; 1.2053 + else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1) 1.2054 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]; 1.2055 + else if ( (~IRQ_MASK_BOTH[j_both]) & GPIO_DAT_I_switch[j_both-8] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1]) 1.2056 + // interrupt mask is being set, so clear edge-capture 1.2057 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0; 1.2058 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[1]) 1.2059 + // user's writing to the edge register, so update edge capture 1.2060 + // register 1.2061 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY EDGE_CAPTURE_BOTH[j_both] & GPIO_DAT_I_switch[j_both]; 1.2062 + end 1.2063 + end 1.2064 + if (INPUT_WIDTH > 16) begin 1.2065 + genvar k_both; 1.2066 + for (k_both = 16; (k_both < INPUT_WIDTH) && (k_both < 24); k_both = k_both + 1) 1.2067 + begin 1.2068 + always @(posedge CLK_I or posedge RST_I) 1.2069 + if (RST_I) 1.2070 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0; 1.2071 + else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && POSE_EDGE_IRQ == 1) 1.2072 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]; 1.2073 + else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) && NEGE_EDGE_IRQ == 1) 1.2074 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]; 1.2075 + else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1) 1.2076 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]; 1.2077 + else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1) 1.2078 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]; 1.2079 + else if ( (~IRQ_MASK_BOTH[k_both]) & GPIO_DAT_I_switch[k_both-16] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2]) 1.2080 + // interrupt mask is being set, so clear edge-capture 1.2081 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0; 1.2082 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[2]) 1.2083 + // user's writing to the edge register, so update edge capture 1.2084 + // register 1.2085 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY EDGE_CAPTURE_BOTH[k_both] & GPIO_DAT_I_switch[k_both]; 1.2086 + end 1.2087 + end 1.2088 + if (INPUT_WIDTH > 24) begin 1.2089 + genvar l_both; 1.2090 + for (l_both = 24; (l_both < INPUT_WIDTH) && (l_both < 32); l_both = l_both + 1) 1.2091 + begin 1.2092 + always @(posedge CLK_I or posedge RST_I) 1.2093 + if (RST_I) 1.2094 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0; 1.2095 + else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && POSE_EDGE_IRQ == 1) 1.2096 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]; 1.2097 + else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) && NEGE_EDGE_IRQ == 1) 1.2098 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]; 1.2099 + else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1) 1.2100 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]; 1.2101 + else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1) 1.2102 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]; 1.2103 + else if ( (~IRQ_MASK_BOTH[l_both]) & GPIO_DAT_I_switch[l_both-24] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3]) 1.2104 + // interrupt mask is being set, so clear edge-capture 1.2105 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0; 1.2106 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[3]) 1.2107 + // user's writing to the edge register, so update edge capture 1.2108 + // register 1.2109 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY EDGE_CAPTURE_BOTH[l_both] & GPIO_DAT_I_switch[l_both]; 1.2110 + end 1.2111 + end 1.2112 + 1.2113 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.2114 + 1.2115 assign IRQ_O = |(EDGE_CAPTURE_BOTH & IRQ_MASK_BOTH); 1.2116 1.2117 - end else if (IRQ_MODE == 1 && TRISTATE_PORTS == 1) begin 1.2118 + end // if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (EDGE == 1)) 1.2119 + 1.2120 + else if (IRQ_MODE == 1 && TRISTATE_PORTS == 1) begin 1.2121 + 1.2122 assign IRQ_O = |IRQ_TRI_TEMP; 1.2123 - end else 1.2124 + end 1.2125 + 1.2126 + else begin 1.2127 + 1.2128 assign IRQ_O = 1'b0; 1.2129 - endgenerate 1.2130 + end 1.2131 + 1.2132 + endgenerate 1.2133 + 1.2134 1.2135 endmodule 1.2136 `endif // GPIO_V