1.1 diff -r 267b5a25932f -r dfc32cad81ba rtl/verilog/gpio.v 1.2 --- a/rtl/verilog/gpio.v Fri Aug 13 10:41:29 2010 +0100 1.3 +++ b/rtl/verilog/gpio.v Sat Aug 06 01:43:24 2011 +0100 1.4 @@ -1,18 +1,39 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2004 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 +// ================================================================== 1.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.16 +// ------------------------------------------------------------------ 1.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.18 +// ALL RIGHTS RESERVED 1.19 +// ------------------------------------------------------------------ 1.20 +// 1.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.22 +// 1.23 +// Permission: 1.24 +// 1.25 +// Lattice Semiconductor grants permission to use this code 1.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.27 +// Open Source License Agreement. 1.28 +// 1.29 +// Disclaimer: 1.30 // 1.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.34 -// U.S.A email: techsupport@latticesemi.com 1.35 -// =============================================================================/ 1.36 +// Lattice Semiconductor provides no warranty regarding the use or 1.37 +// functionality of this code. It is the user's responsibility to 1.38 +// verify the user’s design for consistency and functionality through 1.39 +// the use of formal verification methods. 1.40 +// 1.41 +// -------------------------------------------------------------------- 1.42 +// 1.43 +// Lattice Semiconductor Corporation 1.44 +// 5555 NE Moore Court 1.45 +// Hillsboro, OR 97214 1.46 +// U.S.A 1.47 +// 1.48 +// TEL: 1-800-Lattice (USA and Canada) 1.49 +// 503-286-8001 (other locations) 1.50 +// 1.51 +// web: http://www.latticesemi.com/ 1.52 +// email: techsupport@latticesemi.com 1.53 +// 1.54 +// -------------------------------------------------------------------- 1.55 // FILE DETAILS 1.56 // Project : GPIO for LM32 1.57 // File : gpio.v 1.58 @@ -34,346 +55,1782 @@ 1.59 // Mod. Date : 11 Oct. 2008 1.60 // Changes Made : Update the Edge Capture Register clean method 1.61 // Make IRQ Mask register readable 1.62 +// 1.63 +// Version : 3.2 1.64 +// Mod. Data : Jun 6, 2010 1.65 +// Changes Made : 1. Provide capability to read/write bytes (when GPIO larger 1.66 +// than 8 bits wide) 1.67 +// 2. Provide capability to use a 32-bit or 8-bit data bus on 1.68 +// the WISHBONE slave port 1.69 +// 3. Perform a big-endian to little-endian conversion in 1.70 +// hardware 1.71 // ============================================================================= 1.72 `ifndef GPIO_V 1.73 `define GPIO_V 1.74 `timescale 1ns/100 ps 1.75 `include "system_conf.v" 1.76 -module gpio #(parameter DATA_WIDTH = 16, 1.77 - parameter INPUT_WIDTH = 16, 1.78 - parameter OUTPUT_WIDTH = 16, 1.79 - parameter IRQ_MODE = 0, 1.80 - parameter LEVEL = 0, 1.81 - parameter EDGE = 0, 1.82 - parameter POSE_EDGE_IRQ = 0, 1.83 - parameter NEGE_EDGE_IRQ = 0, 1.84 - parameter EITHER_EDGE_IRQ = 0, 1.85 - parameter INPUT_PORTS_ONLY = 1, 1.86 - parameter OUTPUT_PORTS_ONLY = 0, 1.87 - parameter BOTH_INPUT_AND_OUTPUT = 0, 1.88 - parameter TRISTATE_PORTS = 0) 1.89 - ( 1.90 - //system clock and reset 1.91 - CLK_I, 1.92 - RST_I, 1.93 - //wishbone interface signals 1.94 - GPIO_ADR_I, 1.95 - GPIO_CYC_I, 1.96 - GPIO_DAT_I, 1.97 - GPIO_SEL_I, 1.98 - GPIO_STB_I, 1.99 - GPIO_WE_I, 1.100 - GPIO_LOCK_I, 1.101 - GPIO_CTI_I, 1.102 - GPIO_BTE_I, 1.103 - GPIO_ACK_O, 1.104 - GPIO_RTY_O, 1.105 - GPIO_DAT_O, 1.106 - GPIO_ERR_O, 1.107 - IRQ_O, //bit_or of all IRQs 1.108 - //PIO side 1.109 - PIO_IN, 1.110 - PIO_OUT, 1.111 - PIO_IO, 1.112 - PIO_BOTH_IN, 1.113 - PIO_BOTH_OUT 1.114 - ); 1.115 - 1.116 -//--------------------------------------------------------------------- 1.117 -// inputs 1.118 - // 1.119 - input CLK_I; 1.120 - input RST_I; 1.121 - input [31:0] GPIO_ADR_I; 1.122 - input GPIO_CYC_I; 1.123 - input [31:0] GPIO_DAT_I; 1.124 - input [3:0] GPIO_SEL_I; 1.125 - input GPIO_STB_I; 1.126 - input GPIO_WE_I; 1.127 - input GPIO_LOCK_I; 1.128 - input [2:0] GPIO_CTI_I; 1.129 - input [1:0] GPIO_BTE_I; 1.130 - input [DATA_WIDTH-1:0] PIO_IN; 1.131 - input [INPUT_WIDTH-1:0] PIO_BOTH_IN; 1.132 -//--------------------------------------------------------------------- 1.133 -// outputs 1.134 -// 1.135 - output GPIO_ACK_O; 1.136 - output GPIO_RTY_O; 1.137 - output [31:0] GPIO_DAT_O; 1.138 - output GPIO_ERR_O; 1.139 - output IRQ_O; 1.140 - output [DATA_WIDTH-1:0] PIO_OUT; 1.141 - output [OUTPUT_WIDTH-1:0] PIO_BOTH_OUT; 1.142 -//---------------- 1.143 -//inout mode 1.144 - inout [DATA_WIDTH-1:0] PIO_IO; 1.145 -//---------------- 1.146 -//process 1.147 +module gpio 1.148 + #( 1.149 + parameter GPIO_WB_DAT_WIDTH = 32, 1.150 + parameter GPIO_WB_ADR_WIDTH = 4, 1.151 + parameter DATA_WIDTH = 16, 1.152 + parameter INPUT_WIDTH = 16, 1.153 + parameter OUTPUT_WIDTH = 16, 1.154 + parameter IRQ_MODE = 0, 1.155 + parameter LEVEL = 0, 1.156 + parameter EDGE = 0, 1.157 + parameter POSE_EDGE_IRQ = 0, 1.158 + parameter NEGE_EDGE_IRQ = 0, 1.159 + parameter EITHER_EDGE_IRQ = 0, 1.160 + parameter INPUT_PORTS_ONLY = 1, 1.161 + parameter OUTPUT_PORTS_ONLY = 0, 1.162 + parameter BOTH_INPUT_AND_OUTPUT = 0, 1.163 + parameter TRISTATE_PORTS = 0 1.164 + ) 1.165 + ( 1.166 + // system clock and reset 1.167 + input CLK_I, 1.168 + input RST_I, 1.169 + 1.170 + // wishbone interface signals 1.171 + input GPIO_CYC_I, 1.172 + input GPIO_STB_I, 1.173 + input GPIO_WE_I, 1.174 + input GPIO_LOCK_I, 1.175 + input [2:0] GPIO_CTI_I, 1.176 + input [1:0] GPIO_BTE_I, 1.177 + input [GPIO_WB_ADR_WIDTH-1:0] GPIO_ADR_I, 1.178 + input [GPIO_WB_DAT_WIDTH-1:0] GPIO_DAT_I, 1.179 + input [GPIO_WB_DAT_WIDTH/8-1:0] GPIO_SEL_I, 1.180 + output reg GPIO_ACK_O, 1.181 + output GPIO_ERR_O, 1.182 + output GPIO_RTY_O, 1.183 + output [GPIO_WB_DAT_WIDTH-1:0] GPIO_DAT_O, 1.184 + 1.185 + output IRQ_O, 1.186 + 1.187 + // PIO side 1.188 + input [DATA_WIDTH-1:0] PIO_IN, 1.189 + input [INPUT_WIDTH-1:0] PIO_BOTH_IN, 1.190 + output [DATA_WIDTH-1:0] PIO_OUT, 1.191 + output [OUTPUT_WIDTH-1:0] PIO_BOTH_OUT, 1.192 + inout [DATA_WIDTH-1:0] PIO_IO 1.193 + ); 1.194 1.195 - parameter UDLY = 1; 1.196 + // The incoming data bus is big-endian and the internal memory-mapped registers of GPIO 1.197 + // component are little-endian. Performing a big-endian to little-endian conversion! 1.198 + wire [GPIO_WB_DAT_WIDTH-1:0] GPIO_DAT_I_switch, GPIO_DAT_O_switch; 1.199 + wire [GPIO_WB_DAT_WIDTH/8-1:0] GPIO_SEL_I_switch; 1.200 + generate 1.201 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.202 + assign GPIO_DAT_I_switch = GPIO_DAT_I; 1.203 + assign GPIO_SEL_I_switch = GPIO_SEL_I; 1.204 + assign GPIO_DAT_O = GPIO_DAT_O_switch; 1.205 + end 1.206 + else begin 1.207 + assign GPIO_DAT_I_switch = {GPIO_DAT_I[7:0], GPIO_DAT_I[15:8], GPIO_DAT_I[23:16], GPIO_DAT_I[31:24]}; 1.208 + assign GPIO_SEL_I_switch = {GPIO_SEL_I[0], GPIO_SEL_I[1], GPIO_SEL_I[2], GPIO_SEL_I[3]}; 1.209 + assign GPIO_DAT_O = {GPIO_DAT_O_switch[7:0], GPIO_DAT_O_switch[15:8], GPIO_DAT_O_switch[23:16], GPIO_DAT_O_switch[31:24]}; 1.210 + end 1.211 + endgenerate 1.212 + 1.213 + reg [OUTPUT_WIDTH-1:0] PIO_DATAO; 1.214 + reg [INPUT_WIDTH-1:0] PIO_DATAI; 1.215 + wire ADR_0, ADR_4, ADR_8, ADR_C; 1.216 + wire [DATA_WIDTH-1:0] tpio_out; 1.217 + 1.218 + wire PIO_DATA_WR_EN; 1.219 + wire PIO_DATA_WR_EN_0, PIO_DATA_WR_EN_1, PIO_DATA_WR_EN_2, PIO_DATA_WR_EN_3; 1.220 1.221 - wire ADR_0; 1.222 - wire ADR_4; 1.223 - wire ADR_8; 1.224 - wire ADR_C; 1.225 - wire read_addr_0; 1.226 - wire read_addr_4; 1.227 - wire read_addr_8; 1.228 - wire read_addr_C; 1.229 - wire GPIO_RTY_O; 1.230 - wire GPIO_ERR_O; 1.231 - wire [31:0] GPIO_DAT_O; 1.232 - wire IRQ_O; 1.233 - wire [DATA_WIDTH-1:0] PIO_OUT; 1.234 - wire [OUTPUT_WIDTH-1:0] PIO_BOTH_OUT; 1.235 - wire [DATA_WIDTH-1:0] tpio_out; 1.236 - wire PIO_DATA_WR_EN; 1.237 - wire PIO_TRI_WR_EN; 1.238 - wire IRQ_MASK_WR_EN; 1.239 - wire EDGE_CAP_WR_EN; 1.240 - wire PIO_DATA_RE_EN; 1.241 - wire PIO_TRI_RE_EN; 1.242 - wire IRQ_MASK_RE_EN; 1.243 - wire [DATA_WIDTH-1:0] IRQ_TRI_TEMP; 1.244 - reg [DATA_WIDTH-1:0] PIO_DATA; 1.245 - reg [DATA_WIDTH-1:0] IRQ_MASK; 1.246 - reg [INPUT_WIDTH-1:0] IRQ_MASK_BOTH; 1.247 - reg [DATA_WIDTH-1:0] IRQ_TEMP; 1.248 - reg [INPUT_WIDTH-1:0] IRQ_TEMP_BOTH; 1.249 - reg [DATA_WIDTH-1:0] EDGE_CAPTURE; 1.250 - reg [INPUT_WIDTH-1:0] EDGE_CAPTURE_BOTH; 1.251 - reg [DATA_WIDTH-1:0] PIO_DATA_DLY; 1.252 - reg [INPUT_WIDTH-1:0] PIO_DATA_DLY_BOTH; 1.253 - reg [OUTPUT_WIDTH-1:0] PIO_DATAO; 1.254 - reg [INPUT_WIDTH-1 :0] PIO_DATAI; 1.255 - reg GPIO_ACK_O; 1.256 - 1.257 + wire PIO_TRI_WR_EN; 1.258 + wire PIO_TRI_WR_EN_0, PIO_TRI_WR_EN_1, PIO_TRI_WR_EN_2, PIO_TRI_WR_EN_3; 1.259 + 1.260 + wire IRQ_MASK_WR_EN; 1.261 + wire IRQ_MASK_WR_EN_0, IRQ_MASK_WR_EN_1, IRQ_MASK_WR_EN_2, IRQ_MASK_WR_EN_3; 1.262 + 1.263 + wire EDGE_CAP_WR_EN; 1.264 + wire EDGE_CAP_WR_EN_0, EDGE_CAP_WR_EN_1, EDGE_CAP_WR_EN_2, EDGE_CAP_WR_EN_3; 1.265 + 1.266 + wire PIO_DATA_RE_EN; 1.267 + wire PIO_TRI_RE_EN; 1.268 + wire IRQ_MASK_RE_EN; 1.269 + wire [DATA_WIDTH-1:0] IRQ_TRI_TEMP; 1.270 + reg [DATA_WIDTH-1:0] PIO_DATA; 1.271 + reg [DATA_WIDTH-1:0] IRQ_MASK; 1.272 + reg [INPUT_WIDTH-1:0] IRQ_MASK_BOTH; 1.273 + reg [DATA_WIDTH-1:0] IRQ_TEMP; 1.274 + reg [INPUT_WIDTH-1:0] IRQ_TEMP_BOTH; 1.275 + reg [DATA_WIDTH-1:0] EDGE_CAPTURE; 1.276 + reg [INPUT_WIDTH-1:0] EDGE_CAPTURE_BOTH; 1.277 + reg [DATA_WIDTH-1:0] PIO_DATA_DLY; 1.278 + reg [INPUT_WIDTH-1:0] PIO_DATA_DLY_BOTH; 1.279 + 1.280 + parameter UDLY = 1; 1.281 + 1.282 assign GPIO_RTY_O = 1'b0; 1.283 assign GPIO_ERR_O = 1'b0; 1.284 - assign ADR_0 = (GPIO_ADR_I[3:0] == 4'b0000 ? 1'b1 : 0); // IO Data 1.285 - assign ADR_4 = (GPIO_ADR_I[3:0] == 4'b0100 ? 1'b1 : 0); // Tri-state Control 1.286 - assign ADR_8 = (GPIO_ADR_I[3:0] == 4'b1000 ? 1'b1 : 0); // IRQ Mask 1.287 - assign ADR_C = (GPIO_ADR_I[3:0] == 4'b1100 ? 1'b1 : 0); // Edge Capture 1.288 + assign ADR_0 = (GPIO_ADR_I[3:2] == 4'b00 ? 1'b1 : 0); // IO Data 1.289 + assign ADR_4 = (GPIO_ADR_I[3:2] == 4'b01 ? 1'b1 : 0); // Tri-state Control 1.290 + assign ADR_8 = (GPIO_ADR_I[3:2] == 4'b10 ? 1'b1 : 0); // IRQ Mask 1.291 + assign ADR_C = (GPIO_ADR_I[3:2] == 4'b11 ? 1'b1 : 0); // Edge Capture 1.292 + 1.293 + always @(posedge CLK_I or posedge RST_I) 1.294 + if(RST_I) 1.295 + GPIO_ACK_O <= #UDLY 1'b0; 1.296 + else if(GPIO_STB_I && (GPIO_ACK_O == 1'b0)) 1.297 + GPIO_ACK_O <= #UDLY 1'b1; 1.298 + else 1.299 + GPIO_ACK_O <= #UDLY 1'b0; 1.300 + 1.301 + 1.302 + generate 1.303 + if (INPUT_PORTS_ONLY == 1) begin 1.304 + always @(posedge CLK_I or posedge RST_I) 1.305 + if (RST_I) 1.306 + PIO_DATA <= #UDLY 0; 1.307 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:2] == 2'b00) 1.308 + PIO_DATA <= #UDLY PIO_IN; 1.309 + end 1.310 + endgenerate 1.311 + 1.312 + generate 1.313 + if (OUTPUT_PORTS_ONLY == 1) begin 1.314 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.315 + genvar ipd_idx; 1.316 + for (ipd_idx = 0; (ipd_idx < DATA_WIDTH) && (ipd_idx < 8); ipd_idx = ipd_idx + 1) 1.317 + begin 1.318 + always @(posedge CLK_I or posedge RST_I) 1.319 + if (RST_I) 1.320 + PIO_DATA[ipd_idx] <= #UDLY 0; 1.321 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000) 1.322 + PIO_DATA[ipd_idx] <= #UDLY GPIO_DAT_I_switch[ipd_idx]; 1.323 + end 1.324 + if (DATA_WIDTH > 8) begin 1.325 + genvar jpd_idx; 1.326 + for (jpd_idx = 8; (jpd_idx < DATA_WIDTH) && (jpd_idx < 16); jpd_idx = jpd_idx + 1) 1.327 + begin 1.328 + always @(posedge CLK_I or posedge RST_I) 1.329 + if (RST_I) 1.330 + PIO_DATA[jpd_idx] <= #UDLY 0; 1.331 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001) 1.332 + PIO_DATA[jpd_idx] <= #UDLY GPIO_DAT_I_switch[jpd_idx-8]; 1.333 + end 1.334 + end 1.335 + if (DATA_WIDTH > 16) begin 1.336 + genvar kpd_idx; 1.337 + for (kpd_idx = 16; (kpd_idx < DATA_WIDTH) && (kpd_idx < 24); kpd_idx = kpd_idx + 1) 1.338 + begin 1.339 + always @(posedge CLK_I or posedge RST_I) 1.340 + if (RST_I) 1.341 + PIO_DATA[kpd_idx] <= #UDLY 0; 1.342 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010) 1.343 + PIO_DATA[kpd_idx] <= #UDLY GPIO_DAT_I_switch[kpd_idx-16]; 1.344 + end 1.345 + end 1.346 + if (DATA_WIDTH > 24) begin 1.347 + genvar lpd_idx; 1.348 + for (lpd_idx = 24; (lpd_idx < DATA_WIDTH) && (lpd_idx < 32); lpd_idx = lpd_idx + 1) 1.349 + begin 1.350 + always @(posedge CLK_I or posedge RST_I) 1.351 + if (RST_I) 1.352 + PIO_DATA[lpd_idx] <= #UDLY 0; 1.353 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011) 1.354 + PIO_DATA[lpd_idx] <= #UDLY GPIO_DAT_I_switch[lpd_idx-24]; 1.355 + end 1.356 + end 1.357 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.358 + 1.359 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.360 + genvar ipd_idx; 1.361 + for (ipd_idx = 0; (ipd_idx < DATA_WIDTH) && (ipd_idx < 8); ipd_idx = ipd_idx + 1) 1.362 + begin 1.363 + always @(posedge CLK_I or posedge RST_I) 1.364 + if (RST_I) 1.365 + PIO_DATA[ipd_idx] <= #UDLY 0; 1.366 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[0]) 1.367 + PIO_DATA[ipd_idx] <= #UDLY GPIO_DAT_I_switch[ipd_idx]; 1.368 + end 1.369 + if (DATA_WIDTH > 8) begin 1.370 + genvar jpd_idx; 1.371 + for (jpd_idx = 8; (jpd_idx < DATA_WIDTH) && (jpd_idx < 16); jpd_idx = jpd_idx + 1) 1.372 + begin 1.373 + always @(posedge CLK_I or posedge RST_I) 1.374 + if (RST_I) 1.375 + PIO_DATA[jpd_idx] <= #UDLY 0; 1.376 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[1]) 1.377 + PIO_DATA[jpd_idx] <= #UDLY GPIO_DAT_I_switch[jpd_idx]; 1.378 + end 1.379 + end 1.380 + if (DATA_WIDTH > 16) begin 1.381 + genvar kpd_idx; 1.382 + for (kpd_idx = 16; (kpd_idx < DATA_WIDTH) && (kpd_idx < 24); kpd_idx = kpd_idx + 1) 1.383 + begin 1.384 + always @(posedge CLK_I or posedge RST_I) 1.385 + if (RST_I) 1.386 + PIO_DATA[kpd_idx] <= #UDLY 0; 1.387 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[2]) 1.388 + PIO_DATA[kpd_idx] <= #UDLY GPIO_DAT_I_switch[kpd_idx]; 1.389 + end 1.390 + end 1.391 + if (DATA_WIDTH > 24) begin 1.392 + genvar lpd_idx; 1.393 + for (lpd_idx = 24; (lpd_idx < DATA_WIDTH) && (lpd_idx < 32); lpd_idx = lpd_idx + 1) 1.394 + begin 1.395 + always @(posedge CLK_I or posedge RST_I) 1.396 + if (RST_I) 1.397 + PIO_DATA[lpd_idx] <= #UDLY 0; 1.398 + else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[3]) 1.399 + PIO_DATA[lpd_idx] <= #UDLY GPIO_DAT_I_switch[lpd_idx]; 1.400 + end 1.401 + end 1.402 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.403 + 1.404 + assign PIO_OUT = PIO_DATA; 1.405 + end 1.406 + endgenerate 1.407 + 1.408 + generate 1.409 + if (BOTH_INPUT_AND_OUTPUT == 1) begin 1.410 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.411 + genvar iopd_idx; 1.412 + for (iopd_idx = 0; (iopd_idx < OUTPUT_WIDTH) && (iopd_idx < 8); iopd_idx = iopd_idx + 1) 1.413 + begin 1.414 + always @(posedge CLK_I or posedge RST_I) 1.415 + if (RST_I) 1.416 + begin 1.417 + PIO_DATAI[iopd_idx] <= #UDLY 0; 1.418 + PIO_DATAO[iopd_idx] <= #UDLY 0; 1.419 + end 1.420 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000) 1.421 + PIO_DATAI[iopd_idx] <= #UDLY PIO_BOTH_IN[iopd_idx]; 1.422 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000) 1.423 + PIO_DATAO[iopd_idx] <= #UDLY GPIO_DAT_I_switch[iopd_idx]; 1.424 + end 1.425 + if (OUTPUT_WIDTH > 8) begin 1.426 + genvar jopd_idx; 1.427 + for (jopd_idx = 8; (jopd_idx < OUTPUT_WIDTH) && (jopd_idx < 16); jopd_idx = jopd_idx + 1) 1.428 + begin 1.429 + always @(posedge CLK_I or posedge RST_I) 1.430 + if (RST_I) 1.431 + begin 1.432 + PIO_DATAI[jopd_idx] <= #UDLY 0; 1.433 + PIO_DATAO[jopd_idx] <= #UDLY 0; 1.434 + end 1.435 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001) 1.436 + PIO_DATAI[jopd_idx] <= #UDLY PIO_BOTH_IN[jopd_idx]; 1.437 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001) 1.438 + PIO_DATAO[jopd_idx] <= #UDLY GPIO_DAT_I_switch[jopd_idx-8]; 1.439 + end 1.440 + end 1.441 + if (OUTPUT_WIDTH > 16) begin 1.442 + genvar kopd_idx; 1.443 + for (kopd_idx = 16; (kopd_idx < OUTPUT_WIDTH) && (kopd_idx < 24); kopd_idx = kopd_idx + 1) 1.444 + begin 1.445 + always @(posedge CLK_I or posedge RST_I) 1.446 + if (RST_I) 1.447 + begin 1.448 + PIO_DATAI[kopd_idx] <= #UDLY 0; 1.449 + PIO_DATAO[kopd_idx] <= #UDLY 0; 1.450 + end 1.451 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010) 1.452 + PIO_DATAI[kopd_idx] <= #UDLY PIO_BOTH_IN[kopd_idx]; 1.453 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010) 1.454 + PIO_DATAO[kopd_idx] <= #UDLY GPIO_DAT_I_switch[kopd_idx-16]; 1.455 + end 1.456 + end 1.457 + if (OUTPUT_WIDTH > 24) begin 1.458 + genvar lopd_idx; 1.459 + for (lopd_idx = 24; (lopd_idx < OUTPUT_WIDTH) && (lopd_idx < 32); lopd_idx = lopd_idx + 1) 1.460 + begin 1.461 + always @(posedge CLK_I or posedge RST_I) 1.462 + if (RST_I) 1.463 + begin 1.464 + PIO_DATAI[lopd_idx] <= #UDLY 0; 1.465 + PIO_DATAO[lopd_idx] <= #UDLY 0; 1.466 + end 1.467 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011) 1.468 + PIO_DATAI[lopd_idx] <= #UDLY PIO_BOTH_IN[lopd_idx]; 1.469 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011) 1.470 + PIO_DATAO[lopd_idx] <= #UDLY GPIO_DAT_I_switch[lopd_idx-24]; 1.471 + end 1.472 + end 1.473 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.474 + 1.475 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.476 + genvar iopd_idx; 1.477 + for (iopd_idx = 0; (iopd_idx < OUTPUT_WIDTH) && (iopd_idx < 8); iopd_idx = iopd_idx + 1) 1.478 + begin 1.479 + always @(posedge CLK_I or posedge RST_I) 1.480 + if (RST_I) 1.481 + begin 1.482 + PIO_DATAI[iopd_idx] <= #UDLY 0; 1.483 + PIO_DATAO[iopd_idx] <= #UDLY 0; 1.484 + end 1.485 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[0]) 1.486 + PIO_DATAI[iopd_idx] <= #UDLY PIO_BOTH_IN[iopd_idx]; 1.487 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[0]) 1.488 + PIO_DATAO[iopd_idx] <= #UDLY GPIO_DAT_I_switch[iopd_idx]; 1.489 + end 1.490 + if (OUTPUT_WIDTH > 8) begin 1.491 + genvar jopd_idx; 1.492 + for (jopd_idx = 8; (jopd_idx < OUTPUT_WIDTH) && (jopd_idx < 16); jopd_idx = jopd_idx + 1) 1.493 + begin 1.494 + always @(posedge CLK_I or posedge RST_I) 1.495 + if (RST_I) 1.496 + begin 1.497 + PIO_DATAI[jopd_idx] <= #UDLY 0; 1.498 + PIO_DATAO[jopd_idx] <= #UDLY 0; 1.499 + end 1.500 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[1]) 1.501 + PIO_DATAI[jopd_idx] <= #UDLY PIO_BOTH_IN[jopd_idx]; 1.502 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[1]) 1.503 + PIO_DATAO[jopd_idx] <= #UDLY GPIO_DAT_I_switch[jopd_idx]; 1.504 + end 1.505 + end 1.506 + if (OUTPUT_WIDTH > 16) begin 1.507 + genvar kopd_idx; 1.508 + for (kopd_idx = 16; (kopd_idx < OUTPUT_WIDTH) && (kopd_idx < 24); kopd_idx = kopd_idx + 1) 1.509 + begin 1.510 + always @(posedge CLK_I or posedge RST_I) 1.511 + if (RST_I) 1.512 + begin 1.513 + PIO_DATAI[kopd_idx] <= #UDLY 0; 1.514 + PIO_DATAO[kopd_idx] <= #UDLY 0; 1.515 + end 1.516 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[2]) 1.517 + PIO_DATAI[kopd_idx] <= #UDLY PIO_BOTH_IN[kopd_idx]; 1.518 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[2]) 1.519 + PIO_DATAO[kopd_idx] <= #UDLY GPIO_DAT_I_switch[kopd_idx]; 1.520 + end 1.521 + end 1.522 + if (OUTPUT_WIDTH > 24) begin 1.523 + genvar lopd_idx; 1.524 + for (lopd_idx = 24; (lopd_idx < OUTPUT_WIDTH) && (lopd_idx < 32); lopd_idx = lopd_idx + 1) 1.525 + begin 1.526 + always @(posedge CLK_I or posedge RST_I) 1.527 + if (RST_I) 1.528 + begin 1.529 + PIO_DATAI[lopd_idx] <= #UDLY 0; 1.530 + PIO_DATAO[lopd_idx] <= #UDLY 0; 1.531 + end 1.532 + else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[3]) 1.533 + PIO_DATAI[lopd_idx] <= #UDLY PIO_BOTH_IN[lopd_idx]; 1.534 + else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[3]) 1.535 + PIO_DATAO[lopd_idx] <= #UDLY GPIO_DAT_I_switch[lopd_idx]; 1.536 + end 1.537 + end 1.538 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.539 + 1.540 + assign PIO_BOTH_OUT = PIO_DATAO[OUTPUT_WIDTH-1:0]; 1.541 + end 1.542 + endgenerate 1.543 + 1.544 + assign PIO_DATA_RE_EN = GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b00); 1.545 + 1.546 + assign PIO_TRI_RE_EN = GPIO_STB_I && GPIO_ACK_O && !GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b01); 1.547 + 1.548 + assign IRQ_MASK_RE_EN = GPIO_STB_I && GPIO_ACK_O && !GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b10); 1.549 + 1.550 + assign PIO_DATA_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b00); 1.551 + generate 1.552 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.553 + assign PIO_DATA_WR_EN_0 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000; 1.554 + assign PIO_DATA_WR_EN_1 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001; 1.555 + assign PIO_DATA_WR_EN_2 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010; 1.556 + assign PIO_DATA_WR_EN_3 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011; 1.557 + end 1.558 + endgenerate 1.559 + 1.560 + assign PIO_TRI_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (GPIO_ADR_I[3:2] == 4'b01); 1.561 + generate 1.562 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.563 + assign PIO_TRI_WR_EN_0 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0100; 1.564 + assign PIO_TRI_WR_EN_1 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0101; 1.565 + assign PIO_TRI_WR_EN_2 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0110; 1.566 + assign PIO_TRI_WR_EN_3 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0111; 1.567 + end 1.568 + endgenerate 1.569 + 1.570 + assign IRQ_MASK_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b10); 1.571 + generate 1.572 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.573 + assign IRQ_MASK_WR_EN_0 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1000; 1.574 + assign IRQ_MASK_WR_EN_1 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1001; 1.575 + assign IRQ_MASK_WR_EN_2 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1010; 1.576 + assign IRQ_MASK_WR_EN_3 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1011; 1.577 + end 1.578 + endgenerate 1.579 + 1.580 + assign EDGE_CAP_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b11); 1.581 + generate 1.582 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.583 + assign EDGE_CAP_WR_EN_0 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1100; 1.584 + assign EDGE_CAP_WR_EN_1 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1101; 1.585 + assign EDGE_CAP_WR_EN_2 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1110; 1.586 + assign EDGE_CAP_WR_EN_3 = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1111; 1.587 + end 1.588 + endgenerate 1.589 + 1.590 + generate 1.591 + 1.592 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.593 + 1.594 + genvar iti; 1.595 + for (iti = 0; (iti < DATA_WIDTH) && (iti < 8); iti = iti + 1) 1.596 + begin : itio_inst 1.597 + TRI_PIO 1.598 + #(.DATA_WIDTH(1), 1.599 + .IRQ_MODE(IRQ_MODE), 1.600 + .LEVEL(LEVEL), 1.601 + .EDGE(EDGE), 1.602 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.603 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.604 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.605 + TP 1.606 + (.CLK_I(CLK_I), 1.607 + .RST_I(RST_I), 1.608 + .DAT_I(GPIO_DAT_I_switch[iti]), 1.609 + .DAT_O(tpio_out[iti]), 1.610 + .PIO_IO(PIO_IO[iti]), 1.611 + .IRQ_O(IRQ_TRI_TEMP[iti]), 1.612 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN_0), 1.613 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.614 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN_0), 1.615 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.616 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_0), 1.617 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.618 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_0)); 1.619 + end 1.620 + if (DATA_WIDTH > 8) begin 1.621 + genvar jti; 1.622 + for (jti = 8; (jti < DATA_WIDTH) && (jti < 16); jti = jti + 1) 1.623 + begin : jtio_inst 1.624 + TRI_PIO 1.625 + #(.DATA_WIDTH(1), 1.626 + .IRQ_MODE(IRQ_MODE), 1.627 + .LEVEL(LEVEL), 1.628 + .EDGE(EDGE), 1.629 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.630 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.631 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.632 + TP 1.633 + (.CLK_I(CLK_I), 1.634 + .RST_I(RST_I), 1.635 + .DAT_I(GPIO_DAT_I_switch[jti-8]), 1.636 + .DAT_O(tpio_out[jti]), 1.637 + .PIO_IO(PIO_IO[jti]), 1.638 + .IRQ_O(IRQ_TRI_TEMP[jti]), 1.639 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN_1), 1.640 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.641 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN_1), 1.642 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.643 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_1), 1.644 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.645 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_1)); 1.646 + end 1.647 + end 1.648 + if (DATA_WIDTH > 16) begin 1.649 + genvar kti; 1.650 + for (kti = 16; (kti < DATA_WIDTH) && (kti < 24); kti = kti + 1) 1.651 + begin : ktio_inst 1.652 + TRI_PIO 1.653 + #(.DATA_WIDTH(1), 1.654 + .IRQ_MODE(IRQ_MODE), 1.655 + .LEVEL(LEVEL), 1.656 + .EDGE(EDGE), 1.657 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.658 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.659 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.660 + TP 1.661 + (.CLK_I(CLK_I), 1.662 + .RST_I(RST_I), 1.663 + .DAT_I(GPIO_DAT_I_switch[kti-16]), 1.664 + .DAT_O(tpio_out[kti]), 1.665 + .PIO_IO(PIO_IO[kti]), 1.666 + .IRQ_O(IRQ_TRI_TEMP[kti]), 1.667 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN_2), 1.668 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.669 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN_2), 1.670 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.671 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_2), 1.672 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.673 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_2)); 1.674 + end 1.675 + end 1.676 + if (DATA_WIDTH > 24) begin 1.677 + genvar lti; 1.678 + for (lti = 24; (lti < DATA_WIDTH) && (lti < 32); lti = lti + 1) 1.679 + begin : ltio_inst 1.680 + TRI_PIO 1.681 + #(.DATA_WIDTH(1), 1.682 + .IRQ_MODE(IRQ_MODE), 1.683 + .LEVEL(LEVEL), 1.684 + .EDGE(EDGE), 1.685 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.686 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.687 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.688 + TP 1.689 + (.CLK_I(CLK_I), 1.690 + .RST_I(RST_I), 1.691 + .DAT_I(GPIO_DAT_I_switch[lti-24]), 1.692 + .DAT_O(tpio_out[lti]), 1.693 + .PIO_IO(PIO_IO[lti]), 1.694 + .IRQ_O(IRQ_TRI_TEMP[lti]), 1.695 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN_3), 1.696 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.697 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN_3), 1.698 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.699 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_3), 1.700 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.701 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_3)); 1.702 + end 1.703 + end 1.704 + 1.705 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.706 + 1.707 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.708 + 1.709 + genvar iti; 1.710 + for (iti = 0; (iti < DATA_WIDTH) && (iti < 8); iti = iti + 1) 1.711 + begin : itio_inst 1.712 + TRI_PIO 1.713 + #(.DATA_WIDTH(1), 1.714 + .IRQ_MODE(IRQ_MODE), 1.715 + .LEVEL(LEVEL), 1.716 + .EDGE(EDGE), 1.717 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.718 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.719 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.720 + TP 1.721 + (.CLK_I(CLK_I), 1.722 + .RST_I(RST_I), 1.723 + .DAT_I(GPIO_DAT_I_switch[iti]), 1.724 + .DAT_O(tpio_out[iti]), 1.725 + .PIO_IO(PIO_IO[iti]), 1.726 + .IRQ_O(IRQ_TRI_TEMP[iti]), 1.727 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[0]), 1.728 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.729 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[0]), 1.730 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.731 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[0]), 1.732 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.733 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[0])); 1.734 + end 1.735 + if (DATA_WIDTH > 8) begin 1.736 + genvar jti; 1.737 + for (jti = 8; (jti < DATA_WIDTH) && (jti < 16); jti = jti + 1) 1.738 + begin : jtio_inst 1.739 + TRI_PIO 1.740 + #(.DATA_WIDTH(1), 1.741 + .IRQ_MODE(IRQ_MODE), 1.742 + .LEVEL(LEVEL), 1.743 + .EDGE(EDGE), 1.744 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.745 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.746 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.747 + TP 1.748 + (.CLK_I(CLK_I), 1.749 + .RST_I(RST_I), 1.750 + .DAT_I(GPIO_DAT_I_switch[jti]), 1.751 + .DAT_O(tpio_out[jti]), 1.752 + .PIO_IO(PIO_IO[jti]), 1.753 + .IRQ_O(IRQ_TRI_TEMP[jti]), 1.754 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[1]), 1.755 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.756 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[1]), 1.757 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.758 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[1]), 1.759 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.760 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[1])); 1.761 + end 1.762 + end 1.763 + if (DATA_WIDTH > 16) begin 1.764 + genvar kti; 1.765 + for (kti = 16; (kti < DATA_WIDTH) && (kti < 24); kti = kti + 1) 1.766 + begin : ktio_inst 1.767 + TRI_PIO 1.768 + #(.DATA_WIDTH(1), 1.769 + .IRQ_MODE(IRQ_MODE), 1.770 + .LEVEL(LEVEL), 1.771 + .EDGE(EDGE), 1.772 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.773 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.774 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.775 + TP 1.776 + (.CLK_I(CLK_I), 1.777 + .RST_I(RST_I), 1.778 + .DAT_I(GPIO_DAT_I_switch[kti]), 1.779 + .DAT_O(tpio_out[kti]), 1.780 + .PIO_IO(PIO_IO[kti]), 1.781 + .IRQ_O(IRQ_TRI_TEMP[kti]), 1.782 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[2]), 1.783 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.784 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[2]), 1.785 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.786 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[2]), 1.787 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.788 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[2])); 1.789 + end 1.790 + end 1.791 + if (DATA_WIDTH > 24) begin 1.792 + genvar lti; 1.793 + for (lti = 24; (lti < DATA_WIDTH) && (lti < 32); lti = lti + 1) 1.794 + begin : ltio_inst 1.795 + TRI_PIO 1.796 + #(.DATA_WIDTH(1), 1.797 + .IRQ_MODE(IRQ_MODE), 1.798 + .LEVEL(LEVEL), 1.799 + .EDGE(EDGE), 1.800 + .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.801 + .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.802 + .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.803 + TP 1.804 + (.CLK_I(CLK_I), 1.805 + .RST_I(RST_I), 1.806 + .DAT_I(GPIO_DAT_I_switch[lti]), 1.807 + .DAT_O(tpio_out[lti]), 1.808 + .PIO_IO(PIO_IO[lti]), 1.809 + .IRQ_O(IRQ_TRI_TEMP[lti]), 1.810 + .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[3]), 1.811 + .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.812 + .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[3]), 1.813 + .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.814 + .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[3]), 1.815 + .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.816 + .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[3])); 1.817 + end 1.818 + end 1.819 + 1.820 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.821 + 1.822 + endgenerate 1.823 + 1.824 + 1.825 + wire read_addr_0, read_addr_4, read_addr_8, read_addr_C; 1.826 assign read_addr_0 = (ADR_0 & GPIO_STB_I & ~GPIO_WE_I) ; 1.827 assign read_addr_4 = (ADR_4 & GPIO_STB_I & ~GPIO_WE_I) ; 1.828 assign read_addr_8 = (IRQ_MODE == 1 && (ADR_8 & GPIO_STB_I & ~GPIO_WE_I)); 1.829 - assign read_addr_C = (IRQ_MODE == 1 && (ADR_C & GPIO_STB_I & ~GPIO_WE_I)); 1.830 - 1.831 - always @(posedge CLK_I or posedge RST_I) 1.832 - if(RST_I) 1.833 - GPIO_ACK_O <= #UDLY 1'b0; 1.834 - else if( GPIO_STB_I && !GPIO_ACK_O) 1.835 - GPIO_ACK_O <= #UDLY 1'b1; 1.836 - else 1.837 - GPIO_ACK_O <= #UDLY 1'b0; 1.838 - 1.839 - generate 1.840 - if (INPUT_PORTS_ONLY == 1) begin 1.841 - always @(posedge CLK_I or posedge RST_I) 1.842 - if (RST_I) 1.843 - PIO_DATA <= #UDLY 0; 1.844 - else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I == 4'b1111) 1.845 - PIO_DATA <= #UDLY PIO_IN; 1.846 - end 1.847 - endgenerate 1.848 - 1.849 - generate 1.850 - if (OUTPUT_PORTS_ONLY == 1) begin 1.851 - always @(posedge CLK_I or posedge RST_I) 1.852 - if (RST_I) 1.853 - PIO_DATA <= #UDLY 0; 1.854 - else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I == 4'b1111) 1.855 - PIO_DATA <= #UDLY GPIO_DAT_I[DATA_WIDTH-1:0]; 1.856 - 1.857 - assign PIO_OUT = PIO_DATA; 1.858 - end 1.859 - endgenerate 1.860 + assign read_addr_C = (IRQ_MODE == 1 && (ADR_C & GPIO_STB_I & ~GPIO_WE_I)); 1.861 1.862 - generate 1.863 - if (BOTH_INPUT_AND_OUTPUT == 1) begin 1.864 - always @(posedge CLK_I or posedge RST_I) 1.865 - if (RST_I) begin 1.866 - PIO_DATAI <= #UDLY 0; 1.867 - PIO_DATAO <= #UDLY 0; 1.868 - end else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111) 1.869 - PIO_DATAI <= #UDLY PIO_BOTH_IN; 1.870 - else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111) 1.871 - PIO_DATAO <= #UDLY GPIO_DAT_I[OUTPUT_WIDTH-1:0]; 1.872 - 1.873 - assign PIO_BOTH_OUT = PIO_DATAO[OUTPUT_WIDTH-1:0]; 1.874 - end 1.875 - endgenerate 1.876 - 1.877 - assign PIO_DATA_RE_EN = GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111; 1.878 - assign PIO_TRI_RE_EN = GPIO_STB_I && GPIO_ACK_O && !GPIO_WE_I && (ADR_4 == 1'b1) && GPIO_SEL_I == 4'b1111; 1.879 - assign IRQ_MASK_RE_EN = GPIO_STB_I && GPIO_ACK_O && !GPIO_WE_I && (ADR_8 == 1'b1) && GPIO_SEL_I == 4'b1111; 1.880 - assign PIO_DATA_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111; 1.881 - assign PIO_TRI_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (ADR_4 == 1'b1) && GPIO_SEL_I == 4'b1111; 1.882 - assign IRQ_MASK_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (ADR_8 == 1'b1) && GPIO_SEL_I == 4'b1111; 1.883 - assign EDGE_CAP_WR_EN = GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (ADR_C == 1'b1) && GPIO_SEL_I == 4'b1111; 1.884 + wire read_byte_0, read_byte_1, read_byte_2, read_byte_3; 1.885 + wire read_byte_4, read_byte_5, read_byte_6, read_byte_7; 1.886 + wire read_byte_8, read_byte_9, read_byte_A, read_byte_B; 1.887 + wire read_byte_C, read_byte_D, read_byte_E, read_byte_F; 1.888 + assign read_byte_0 = ((GPIO_ADR_I[3:0] == 4'b0000) & GPIO_STB_I & ~GPIO_WE_I) ; 1.889 + assign read_byte_1 = ((GPIO_ADR_I[3:0] == 4'b0001) & GPIO_STB_I & ~GPIO_WE_I) ; 1.890 + assign read_byte_2 = ((GPIO_ADR_I[3:0] == 4'b0010) & GPIO_STB_I & ~GPIO_WE_I) ; 1.891 + assign read_byte_3 = ((GPIO_ADR_I[3:0] == 4'b0011) & GPIO_STB_I & ~GPIO_WE_I) ; 1.892 + assign read_byte_4 = ((GPIO_ADR_I[3:0] == 4'b0100) & GPIO_STB_I & ~GPIO_WE_I) ; 1.893 + assign read_byte_5 = ((GPIO_ADR_I[3:0] == 4'b0101) & GPIO_STB_I & ~GPIO_WE_I) ; 1.894 + assign read_byte_6 = ((GPIO_ADR_I[3:0] == 4'b0110) & GPIO_STB_I & ~GPIO_WE_I) ; 1.895 + assign read_byte_7 = ((GPIO_ADR_I[3:0] == 4'b0111) & GPIO_STB_I & ~GPIO_WE_I) ; 1.896 + assign read_byte_8 = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1000) & GPIO_STB_I & ~GPIO_WE_I)); 1.897 + assign read_byte_9 = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1001) & GPIO_STB_I & ~GPIO_WE_I)); 1.898 + assign read_byte_A = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1010) & GPIO_STB_I & ~GPIO_WE_I)); 1.899 + assign read_byte_B = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1011) & GPIO_STB_I & ~GPIO_WE_I)); 1.900 + assign read_byte_C = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1100) & GPIO_STB_I & ~GPIO_WE_I)); 1.901 + assign read_byte_D = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1101) & GPIO_STB_I & ~GPIO_WE_I)); 1.902 + assign read_byte_E = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1110) & GPIO_STB_I & ~GPIO_WE_I)); 1.903 + assign read_byte_F = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1111) & GPIO_STB_I & ~GPIO_WE_I)); 1.904 1.905 generate 1.906 - genvar ti; 1.907 - for (ti = 0 ; ti < DATA_WIDTH; ti = ti + 1) 1.908 - begin : tio_inst 1.909 - TRI_PIO #(.DATA_WIDTH(DATA_WIDTH), 1.910 - .IRQ_MODE(IRQ_MODE), 1.911 - .LEVEL(LEVEL), 1.912 - .EDGE(EDGE), 1.913 - .POSE_EDGE_IRQ(POSE_EDGE_IRQ), 1.914 - .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ), 1.915 - .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ)) 1.916 - TP (.CLK_I(CLK_I), 1.917 - .RST_I(RST_I), 1.918 - .DAT_I(GPIO_DAT_I[ti]), 1.919 - .DAT_O(tpio_out[ti]), 1.920 - .PIO_IO(PIO_IO[ti]), 1.921 - .IRQ_O(IRQ_TRI_TEMP[ti]), 1.922 - .PIO_TRI_WR_EN(PIO_TRI_WR_EN), 1.923 - .PIO_TRI_RE_EN(PIO_TRI_RE_EN), 1.924 - .PIO_DATA_WR_EN(PIO_DATA_WR_EN), 1.925 - .PIO_DATA_RE_EN(PIO_DATA_RE_EN), 1.926 - .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN), 1.927 - .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN), 1.928 - .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN)); 1.929 - end 1.930 - endgenerate 1.931 1.932 - generate 1.933 - if (INPUT_PORTS_ONLY == 1) 1.934 - assign GPIO_DAT_O = read_addr_0 ? PIO_DATA : 1.935 - read_addr_8 ? IRQ_MASK : 1.936 - read_addr_C ? EDGE_CAPTURE : 1.937 - 0; 1.938 - else if (BOTH_INPUT_AND_OUTPUT == 1) 1.939 - assign GPIO_DAT_O = read_addr_0 ? PIO_DATAI : 1.940 - read_addr_8 ? IRQ_MASK_BOTH : 1.941 - read_addr_C ? EDGE_CAPTURE_BOTH : 1.942 - 0; 1.943 - else if (TRISTATE_PORTS == 1) 1.944 - assign GPIO_DAT_O = read_addr_0 ? tpio_out : 1.945 - read_addr_4 ? tpio_out : 1.946 - read_addr_8 ? tpio_out : 1.947 - read_addr_C ? IRQ_TRI_TEMP : 1.948 - 0; 1.949 - else 1.950 - assign GPIO_DAT_O = 0; 1.951 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.952 + 1.953 + if (INPUT_PORTS_ONLY == 1) begin 1.954 + if (DATA_WIDTH > 24) 1.955 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[ 7: 0] : 1.956 + read_byte_1 ? PIO_DATA[15: 8] : 1.957 + read_byte_2 ? PIO_DATA[23:16] : 1.958 + read_byte_3 ? PIO_DATA[DATA_WIDTH-1:24] : 1.959 + read_byte_8 ? IRQ_MASK[ 7: 0] : 1.960 + read_byte_9 ? IRQ_MASK[15: 8] : 1.961 + read_byte_A ? IRQ_MASK[23:16] : 1.962 + read_byte_B ? IRQ_MASK[DATA_WIDTH-1:24] : 1.963 + read_byte_C ? EDGE_CAPTURE[ 7: 0] : 1.964 + read_byte_D ? EDGE_CAPTURE[15: 8] : 1.965 + read_byte_E ? EDGE_CAPTURE[23:16] : 1.966 + read_byte_F ? EDGE_CAPTURE[DATA_WIDTH-1:24] : 1.967 + 0; 1.968 + else if (DATA_WIDTH > 16) 1.969 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[ 7: 0] : 1.970 + read_byte_1 ? PIO_DATA[15: 8] : 1.971 + read_byte_2 ? PIO_DATA[DATA_WIDTH-1:16] : 1.972 + read_byte_3 ? 8'h00 : 1.973 + read_byte_8 ? IRQ_MASK[ 7: 0] : 1.974 + read_byte_9 ? IRQ_MASK[15: 8] : 1.975 + read_byte_A ? IRQ_MASK[DATA_WIDTH-1:16] : 1.976 + read_byte_B ? 8'h00 : 1.977 + read_byte_C ? EDGE_CAPTURE[ 7: 0] : 1.978 + read_byte_D ? EDGE_CAPTURE[15: 8] : 1.979 + read_byte_E ? EDGE_CAPTURE[DATA_WIDTH-1:16] : 1.980 + read_byte_F ? 8'h00 : 1.981 + 0; 1.982 + else if (DATA_WIDTH > 8) 1.983 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[ 7: 0] : 1.984 + read_byte_1 ? PIO_DATA[DATA_WIDTH-1: 8] : 1.985 + read_byte_2 ? 8'h00 : 1.986 + read_byte_3 ? 8'h00 : 1.987 + read_byte_8 ? IRQ_MASK[ 7: 0] : 1.988 + read_byte_9 ? IRQ_MASK[DATA_WIDTH-1: 8] : 1.989 + read_byte_A ? 8'h00 : 1.990 + read_byte_B ? 8'h00 : 1.991 + read_byte_C ? EDGE_CAPTURE[ 7: 0] : 1.992 + read_byte_D ? EDGE_CAPTURE[DATA_WIDTH-1: 8] : 1.993 + read_byte_E ? 8'h00 : 1.994 + read_byte_F ? 8'h00 : 1.995 + 0; 1.996 + else 1.997 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[DATA_WIDTH-1: 0] : 1.998 + read_byte_1 ? 8'h00 : 1.999 + read_byte_2 ? 8'h00 : 1.1000 + read_byte_3 ? 8'h00 : 1.1001 + read_byte_8 ? IRQ_MASK[DATA_WIDTH-1: 0] : 1.1002 + read_byte_9 ? 8'h00 : 1.1003 + read_byte_A ? 8'h00 : 1.1004 + read_byte_B ? 8'h00 : 1.1005 + read_byte_C ? EDGE_CAPTURE[DATA_WIDTH-1: 0] : 1.1006 + read_byte_D ? 8'h00 : 1.1007 + read_byte_E ? 8'h00 : 1.1008 + read_byte_F ? 8'h00 : 1.1009 + 0; 1.1010 + end 1.1011 + else if (BOTH_INPUT_AND_OUTPUT == 1) begin 1.1012 + if (INPUT_WIDTH > 24) 1.1013 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[ 7: 0] : 1.1014 + read_byte_1 ? PIO_DATAI[15: 8] : 1.1015 + read_byte_2 ? PIO_DATAI[23:16] : 1.1016 + read_byte_3 ? PIO_DATAI[INPUT_WIDTH-1:24] : 1.1017 + read_byte_8 ? IRQ_MASK_BOTH[ 7: 0] : 1.1018 + read_byte_9 ? IRQ_MASK_BOTH[15: 8] : 1.1019 + read_byte_A ? IRQ_MASK_BOTH[23:16] : 1.1020 + read_byte_B ? IRQ_MASK_BOTH[INPUT_WIDTH-1:24] : 1.1021 + read_byte_C ? EDGE_CAPTURE_BOTH[ 7: 0] : 1.1022 + read_byte_D ? EDGE_CAPTURE_BOTH[15: 8] : 1.1023 + read_byte_E ? EDGE_CAPTURE_BOTH[23:16] : 1.1024 + read_byte_F ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1:24] : 1.1025 + 0; 1.1026 + else if (INPUT_WIDTH > 16) 1.1027 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[ 7: 0] : 1.1028 + read_byte_1 ? PIO_DATAI[15: 8] : 1.1029 + read_byte_2 ? PIO_DATAI[INPUT_WIDTH-1:16] : 1.1030 + read_byte_3 ? 8'h00 : 1.1031 + read_byte_8 ? IRQ_MASK_BOTH[ 7: 0] : 1.1032 + read_byte_9 ? IRQ_MASK_BOTH[15: 8] : 1.1033 + read_byte_A ? IRQ_MASK_BOTH[INPUT_WIDTH-1:16] : 1.1034 + read_byte_B ? 8'h00 : 1.1035 + read_byte_C ? EDGE_CAPTURE_BOTH[ 7: 0] : 1.1036 + read_byte_D ? EDGE_CAPTURE_BOTH[15: 8] : 1.1037 + read_byte_E ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1:16] : 1.1038 + read_byte_F ? 8'h00 : 1.1039 + 0; 1.1040 + else if (INPUT_WIDTH > 8) 1.1041 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[ 7: 0] : 1.1042 + read_byte_1 ? PIO_DATAI[INPUT_WIDTH-1: 8] : 1.1043 + read_byte_2 ? 8'h00 : 1.1044 + read_byte_3 ? 8'h00 : 1.1045 + read_byte_8 ? IRQ_MASK_BOTH[ 7: 0] : 1.1046 + read_byte_9 ? IRQ_MASK_BOTH[INPUT_WIDTH-1: 8] : 1.1047 + read_byte_A ? 8'h00 : 1.1048 + read_byte_B ? 8'h00 : 1.1049 + read_byte_C ? EDGE_CAPTURE_BOTH[ 7: 0] : 1.1050 + read_byte_D ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1: 8] : 1.1051 + read_byte_E ? 8'h00 : 1.1052 + read_byte_F ? 8'h00 : 1.1053 + 0; 1.1054 + else 1.1055 + assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[INPUT_WIDTH-1: 0] : 1.1056 + read_byte_1 ? 8'h00 : 1.1057 + read_byte_2 ? 8'h00 : 1.1058 + read_byte_3 ? 8'h00 : 1.1059 + read_byte_8 ? IRQ_MASK_BOTH[INPUT_WIDTH-1: 0] : 1.1060 + read_byte_9 ? 8'h00 : 1.1061 + read_byte_A ? 8'h00 : 1.1062 + read_byte_B ? 8'h00 : 1.1063 + read_byte_C ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1: 0] : 1.1064 + read_byte_D ? 8'h00 : 1.1065 + read_byte_E ? 8'h00 : 1.1066 + read_byte_F ? 8'h00 : 1.1067 + 0; 1.1068 + end 1.1069 + else if (TRISTATE_PORTS == 1) begin 1.1070 + if (DATA_WIDTH > 24) 1.1071 + assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[ 7: 0] : 1.1072 + read_byte_1 ? tpio_out[15: 8] : 1.1073 + read_byte_2 ? tpio_out[23:16] : 1.1074 + read_byte_3 ? tpio_out[DATA_WIDTH-1:24] : 1.1075 + read_byte_4 ? tpio_out[ 7: 0] : 1.1076 + read_byte_5 ? tpio_out[15: 8] : 1.1077 + read_byte_6 ? tpio_out[23:16] : 1.1078 + read_byte_7 ? tpio_out[DATA_WIDTH-1:24] : 1.1079 + read_byte_8 ? tpio_out[ 7: 0] : 1.1080 + read_byte_9 ? tpio_out[15: 8] : 1.1081 + read_byte_A ? tpio_out[23:16] : 1.1082 + read_byte_B ? tpio_out[DATA_WIDTH-1:24] : 1.1083 + read_byte_C ? IRQ_TRI_TEMP[ 7: 0] : 1.1084 + read_byte_D ? IRQ_TRI_TEMP[15: 8] : 1.1085 + read_byte_E ? IRQ_TRI_TEMP[23:16] : 1.1086 + read_byte_F ? IRQ_TRI_TEMP[DATA_WIDTH-1:24] : 1.1087 + 0; 1.1088 + else if (DATA_WIDTH > 16) 1.1089 + assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[ 7: 0] : 1.1090 + read_byte_1 ? tpio_out[15: 8] : 1.1091 + read_byte_2 ? tpio_out[DATA_WIDTH-1:16] : 1.1092 + read_byte_3 ? 8'h00 : 1.1093 + read_byte_4 ? tpio_out[ 7: 0] : 1.1094 + read_byte_5 ? tpio_out[15: 8] : 1.1095 + read_byte_6 ? tpio_out[DATA_WIDTH-1:16] : 1.1096 + read_byte_7 ? 8'h00 : 1.1097 + read_byte_8 ? tpio_out[ 7: 0] : 1.1098 + read_byte_9 ? tpio_out[15: 8] : 1.1099 + read_byte_A ? tpio_out[DATA_WIDTH-1:16] : 1.1100 + read_byte_B ? 8'h00 : 1.1101 + read_byte_C ? IRQ_TRI_TEMP[ 7: 0] : 1.1102 + read_byte_D ? IRQ_TRI_TEMP[15: 8] : 1.1103 + read_byte_E ? IRQ_TRI_TEMP[DATA_WIDTH-1:16] : 1.1104 + read_byte_F ? 8'h00 : 1.1105 + 0; 1.1106 + else if (DATA_WIDTH > 8) 1.1107 + assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[ 7: 0] : 1.1108 + read_byte_1 ? tpio_out[DATA_WIDTH-1: 8] : 1.1109 + read_byte_2 ? 8'h00 : 1.1110 + read_byte_3 ? 8'h00 : 1.1111 + read_byte_4 ? tpio_out[ 7: 0] : 1.1112 + read_byte_5 ? tpio_out[DATA_WIDTH-1: 8] : 1.1113 + read_byte_6 ? 8'h00 : 1.1114 + read_byte_7 ? 8'h00 : 1.1115 + read_byte_8 ? tpio_out[ 7: 0] : 1.1116 + read_byte_9 ? tpio_out[DATA_WIDTH-1: 8] : 1.1117 + read_byte_A ? 8'h00 : 1.1118 + read_byte_B ? 8'h00 : 1.1119 + read_byte_C ? IRQ_TRI_TEMP[ 7: 0] : 1.1120 + read_byte_D ? IRQ_TRI_TEMP[DATA_WIDTH-1: 8] : 1.1121 + read_byte_E ? 8'h00 : 1.1122 + read_byte_F ? 8'h00 : 1.1123 + 0; 1.1124 + else 1.1125 + assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[DATA_WIDTH-1: 0] : 1.1126 + read_byte_1 ? 8'h00 : 1.1127 + read_byte_2 ? 8'h00 : 1.1128 + read_byte_3 ? 8'h00 : 1.1129 + read_byte_4 ? tpio_out[DATA_WIDTH-1: 0] : 1.1130 + read_byte_5 ? 8'h00 : 1.1131 + read_byte_6 ? 8'h00 : 1.1132 + read_byte_7 ? 8'h00 : 1.1133 + read_byte_8 ? tpio_out[DATA_WIDTH-1: 0] : 1.1134 + read_byte_9 ? 8'h00 : 1.1135 + read_byte_A ? 8'h00 : 1.1136 + read_byte_B ? 8'h00 : 1.1137 + read_byte_C ? IRQ_TRI_TEMP[DATA_WIDTH-1: 0] : 1.1138 + read_byte_D ? 8'h00 : 1.1139 + read_byte_E ? 8'h00 : 1.1140 + read_byte_F ? 8'h00 : 1.1141 + 0; 1.1142 + end 1.1143 + else 1.1144 + assign GPIO_DAT_O_switch = 0; 1.1145 + 1.1146 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.1147 + 1.1148 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.1149 + 1.1150 + if (INPUT_PORTS_ONLY == 1) 1.1151 + assign GPIO_DAT_O_switch = read_addr_0 ? PIO_DATA : 1.1152 + read_addr_8 ? IRQ_MASK : 1.1153 + read_addr_C ? EDGE_CAPTURE : 1.1154 + 0; 1.1155 + else if (BOTH_INPUT_AND_OUTPUT == 1) 1.1156 + assign GPIO_DAT_O_switch = read_addr_0 ? PIO_DATAI : 1.1157 + read_addr_8 ? IRQ_MASK_BOTH : 1.1158 + read_addr_C ? EDGE_CAPTURE_BOTH : 1.1159 + 0; 1.1160 + else if (TRISTATE_PORTS == 1) 1.1161 + assign GPIO_DAT_O_switch = read_addr_0 ? tpio_out : 1.1162 + read_addr_4 ? tpio_out : 1.1163 + read_addr_8 ? tpio_out : 1.1164 + read_addr_C ? IRQ_TRI_TEMP : 1.1165 + 0; 1.1166 + else 1.1167 + assign GPIO_DAT_O_switch = 0; 1.1168 + 1.1169 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.1170 + 1.1171 endgenerate 1.1172 1.1173 -//----------------------------------------------------------------------------- 1.1174 -//-------------------------------IRQ Generation-------------------------------- 1.1175 -//----------------------------------------------------------------------------- 1.1176 + 1.1177 + 1.1178 + //----------------------------------------------------------------------------- 1.1179 + //-------------------------------IRQ Generation-------------------------------- 1.1180 + //----------------------------------------------------------------------------- 1.1181 generate 1.1182 + 1.1183 if (IRQ_MODE == 1) begin 1.1184 - always @(posedge CLK_I or posedge RST_I) 1.1185 - if (RST_I) begin 1.1186 - IRQ_MASK <= #UDLY 0; 1.1187 - IRQ_MASK_BOTH <= #UDLY 0; 1.1188 - end else if (IRQ_MASK_WR_EN) begin 1.1189 - IRQ_MASK <= #UDLY GPIO_DAT_I[DATA_WIDTH-1:0]; 1.1190 - IRQ_MASK_BOTH <= #UDLY GPIO_DAT_I[INPUT_WIDTH-1:0]; 1.1191 - end 1.1192 - end 1.1193 + 1.1194 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.1195 + 1.1196 + genvar im_idx; 1.1197 + for (im_idx = 0; (im_idx < DATA_WIDTH) && (im_idx < 8); im_idx = im_idx + 1) 1.1198 + begin 1.1199 + always @(posedge CLK_I or posedge RST_I) 1.1200 + if (RST_I) 1.1201 + IRQ_MASK[im_idx] <= #UDLY 0; 1.1202 + else if (IRQ_MASK_WR_EN_0) 1.1203 + IRQ_MASK[im_idx] <= #UDLY GPIO_DAT_I_switch[im_idx]; 1.1204 + end 1.1205 + if (DATA_WIDTH > 8) begin 1.1206 + genvar jm_idx; 1.1207 + for (jm_idx = 8; (jm_idx < DATA_WIDTH) && (jm_idx < 16); jm_idx = jm_idx + 1) 1.1208 + begin 1.1209 + always @(posedge CLK_I or posedge RST_I) 1.1210 + if (RST_I) 1.1211 + IRQ_MASK[jm_idx] <= #UDLY 0; 1.1212 + else if (IRQ_MASK_WR_EN_1) 1.1213 + IRQ_MASK[jm_idx] <= #UDLY GPIO_DAT_I_switch[jm_idx-8]; 1.1214 + end 1.1215 + end 1.1216 + if (DATA_WIDTH > 16) begin 1.1217 + genvar km_idx; 1.1218 + for (km_idx = 16; (km_idx < DATA_WIDTH) && (km_idx < 24); km_idx = km_idx + 1) 1.1219 + begin 1.1220 + always @(posedge CLK_I or posedge RST_I) 1.1221 + if (RST_I) 1.1222 + IRQ_MASK[km_idx] <= #UDLY 0; 1.1223 + else if (IRQ_MASK_WR_EN_2) 1.1224 + IRQ_MASK[km_idx] <= #UDLY GPIO_DAT_I_switch[km_idx-16]; 1.1225 + end 1.1226 + end 1.1227 + if (DATA_WIDTH > 24) begin 1.1228 + genvar lm_idx; 1.1229 + for (lm_idx = 24; (lm_idx < DATA_WIDTH) && (lm_idx < 32); lm_idx = lm_idx + 1) 1.1230 + begin 1.1231 + always @(posedge CLK_I or posedge RST_I) 1.1232 + if (RST_I) 1.1233 + IRQ_MASK[lm_idx] <= #UDLY 0; 1.1234 + else if (IRQ_MASK_WR_EN_3) 1.1235 + IRQ_MASK[lm_idx] <= #UDLY GPIO_DAT_I_switch[lm_idx-24]; 1.1236 + end 1.1237 + end 1.1238 + 1.1239 + genvar imb_idx; 1.1240 + for (imb_idx = 0; (imb_idx < INPUT_WIDTH) && (imb_idx < 8); imb_idx = imb_idx + 1) 1.1241 + begin 1.1242 + always @(posedge CLK_I or posedge RST_I) 1.1243 + if (RST_I) 1.1244 + IRQ_MASK_BOTH[imb_idx] <= #UDLY 0; 1.1245 + else if (IRQ_MASK_WR_EN_0) 1.1246 + IRQ_MASK_BOTH[imb_idx] <= #UDLY GPIO_DAT_I_switch[imb_idx]; 1.1247 + end 1.1248 + if (INPUT_WIDTH > 8) begin 1.1249 + genvar jmb_idx; 1.1250 + for (jmb_idx = 8; (jmb_idx < INPUT_WIDTH) && (jmb_idx < 16); jmb_idx = jmb_idx + 1) 1.1251 + begin 1.1252 + always @(posedge CLK_I or posedge RST_I) 1.1253 + if (RST_I) 1.1254 + IRQ_MASK_BOTH[jmb_idx] <= #UDLY 0; 1.1255 + else if (IRQ_MASK_WR_EN_1) 1.1256 + IRQ_MASK_BOTH[jmb_idx] <= #UDLY GPIO_DAT_I_switch[jmb_idx-8]; 1.1257 + end 1.1258 + end 1.1259 + if (INPUT_WIDTH > 16) begin 1.1260 + genvar kmb_idx; 1.1261 + for (kmb_idx = 16; (kmb_idx < INPUT_WIDTH) && (kmb_idx < 24); kmb_idx = kmb_idx + 1) 1.1262 + begin 1.1263 + always @(posedge CLK_I or posedge RST_I) 1.1264 + if (RST_I) 1.1265 + IRQ_MASK_BOTH[kmb_idx] <= #UDLY 0; 1.1266 + else if (IRQ_MASK_WR_EN_2) 1.1267 + IRQ_MASK_BOTH[kmb_idx] <= #UDLY GPIO_DAT_I_switch[kmb_idx-16]; 1.1268 + end 1.1269 + end 1.1270 + if (INPUT_WIDTH > 24) begin 1.1271 + genvar lmb_idx; 1.1272 + for (lmb_idx = 24; (lmb_idx < INPUT_WIDTH) && (lmb_idx < 32); lmb_idx = lmb_idx + 1) 1.1273 + begin 1.1274 + always @(posedge CLK_I or posedge RST_I) 1.1275 + if (RST_I) 1.1276 + IRQ_MASK_BOTH[lmb_idx] <= #UDLY 0; 1.1277 + else if (IRQ_MASK_WR_EN_3) 1.1278 + IRQ_MASK_BOTH[lmb_idx] <= #UDLY GPIO_DAT_I_switch[lmb_idx-24]; 1.1279 + end 1.1280 + end 1.1281 + 1.1282 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.1283 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.1284 + 1.1285 + genvar im_idx; 1.1286 + for (im_idx = 0; (im_idx < DATA_WIDTH) && (im_idx < 8); im_idx = im_idx + 1) 1.1287 + begin 1.1288 + always @(posedge CLK_I or posedge RST_I) 1.1289 + if (RST_I) 1.1290 + IRQ_MASK[im_idx] <= #UDLY 0; 1.1291 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0]) 1.1292 + IRQ_MASK[im_idx] <= #UDLY GPIO_DAT_I_switch[im_idx]; 1.1293 + end 1.1294 + if (DATA_WIDTH > 8) begin 1.1295 + genvar jm_idx; 1.1296 + for (jm_idx = 8; (jm_idx < DATA_WIDTH) && (jm_idx < 16); jm_idx = jm_idx + 1) 1.1297 + begin 1.1298 + always @(posedge CLK_I or posedge RST_I) 1.1299 + if (RST_I) 1.1300 + IRQ_MASK[jm_idx] <= #UDLY 0; 1.1301 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1]) 1.1302 + IRQ_MASK[jm_idx] <= #UDLY GPIO_DAT_I_switch[jm_idx]; 1.1303 + end 1.1304 + end 1.1305 + if (DATA_WIDTH > 16) begin 1.1306 + genvar km_idx; 1.1307 + for (km_idx = 16; (km_idx < DATA_WIDTH) && (km_idx < 24); km_idx = km_idx + 1) 1.1308 + begin 1.1309 + always @(posedge CLK_I or posedge RST_I) 1.1310 + if (RST_I) 1.1311 + IRQ_MASK[km_idx] <= #UDLY 0; 1.1312 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2]) 1.1313 + IRQ_MASK[km_idx] <= #UDLY GPIO_DAT_I_switch[km_idx]; 1.1314 + end 1.1315 + end 1.1316 + if (DATA_WIDTH > 24) begin 1.1317 + genvar lm_idx; 1.1318 + for (lm_idx = 24; (lm_idx < DATA_WIDTH) && (lm_idx < 32); lm_idx = lm_idx + 1) 1.1319 + begin 1.1320 + always @(posedge CLK_I or posedge RST_I) 1.1321 + if (RST_I) 1.1322 + IRQ_MASK[lm_idx] <= #UDLY 0; 1.1323 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3]) 1.1324 + IRQ_MASK[lm_idx] <= #UDLY GPIO_DAT_I_switch[lm_idx]; 1.1325 + end 1.1326 + end 1.1327 + 1.1328 + genvar imb_idx; 1.1329 + for (imb_idx = 0; (imb_idx < INPUT_WIDTH) && (imb_idx < 8); imb_idx = imb_idx + 1) 1.1330 + begin 1.1331 + always @(posedge CLK_I or posedge RST_I) 1.1332 + if (RST_I) 1.1333 + IRQ_MASK_BOTH[imb_idx] <= #UDLY 0; 1.1334 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0]) 1.1335 + IRQ_MASK_BOTH[imb_idx] <= #UDLY GPIO_DAT_I_switch[imb_idx]; 1.1336 + end 1.1337 + if (INPUT_WIDTH > 8) begin 1.1338 + genvar jmb_idx; 1.1339 + for (jmb_idx = 8; (jmb_idx < INPUT_WIDTH) && (jmb_idx < 16); jmb_idx = jmb_idx + 1) 1.1340 + begin 1.1341 + always @(posedge CLK_I or posedge RST_I) 1.1342 + if (RST_I) 1.1343 + IRQ_MASK_BOTH[jmb_idx] <= #UDLY 0; 1.1344 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1]) 1.1345 + IRQ_MASK_BOTH[jmb_idx] <= #UDLY GPIO_DAT_I_switch[jmb_idx]; 1.1346 + end 1.1347 + end 1.1348 + if (INPUT_WIDTH > 16) begin 1.1349 + genvar kmb_idx; 1.1350 + for (kmb_idx = 16; (kmb_idx < INPUT_WIDTH) && (kmb_idx < 24); kmb_idx = kmb_idx + 1) 1.1351 + begin 1.1352 + always @(posedge CLK_I or posedge RST_I) 1.1353 + if (RST_I) 1.1354 + IRQ_MASK_BOTH[kmb_idx] <= #UDLY 0; 1.1355 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2]) 1.1356 + IRQ_MASK_BOTH[kmb_idx] <= #UDLY GPIO_DAT_I_switch[kmb_idx]; 1.1357 + end 1.1358 + end 1.1359 + if (INPUT_WIDTH > 24) begin 1.1360 + genvar lmb_idx; 1.1361 + for (lmb_idx = 24; (lmb_idx < INPUT_WIDTH) && (lmb_idx < 32); lmb_idx = lmb_idx + 1) 1.1362 + begin 1.1363 + always @(posedge CLK_I or posedge RST_I) 1.1364 + if (RST_I) 1.1365 + IRQ_MASK_BOTH[lmb_idx] <= #UDLY 0; 1.1366 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3]) 1.1367 + IRQ_MASK_BOTH[lmb_idx] <= #UDLY GPIO_DAT_I_switch[lmb_idx]; 1.1368 + end 1.1369 + end 1.1370 + 1.1371 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.1372 + 1.1373 + end // if (IRQ_MODE == 1) 1.1374 + 1.1375 endgenerate 1.1376 - 1.1377 + 1.1378 + 1.1379 + 1.1380 generate 1.1381 //-------------------------------- 1.1382 //--INPUT_PORTS_ONLY MODE IRQ 1.1383 //-------------------------------- 1.1384 - if (IRQ_MODE == 1 && INPUT_PORTS_ONLY == 1 && LEVEL == 1) begin 1.1385 - //level mode IRQ 1.1386 - always @(posedge CLK_I or posedge RST_I) 1.1387 - if (RST_I) 1.1388 - IRQ_TEMP <= #UDLY 0; 1.1389 - else if (IRQ_MASK_WR_EN) 1.1390 - IRQ_TEMP <= #UDLY IRQ_TEMP & GPIO_DAT_I[DATA_WIDTH-1:0]; 1.1391 - else 1.1392 - IRQ_TEMP <= #UDLY PIO_IN & IRQ_MASK;//bit-and 1.1393 + if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (LEVEL == 1)) begin 1.1394 + // level mode IRQ 1.1395 + 1.1396 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.1397 + 1.1398 + genvar i; 1.1399 + for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1) 1.1400 + begin 1.1401 + always @(posedge CLK_I or posedge RST_I) 1.1402 + if (RST_I) 1.1403 + IRQ_TEMP[i] <= #UDLY 0; 1.1404 + else if (IRQ_MASK_WR_EN_0) 1.1405 + IRQ_TEMP[i] <= #UDLY IRQ_TEMP[i] & GPIO_DAT_I_switch[i]; 1.1406 + else 1.1407 + IRQ_TEMP[i] <= #UDLY PIO_IN[i] & IRQ_MASK[i]; 1.1408 + end 1.1409 + if (DATA_WIDTH > 8) begin 1.1410 + genvar j; 1.1411 + for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1) 1.1412 + begin 1.1413 + always @(posedge CLK_I or posedge RST_I) 1.1414 + if (RST_I) 1.1415 + IRQ_TEMP[j] <= #UDLY 0; 1.1416 + else if (IRQ_MASK_WR_EN_1) 1.1417 + IRQ_TEMP[j] <= #UDLY IRQ_TEMP[j] & GPIO_DAT_I_switch[j-8]; 1.1418 + else 1.1419 + IRQ_TEMP[j] <= #UDLY PIO_IN[j] & IRQ_MASK[j]; 1.1420 + end 1.1421 + end 1.1422 + if (DATA_WIDTH > 16) begin 1.1423 + genvar k; 1.1424 + for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1) 1.1425 + begin 1.1426 + always @(posedge CLK_I or posedge RST_I) 1.1427 + if (RST_I) 1.1428 + IRQ_TEMP[k] <= #UDLY 0; 1.1429 + else if (IRQ_MASK_WR_EN_2) 1.1430 + IRQ_TEMP[k] <= #UDLY IRQ_TEMP[k] & GPIO_DAT_I_switch[k-16]; 1.1431 + else 1.1432 + IRQ_TEMP[k] <= #UDLY PIO_IN[k] & IRQ_MASK[k]; 1.1433 + end 1.1434 + end 1.1435 + if (DATA_WIDTH > 24) begin 1.1436 + genvar l; 1.1437 + for (l = 24; (l < DATA_WIDTH) && (l < 32); l = l + 1) 1.1438 + begin 1.1439 + always @(posedge CLK_I or posedge RST_I) 1.1440 + if (RST_I) 1.1441 + IRQ_TEMP[l] <= #UDLY 0; 1.1442 + else if (IRQ_MASK_WR_EN_3) 1.1443 + IRQ_TEMP[l] <= #UDLY IRQ_TEMP[l] & GPIO_DAT_I_switch[l-24]; 1.1444 + else 1.1445 + IRQ_TEMP[l] <= #UDLY PIO_IN[l] & IRQ_MASK[l]; 1.1446 + end 1.1447 + end 1.1448 + 1.1449 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.1450 + 1.1451 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.1452 + 1.1453 + genvar i; 1.1454 + for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1) 1.1455 + begin 1.1456 + always @(posedge CLK_I or posedge RST_I) 1.1457 + if (RST_I) 1.1458 + IRQ_TEMP[i] <= #UDLY 0; 1.1459 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0]) 1.1460 + IRQ_TEMP[i] <= #UDLY IRQ_TEMP[i] & GPIO_DAT_I_switch[i]; 1.1461 + else 1.1462 + IRQ_TEMP[i] <= #UDLY PIO_IN[i] & IRQ_MASK[i]; 1.1463 + end 1.1464 + if (DATA_WIDTH > 8) begin 1.1465 + genvar j; 1.1466 + for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1) 1.1467 + begin 1.1468 + always @(posedge CLK_I or posedge RST_I) 1.1469 + if (RST_I) 1.1470 + IRQ_TEMP[j] <= #UDLY 0; 1.1471 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1]) 1.1472 + IRQ_TEMP[j] <= #UDLY IRQ_TEMP[j] & GPIO_DAT_I_switch[j]; 1.1473 + else 1.1474 + IRQ_TEMP[j] <= #UDLY PIO_IN[j] & IRQ_MASK[j]; 1.1475 + end 1.1476 + end 1.1477 + if (DATA_WIDTH > 16) begin 1.1478 + genvar k; 1.1479 + for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1) 1.1480 + begin 1.1481 + always @(posedge CLK_I or posedge RST_I) 1.1482 + if (RST_I) 1.1483 + IRQ_TEMP[k] <= #UDLY 0; 1.1484 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2]) 1.1485 + IRQ_TEMP[k] <= #UDLY IRQ_TEMP[k] & GPIO_DAT_I_switch[k]; 1.1486 + else 1.1487 + IRQ_TEMP[k] <= #UDLY PIO_IN[k] & IRQ_MASK[k]; 1.1488 + end 1.1489 + end 1.1490 + if (DATA_WIDTH > 24) begin 1.1491 + genvar l; 1.1492 + for (l = 24; (l < DATA_WIDTH) && (l < 32); l = l + 1) 1.1493 + begin 1.1494 + always @(posedge CLK_I or posedge RST_I) 1.1495 + if (RST_I) 1.1496 + IRQ_TEMP[l] <= #UDLY 0; 1.1497 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3]) 1.1498 + IRQ_TEMP[l] <= #UDLY IRQ_TEMP[l] & GPIO_DAT_I_switch[l]; 1.1499 + else 1.1500 + IRQ_TEMP[l] <= #UDLY PIO_IN[l] & IRQ_MASK[l]; 1.1501 + end 1.1502 + end 1.1503 + 1.1504 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.1505 + 1.1506 assign IRQ_O = |IRQ_TEMP; 1.1507 - end else if (IRQ_MODE == 1 && INPUT_PORTS_ONLY == 1 && EDGE == 1) begin 1.1508 + 1.1509 + end // if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (LEVEL == 1)) 1.1510 + 1.1511 + else if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (EDGE == 1)) begin 1.1512 + // edge mode IRQ 1.1513 + 1.1514 always @(posedge CLK_I or posedge RST_I) 1.1515 if (RST_I) 1.1516 PIO_DATA_DLY <= #UDLY 0; 1.1517 else 1.1518 PIO_DATA_DLY <= PIO_IN; 1.1519 - 1.1520 + 1.1521 // edge-capture register bits are treated as individual bits. 1.1522 - genvar i; 1.1523 - for( i = 0; i < DATA_WIDTH; i = i + 1) 1.1524 - begin 1.1525 - always @(posedge CLK_I or posedge RST_I) 1.1526 - if (RST_I) 1.1527 - EDGE_CAPTURE[i] <= #UDLY 0; 1.1528 - else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (POSE_EDGE_IRQ == 1)) 1.1529 - EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i]; 1.1530 - else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (NEGE_EDGE_IRQ == 1)) 1.1531 - EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i]; 1.1532 - else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1)) 1.1533 - EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i]; 1.1534 - else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1)) 1.1535 - EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i]; 1.1536 - else if ( (~IRQ_MASK[i]) & GPIO_DAT_I[i] & IRQ_MASK_WR_EN ) 1.1537 - // interrupt mask is being set, so clear edge-capture 1.1538 - EDGE_CAPTURE[i] <= #UDLY 0; 1.1539 - else if (EDGE_CAP_WR_EN) 1.1540 - // user's writing to the edge register, so update edge capture 1.1541 - // register 1.1542 - EDGE_CAPTURE[i] <= #UDLY EDGE_CAPTURE[i] & GPIO_DAT_I[i]; 1.1543 - end 1.1544 - assign IRQ_O = |(EDGE_CAPTURE & IRQ_MASK); 1.1545 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.1546 + 1.1547 + genvar i; 1.1548 + for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1) 1.1549 + begin 1.1550 + always @(posedge CLK_I or posedge RST_I) 1.1551 + if (RST_I) 1.1552 + EDGE_CAPTURE[i] <= #UDLY 0; 1.1553 + else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (POSE_EDGE_IRQ == 1)) 1.1554 + EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i]; 1.1555 + else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (NEGE_EDGE_IRQ == 1)) 1.1556 + EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i]; 1.1557 + else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1)) 1.1558 + EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i]; 1.1559 + else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1)) 1.1560 + EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i]; 1.1561 + else if ( (~IRQ_MASK[i]) & GPIO_DAT_I_switch[i] & IRQ_MASK_WR_EN_0) 1.1562 + // interrupt mask is being set, so clear edge-capture 1.1563 + EDGE_CAPTURE[i] <= #UDLY 0; 1.1564 + else if (EDGE_CAP_WR_EN_0) 1.1565 + // user's writing to the edge register, so update edge capture 1.1566 + // register 1.1567 + EDGE_CAPTURE[i] <= #UDLY EDGE_CAPTURE[i] & GPIO_DAT_I_switch[i]; 1.1568 + end 1.1569 + 1.1570 + if (DATA_WIDTH > 8) begin 1.1571 + genvar j; 1.1572 + for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1) 1.1573 + begin 1.1574 + always @(posedge CLK_I or posedge RST_I) 1.1575 + if (RST_I) 1.1576 + EDGE_CAPTURE[j] <= #UDLY 0; 1.1577 + else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (POSE_EDGE_IRQ == 1)) 1.1578 + EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j]; 1.1579 + else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (NEGE_EDGE_IRQ == 1)) 1.1580 + EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j]; 1.1581 + else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1)) 1.1582 + EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j]; 1.1583 + else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1)) 1.1584 + EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j]; 1.1585 + else if ( (~IRQ_MASK[j]) & GPIO_DAT_I_switch[j-8] & IRQ_MASK_WR_EN_1) 1.1586 + // interrupt mask is being set, so clear edge-capture 1.1587 + EDGE_CAPTURE[j] <= #UDLY 0; 1.1588 + else if (EDGE_CAP_WR_EN_1) 1.1589 + // user's writing to the edge register, so update edge capture 1.1590 + // register 1.1591 + EDGE_CAPTURE[j] <= #UDLY EDGE_CAPTURE[j] & GPIO_DAT_I_switch[j-8]; 1.1592 + end 1.1593 + end 1.1594 + 1.1595 + if (DATA_WIDTH > 16) begin 1.1596 + genvar k; 1.1597 + for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1) 1.1598 + begin 1.1599 + always @(posedge CLK_I or posedge RST_I) 1.1600 + if (RST_I) 1.1601 + EDGE_CAPTURE[k] <= #UDLY 0; 1.1602 + else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (POSE_EDGE_IRQ == 1)) 1.1603 + EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k]; 1.1604 + else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (NEGE_EDGE_IRQ == 1)) 1.1605 + EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k]; 1.1606 + else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1)) 1.1607 + EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k]; 1.1608 + else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1)) 1.1609 + EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k]; 1.1610 + else if ( (~IRQ_MASK[k]) & GPIO_DAT_I_switch[k-16] & IRQ_MASK_WR_EN_2) 1.1611 + // interrupt mask is being set, so clear edge-capture 1.1612 + EDGE_CAPTURE[k] <= #UDLY 0; 1.1613 + else if (EDGE_CAP_WR_EN_2) 1.1614 + // user's writing to the edge register, so update edge capture 1.1615 + // register 1.1616 + EDGE_CAPTURE[k] <= #UDLY EDGE_CAPTURE[k] & GPIO_DAT_I_switch[k-16]; 1.1617 + end 1.1618 + end 1.1619 + 1.1620 + if (DATA_WIDTH > 24) begin 1.1621 + genvar l; 1.1622 + for (l = 24; l < DATA_WIDTH; l = l + 1) 1.1623 + begin 1.1624 + always @(posedge CLK_I or posedge RST_I) 1.1625 + if (RST_I) 1.1626 + EDGE_CAPTURE[l] <= #UDLY 0; 1.1627 + else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (POSE_EDGE_IRQ == 1)) 1.1628 + EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l]; 1.1629 + else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (NEGE_EDGE_IRQ == 1)) 1.1630 + EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l]; 1.1631 + else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1)) 1.1632 + EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l]; 1.1633 + else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1)) 1.1634 + EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l]; 1.1635 + else if ( (~IRQ_MASK[l]) & GPIO_DAT_I_switch[l-24] & IRQ_MASK_WR_EN_3) 1.1636 + // interrupt mask is being set, so clear edge-capture 1.1637 + EDGE_CAPTURE[l] <= #UDLY 0; 1.1638 + else if (EDGE_CAP_WR_EN_3) 1.1639 + // user's writing to the edge register, so update edge capture 1.1640 + // register 1.1641 + EDGE_CAPTURE[l] <= #UDLY EDGE_CAPTURE[l] & GPIO_DAT_I_switch[l-24]; 1.1642 + end 1.1643 + end 1.1644 + 1.1645 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.1646 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.1647 + 1.1648 + genvar i; 1.1649 + for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1) 1.1650 + begin 1.1651 + always @(posedge CLK_I or posedge RST_I) 1.1652 + if (RST_I) 1.1653 + EDGE_CAPTURE[i] <= #UDLY 0; 1.1654 + else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (POSE_EDGE_IRQ == 1)) 1.1655 + EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i]; 1.1656 + else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (NEGE_EDGE_IRQ == 1)) 1.1657 + EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i]; 1.1658 + else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1)) 1.1659 + EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i]; 1.1660 + else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1)) 1.1661 + EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i]; 1.1662 + else if ( (~IRQ_MASK[i]) & GPIO_DAT_I_switch[i] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0]) 1.1663 + // interrupt mask is being set, so clear edge-capture 1.1664 + EDGE_CAPTURE[i] <= #UDLY 0; 1.1665 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[0]) 1.1666 + // user's writing to the edge register, so update edge capture 1.1667 + // register 1.1668 + EDGE_CAPTURE[i] <= #UDLY EDGE_CAPTURE[i] & GPIO_DAT_I_switch[i]; 1.1669 + end 1.1670 + 1.1671 + if (DATA_WIDTH > 8) begin 1.1672 + genvar j; 1.1673 + for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1) 1.1674 + begin 1.1675 + always @(posedge CLK_I or posedge RST_I) 1.1676 + if (RST_I) 1.1677 + EDGE_CAPTURE[j] <= #UDLY 0; 1.1678 + else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (POSE_EDGE_IRQ == 1)) 1.1679 + EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j]; 1.1680 + else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (NEGE_EDGE_IRQ == 1)) 1.1681 + EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j]; 1.1682 + else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1)) 1.1683 + EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j]; 1.1684 + else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1)) 1.1685 + EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j]; 1.1686 + else if ( (~IRQ_MASK[j]) & GPIO_DAT_I_switch[j-8] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0]) 1.1687 + // interrupt mask is being set, so clear edge-capture 1.1688 + EDGE_CAPTURE[j] <= #UDLY 0; 1.1689 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[0]) 1.1690 + // user's writing to the edge register, so update edge capture 1.1691 + // register 1.1692 + EDGE_CAPTURE[j] <= #UDLY EDGE_CAPTURE[j] & GPIO_DAT_I_switch[j]; 1.1693 + end 1.1694 + end 1.1695 + 1.1696 + if (DATA_WIDTH > 16) begin 1.1697 + genvar k; 1.1698 + for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1) 1.1699 + begin 1.1700 + always @(posedge CLK_I or posedge RST_I) 1.1701 + if (RST_I) 1.1702 + EDGE_CAPTURE[k] <= #UDLY 0; 1.1703 + else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (POSE_EDGE_IRQ == 1)) 1.1704 + EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k]; 1.1705 + else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (NEGE_EDGE_IRQ == 1)) 1.1706 + EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k]; 1.1707 + else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1)) 1.1708 + EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k]; 1.1709 + else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1)) 1.1710 + EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k]; 1.1711 + else if ( (~IRQ_MASK[k]) & GPIO_DAT_I_switch[k-16] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2]) 1.1712 + // interrupt mask is being set, so clear edge-capture 1.1713 + EDGE_CAPTURE[k] <= #UDLY 0; 1.1714 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[2]) 1.1715 + // user's writing to the edge register, so update edge capture 1.1716 + // register 1.1717 + EDGE_CAPTURE[k] <= #UDLY EDGE_CAPTURE[k] & GPIO_DAT_I_switch[k]; 1.1718 + end 1.1719 + end 1.1720 + 1.1721 + if (DATA_WIDTH > 24) begin 1.1722 + genvar l; 1.1723 + for (l = 24; l < DATA_WIDTH; l = l + 1) 1.1724 + begin 1.1725 + always @(posedge CLK_I or posedge RST_I) 1.1726 + if (RST_I) 1.1727 + EDGE_CAPTURE[l] <= #UDLY 0; 1.1728 + else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (POSE_EDGE_IRQ == 1)) 1.1729 + EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l]; 1.1730 + else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (NEGE_EDGE_IRQ == 1)) 1.1731 + EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l]; 1.1732 + else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1)) 1.1733 + EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l]; 1.1734 + else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1)) 1.1735 + EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l]; 1.1736 + else if ( (~IRQ_MASK[l]) & GPIO_DAT_I_switch[l-24] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3]) 1.1737 + // interrupt mask is being set, so clear edge-capture 1.1738 + EDGE_CAPTURE[l] <= #UDLY 0; 1.1739 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[3]) 1.1740 + // user's writing to the edge register, so update edge capture 1.1741 + // register 1.1742 + EDGE_CAPTURE[l] <= #UDLY EDGE_CAPTURE[l] & GPIO_DAT_I_switch[l]; 1.1743 + end 1.1744 + end 1.1745 + 1.1746 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.1747 + 1.1748 + assign IRQ_O = |(EDGE_CAPTURE[DATA_WIDTH-1:0] & IRQ_MASK[DATA_WIDTH-1:0]); 1.1749 + 1.1750 + end // if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (EDGE == 1)) 1.1751 + 1.1752 + //---------------------------------- 1.1753 + //--BOTH_INPUT_AND_OUTPUT MODE IRQ 1.1754 + //---------------------------------- 1.1755 + else if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (LEVEL == 1)) begin 1.1756 1.1757 - //---------------------------------- 1.1758 - //--BOTH_INPUT_AND_OUTPUT MODE IRQ 1.1759 - //---------------------------------- 1.1760 - end else if (IRQ_MODE == 1 && BOTH_INPUT_AND_OUTPUT == 1 && LEVEL == 1) begin 1.1761 - always @(posedge CLK_I or posedge RST_I) 1.1762 - if (RST_I) 1.1763 - IRQ_TEMP_BOTH <= #UDLY 0; 1.1764 - else if (IRQ_MASK_WR_EN) 1.1765 - IRQ_TEMP_BOTH <= #UDLY IRQ_TEMP_BOTH & GPIO_DAT_I[INPUT_WIDTH-1:0]; 1.1766 - else 1.1767 - IRQ_TEMP_BOTH <= #UDLY PIO_BOTH_IN & IRQ_MASK_BOTH; 1.1768 - assign IRQ_O = |IRQ_TEMP_BOTH; 1.1769 - 1.1770 - //edge mode IRQ 1.1771 - end else if (IRQ_MODE == 1 && BOTH_INPUT_AND_OUTPUT == 1 && EDGE == 1) begin 1.1772 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.1773 + 1.1774 + genvar iitb_idx; 1.1775 + for (iitb_idx = 0; (iitb_idx < INPUT_WIDTH) && (iitb_idx < 8); iitb_idx = iitb_idx + 1) 1.1776 + begin 1.1777 + always @(posedge CLK_I or posedge RST_I) 1.1778 + if (RST_I) 1.1779 + IRQ_TEMP_BOTH[iitb_idx] <= #UDLY 0; 1.1780 + else if (IRQ_MASK_WR_EN_0) 1.1781 + IRQ_TEMP_BOTH[iitb_idx] <= #UDLY IRQ_TEMP_BOTH[iitb_idx] & GPIO_DAT_I_switch[iitb_idx]; 1.1782 + else 1.1783 + IRQ_TEMP_BOTH[iitb_idx] <= #UDLY PIO_BOTH_IN[iitb_idx] & IRQ_MASK_BOTH[iitb_idx]; 1.1784 + end 1.1785 + if (INPUT_WIDTH > 8) begin 1.1786 + genvar jitb_idx; 1.1787 + for (jitb_idx = 8; (jitb_idx < INPUT_WIDTH) && (jitb_idx < 16); jitb_idx = jitb_idx + 1) 1.1788 + begin 1.1789 + always @(posedge CLK_I or posedge RST_I) 1.1790 + if (RST_I) 1.1791 + IRQ_TEMP_BOTH[jitb_idx] <= #UDLY 0; 1.1792 + else if (IRQ_MASK_WR_EN_1) 1.1793 + IRQ_TEMP_BOTH[jitb_idx] <= #UDLY IRQ_TEMP_BOTH[jitb_idx] & GPIO_DAT_I_switch[jitb_idx - 8]; 1.1794 + else 1.1795 + IRQ_TEMP_BOTH[jitb_idx] <= #UDLY PIO_BOTH_IN[jitb_idx] & IRQ_MASK_BOTH[jitb_idx]; 1.1796 + end 1.1797 + end 1.1798 + if (INPUT_WIDTH > 16) begin 1.1799 + genvar kitb_idx; 1.1800 + for (kitb_idx = 16; (kitb_idx < INPUT_WIDTH) && (kitb_idx < 24); kitb_idx = kitb_idx + 1) 1.1801 + begin 1.1802 + always @(posedge CLK_I or posedge RST_I) 1.1803 + if (RST_I) 1.1804 + IRQ_TEMP_BOTH[kitb_idx] <= #UDLY 0; 1.1805 + else if (IRQ_MASK_WR_EN_2) 1.1806 + IRQ_TEMP_BOTH[kitb_idx] <= #UDLY IRQ_TEMP_BOTH[kitb_idx] & GPIO_DAT_I_switch[kitb_idx - 16]; 1.1807 + else 1.1808 + IRQ_TEMP_BOTH[kitb_idx] <= #UDLY PIO_BOTH_IN[kitb_idx] & IRQ_MASK_BOTH[kitb_idx]; 1.1809 + end 1.1810 + end 1.1811 + if (INPUT_WIDTH > 24) begin 1.1812 + genvar litb_idx; 1.1813 + for (litb_idx = 24; (litb_idx < INPUT_WIDTH) && (litb_idx < 24); litb_idx = litb_idx + 1) 1.1814 + begin 1.1815 + always @(posedge CLK_I or posedge RST_I) 1.1816 + if (RST_I) 1.1817 + IRQ_TEMP_BOTH[litb_idx] <= #UDLY 0; 1.1818 + else if (IRQ_MASK_WR_EN_3) 1.1819 + IRQ_TEMP_BOTH[litb_idx] <= #UDLY IRQ_TEMP_BOTH[litb_idx] & GPIO_DAT_I_switch[litb_idx - 24]; 1.1820 + else 1.1821 + IRQ_TEMP_BOTH[litb_idx] <= #UDLY PIO_BOTH_IN[litb_idx] & IRQ_MASK_BOTH[litb_idx]; 1.1822 + end 1.1823 + end 1.1824 + 1.1825 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.1826 + 1.1827 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.1828 + 1.1829 + genvar iitb_idx; 1.1830 + for (iitb_idx = 0; (iitb_idx < INPUT_WIDTH) && (iitb_idx < 8); iitb_idx = iitb_idx + 1) 1.1831 + begin 1.1832 + always @(posedge CLK_I or posedge RST_I) 1.1833 + if (RST_I) 1.1834 + IRQ_TEMP_BOTH[iitb_idx] <= #UDLY 0; 1.1835 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0]) 1.1836 + IRQ_TEMP_BOTH[iitb_idx] <= #UDLY IRQ_TEMP_BOTH[iitb_idx] & GPIO_DAT_I_switch[iitb_idx]; 1.1837 + else 1.1838 + IRQ_TEMP_BOTH[iitb_idx] <= #UDLY PIO_BOTH_IN[iitb_idx] & IRQ_MASK_BOTH[iitb_idx]; 1.1839 + end 1.1840 + if (INPUT_WIDTH > 8) begin 1.1841 + genvar jitb_idx; 1.1842 + for (jitb_idx = 8; (jitb_idx < INPUT_WIDTH) && (jitb_idx < 16); jitb_idx = jitb_idx + 1) 1.1843 + begin 1.1844 + always @(posedge CLK_I or posedge RST_I) 1.1845 + if (RST_I) 1.1846 + IRQ_TEMP_BOTH[jitb_idx] <= #UDLY 0; 1.1847 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1]) 1.1848 + IRQ_TEMP_BOTH[jitb_idx] <= #UDLY IRQ_TEMP_BOTH[jitb_idx] & GPIO_DAT_I_switch[jitb_idx]; 1.1849 + else 1.1850 + IRQ_TEMP_BOTH[jitb_idx] <= #UDLY PIO_BOTH_IN[jitb_idx] & IRQ_MASK_BOTH[jitb_idx]; 1.1851 + end 1.1852 + end 1.1853 + if (INPUT_WIDTH > 16) begin 1.1854 + genvar kitb_idx; 1.1855 + for (kitb_idx = 16; (kitb_idx < INPUT_WIDTH) && (kitb_idx < 24); kitb_idx = kitb_idx + 1) 1.1856 + begin 1.1857 + always @(posedge CLK_I or posedge RST_I) 1.1858 + if (RST_I) 1.1859 + IRQ_TEMP_BOTH[kitb_idx] <= #UDLY 0; 1.1860 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2]) 1.1861 + IRQ_TEMP_BOTH[kitb_idx] <= #UDLY IRQ_TEMP_BOTH[kitb_idx] & GPIO_DAT_I_switch[kitb_idx]; 1.1862 + else 1.1863 + IRQ_TEMP_BOTH[kitb_idx] <= #UDLY PIO_BOTH_IN[kitb_idx] & IRQ_MASK_BOTH[kitb_idx]; 1.1864 + end 1.1865 + end 1.1866 + if (INPUT_WIDTH > 24) begin 1.1867 + genvar litb_idx; 1.1868 + for (litb_idx = 24; (litb_idx < INPUT_WIDTH) && (litb_idx < 24); litb_idx = litb_idx + 1) 1.1869 + begin 1.1870 + always @(posedge CLK_I or posedge RST_I) 1.1871 + if (RST_I) 1.1872 + IRQ_TEMP_BOTH[litb_idx] <= #UDLY 0; 1.1873 + else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3]) 1.1874 + IRQ_TEMP_BOTH[litb_idx] <= #UDLY IRQ_TEMP_BOTH[litb_idx] & GPIO_DAT_I_switch[litb_idx]; 1.1875 + else 1.1876 + IRQ_TEMP_BOTH[litb_idx] <= #UDLY PIO_BOTH_IN[litb_idx] & IRQ_MASK_BOTH[litb_idx]; 1.1877 + end 1.1878 + end 1.1879 + 1.1880 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.1881 + 1.1882 + assign IRQ_O = |IRQ_TEMP_BOTH; 1.1883 + 1.1884 + end // if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (LEVEL == 1)) 1.1885 + 1.1886 + // edge mode IRQ 1.1887 + else if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (EDGE == 1)) begin 1.1888 + 1.1889 always @(posedge CLK_I or posedge RST_I) 1.1890 if (RST_I) 1.1891 PIO_DATA_DLY_BOTH <= #UDLY 0; 1.1892 else 1.1893 PIO_DATA_DLY_BOTH <= PIO_BOTH_IN; 1.1894 - 1.1895 + 1.1896 // edge-capture register bits are treated as individual bits. 1.1897 - genvar i_both; 1.1898 - for( i_both = 0; i_both < INPUT_WIDTH; i_both = i_both + 1) 1.1899 - begin 1.1900 - always @(posedge CLK_I or posedge RST_I) 1.1901 - if (RST_I) 1.1902 - EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0; 1.1903 - else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && POSE_EDGE_IRQ == 1) 1.1904 - EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]; 1.1905 - else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && NEGE_EDGE_IRQ == 1) 1.1906 - EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]; 1.1907 - else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1) 1.1908 - EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]; 1.1909 - else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1) 1.1910 - EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]; 1.1911 - else if ( (~IRQ_MASK_BOTH[i_both]) & GPIO_DAT_I[i_both] & IRQ_MASK_WR_EN ) 1.1912 - // interrupt mask is being set, so clear edge-capture 1.1913 - EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0; 1.1914 - else if (EDGE_CAP_WR_EN) 1.1915 - // user's writing to the edge register, so update edge capture 1.1916 - // register 1.1917 - EDGE_CAPTURE_BOTH[i_both] <= #UDLY EDGE_CAPTURE_BOTH[i_both] & GPIO_DAT_I[i_both]; 1.1918 - end 1.1919 + if (GPIO_WB_DAT_WIDTH == 8) begin 1.1920 + 1.1921 + genvar i_both; 1.1922 + for (i_both = 0; (i_both < INPUT_WIDTH) && (i_both < 8); i_both = i_both + 1) 1.1923 + begin 1.1924 + always @(posedge CLK_I or posedge RST_I) 1.1925 + if (RST_I) 1.1926 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0; 1.1927 + else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && POSE_EDGE_IRQ == 1) 1.1928 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]; 1.1929 + else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && NEGE_EDGE_IRQ == 1) 1.1930 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]; 1.1931 + else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1) 1.1932 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]; 1.1933 + else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1) 1.1934 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]; 1.1935 + else if ( (~IRQ_MASK_BOTH[i_both]) & GPIO_DAT_I_switch[i_both] & IRQ_MASK_WR_EN_0 ) 1.1936 + // interrupt mask is being set, so clear edge-capture 1.1937 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0; 1.1938 + else if (EDGE_CAP_WR_EN_0) 1.1939 + // user's writing to the edge register, so update edge capture 1.1940 + // register 1.1941 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY EDGE_CAPTURE_BOTH[i_both] & GPIO_DAT_I_switch[i_both]; 1.1942 + end 1.1943 + if (INPUT_WIDTH > 8) begin 1.1944 + genvar j_both; 1.1945 + for (j_both = 8; (j_both < INPUT_WIDTH) && (j_both < 16); j_both = j_both + 1) 1.1946 + begin 1.1947 + always @(posedge CLK_I or posedge RST_I) 1.1948 + if (RST_I) 1.1949 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0; 1.1950 + else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && POSE_EDGE_IRQ == 1) 1.1951 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]; 1.1952 + else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) && NEGE_EDGE_IRQ == 1) 1.1953 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]; 1.1954 + else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1) 1.1955 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]; 1.1956 + else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1) 1.1957 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]; 1.1958 + else if ( (~IRQ_MASK_BOTH[j_both]) & GPIO_DAT_I_switch[j_both-8] & IRQ_MASK_WR_EN_1 ) 1.1959 + // interrupt mask is being set, so clear edge-capture 1.1960 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0; 1.1961 + else if (EDGE_CAP_WR_EN_1) 1.1962 + // user's writing to the edge register, so update edge capture 1.1963 + // register 1.1964 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY EDGE_CAPTURE_BOTH[j_both] & GPIO_DAT_I_switch[j_both-8]; 1.1965 + end 1.1966 + end 1.1967 + if (INPUT_WIDTH > 16) begin 1.1968 + genvar k_both; 1.1969 + for (k_both = 16; (k_both < INPUT_WIDTH) && (k_both < 24); k_both = k_both + 1) 1.1970 + begin 1.1971 + always @(posedge CLK_I or posedge RST_I) 1.1972 + if (RST_I) 1.1973 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0; 1.1974 + else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && POSE_EDGE_IRQ == 1) 1.1975 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]; 1.1976 + else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) && NEGE_EDGE_IRQ == 1) 1.1977 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]; 1.1978 + else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1) 1.1979 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]; 1.1980 + else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1) 1.1981 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]; 1.1982 + else if ( (~IRQ_MASK_BOTH[k_both]) & GPIO_DAT_I_switch[k_both-16] & IRQ_MASK_WR_EN_2 ) 1.1983 + // interrupt mask is being set, so clear edge-capture 1.1984 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0; 1.1985 + else if (EDGE_CAP_WR_EN_2) 1.1986 + // user's writing to the edge register, so update edge capture 1.1987 + // register 1.1988 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY EDGE_CAPTURE_BOTH[k_both] & GPIO_DAT_I_switch[k_both-16]; 1.1989 + end 1.1990 + end 1.1991 + if (INPUT_WIDTH > 24) begin 1.1992 + genvar l_both; 1.1993 + for (l_both = 24; (l_both < INPUT_WIDTH) && (l_both < 32); l_both = l_both + 1) 1.1994 + begin 1.1995 + always @(posedge CLK_I or posedge RST_I) 1.1996 + if (RST_I) 1.1997 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0; 1.1998 + else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && POSE_EDGE_IRQ == 1) 1.1999 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]; 1.2000 + else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) && NEGE_EDGE_IRQ == 1) 1.2001 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]; 1.2002 + else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1) 1.2003 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]; 1.2004 + else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1) 1.2005 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]; 1.2006 + else if ( (~IRQ_MASK_BOTH[l_both]) & GPIO_DAT_I_switch[l_both-24] & IRQ_MASK_WR_EN_3 ) 1.2007 + // interrupt mask is being set, so clear edge-capture 1.2008 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0; 1.2009 + else if (EDGE_CAP_WR_EN_3) 1.2010 + // user's writing to the edge register, so update edge capture 1.2011 + // register 1.2012 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY EDGE_CAPTURE_BOTH[l_both] & GPIO_DAT_I_switch[l_both-24]; 1.2013 + end 1.2014 + end 1.2015 + 1.2016 + end // if (GPIO_WB_DAT_WIDTH == 8) 1.2017 + else if (GPIO_WB_DAT_WIDTH == 32) begin 1.2018 + 1.2019 + genvar i_both; 1.2020 + for (i_both = 0; (i_both < INPUT_WIDTH) && (i_both < 8); i_both = i_both + 1) 1.2021 + begin 1.2022 + always @(posedge CLK_I or posedge RST_I) 1.2023 + if (RST_I) 1.2024 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0; 1.2025 + else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && POSE_EDGE_IRQ == 1) 1.2026 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]; 1.2027 + else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && NEGE_EDGE_IRQ == 1) 1.2028 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]; 1.2029 + else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1) 1.2030 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]; 1.2031 + else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1) 1.2032 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]; 1.2033 + else if ( (~IRQ_MASK_BOTH[i_both]) & GPIO_DAT_I_switch[i_both] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0]) 1.2034 + // interrupt mask is being set, so clear edge-capture 1.2035 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0; 1.2036 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[0]) 1.2037 + // user's writing to the edge register, so update edge capture 1.2038 + // register 1.2039 + EDGE_CAPTURE_BOTH[i_both] <= #UDLY EDGE_CAPTURE_BOTH[i_both] & GPIO_DAT_I_switch[i_both]; 1.2040 + end 1.2041 + if (INPUT_WIDTH > 8) begin 1.2042 + genvar j_both; 1.2043 + for (j_both = 8; (j_both < INPUT_WIDTH) && (j_both < 16); j_both = j_both + 1) 1.2044 + begin 1.2045 + always @(posedge CLK_I or posedge RST_I) 1.2046 + if (RST_I) 1.2047 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0; 1.2048 + else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && POSE_EDGE_IRQ == 1) 1.2049 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]; 1.2050 + else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) && NEGE_EDGE_IRQ == 1) 1.2051 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]; 1.2052 + else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1) 1.2053 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]; 1.2054 + else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1) 1.2055 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]; 1.2056 + else if ( (~IRQ_MASK_BOTH[j_both]) & GPIO_DAT_I_switch[j_both-8] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1]) 1.2057 + // interrupt mask is being set, so clear edge-capture 1.2058 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0; 1.2059 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[1]) 1.2060 + // user's writing to the edge register, so update edge capture 1.2061 + // register 1.2062 + EDGE_CAPTURE_BOTH[j_both] <= #UDLY EDGE_CAPTURE_BOTH[j_both] & GPIO_DAT_I_switch[j_both]; 1.2063 + end 1.2064 + end 1.2065 + if (INPUT_WIDTH > 16) begin 1.2066 + genvar k_both; 1.2067 + for (k_both = 16; (k_both < INPUT_WIDTH) && (k_both < 24); k_both = k_both + 1) 1.2068 + begin 1.2069 + always @(posedge CLK_I or posedge RST_I) 1.2070 + if (RST_I) 1.2071 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0; 1.2072 + else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && POSE_EDGE_IRQ == 1) 1.2073 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]; 1.2074 + else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) && NEGE_EDGE_IRQ == 1) 1.2075 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]; 1.2076 + else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1) 1.2077 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]; 1.2078 + else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1) 1.2079 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]; 1.2080 + else if ( (~IRQ_MASK_BOTH[k_both]) & GPIO_DAT_I_switch[k_both-16] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2]) 1.2081 + // interrupt mask is being set, so clear edge-capture 1.2082 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0; 1.2083 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[2]) 1.2084 + // user's writing to the edge register, so update edge capture 1.2085 + // register 1.2086 + EDGE_CAPTURE_BOTH[k_both] <= #UDLY EDGE_CAPTURE_BOTH[k_both] & GPIO_DAT_I_switch[k_both]; 1.2087 + end 1.2088 + end 1.2089 + if (INPUT_WIDTH > 24) begin 1.2090 + genvar l_both; 1.2091 + for (l_both = 24; (l_both < INPUT_WIDTH) && (l_both < 32); l_both = l_both + 1) 1.2092 + begin 1.2093 + always @(posedge CLK_I or posedge RST_I) 1.2094 + if (RST_I) 1.2095 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0; 1.2096 + else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && POSE_EDGE_IRQ == 1) 1.2097 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]; 1.2098 + else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) && NEGE_EDGE_IRQ == 1) 1.2099 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]; 1.2100 + else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1) 1.2101 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]; 1.2102 + else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1) 1.2103 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]; 1.2104 + else if ( (~IRQ_MASK_BOTH[l_both]) & GPIO_DAT_I_switch[l_both-24] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3]) 1.2105 + // interrupt mask is being set, so clear edge-capture 1.2106 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0; 1.2107 + else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[3]) 1.2108 + // user's writing to the edge register, so update edge capture 1.2109 + // register 1.2110 + EDGE_CAPTURE_BOTH[l_both] <= #UDLY EDGE_CAPTURE_BOTH[l_both] & GPIO_DAT_I_switch[l_both]; 1.2111 + end 1.2112 + end 1.2113 + 1.2114 + end // if (GPIO_WB_DAT_WIDTH == 32) 1.2115 + 1.2116 assign IRQ_O = |(EDGE_CAPTURE_BOTH & IRQ_MASK_BOTH); 1.2117 1.2118 - end else if (IRQ_MODE == 1 && TRISTATE_PORTS == 1) begin 1.2119 + end // if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (EDGE == 1)) 1.2120 + 1.2121 + else if (IRQ_MODE == 1 && TRISTATE_PORTS == 1) begin 1.2122 + 1.2123 assign IRQ_O = |IRQ_TRI_TEMP; 1.2124 - end else 1.2125 + end 1.2126 + 1.2127 + else begin 1.2128 + 1.2129 assign IRQ_O = 1'b0; 1.2130 - endgenerate 1.2131 + end 1.2132 + 1.2133 + endgenerate 1.2134 + 1.2135 1.2136 endmodule 1.2137 `endif // GPIO_V