Sat, 06 Aug 2011 00:02:46 +0100
[UPSTREAM PULL] Update baseline to LatticeMico32 v3.8 from Diamond 1.3-lm32 distribution package (datestamp May 2011)
1.1 diff -r 35dc7ba83714 -r 73de224304c1 JTAGB.v 1.2 --- a/JTAGB.v Sun Mar 06 21:14:43 2011 +0000 1.3 +++ b/JTAGB.v Sat Aug 06 00:02:46 2011 +0100 1.4 @@ -1,18 +1,39 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 +// ================================================================== 1.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.16 +// ------------------------------------------------------------------ 1.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.18 +// ALL RIGHTS RESERVED 1.19 +// ------------------------------------------------------------------ 1.20 +// 1.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.22 +// 1.23 +// Permission: 1.24 +// 1.25 +// Lattice Semiconductor grants permission to use this code 1.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.27 +// Open Source License Agreement. 1.28 +// 1.29 +// Disclaimer: 1.30 // 1.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.34 -// U.S.A email: techsupport@latticesemi.com 1.35 -// =============================================================================/ 1.36 +// Lattice Semiconductor provides no warranty regarding the use or 1.37 +// functionality of this code. It is the user's responsibility to 1.38 +// verify the user’s design for consistency and functionality through 1.39 +// the use of formal verification methods. 1.40 +// 1.41 +// -------------------------------------------------------------------- 1.42 +// 1.43 +// Lattice Semiconductor Corporation 1.44 +// 5555 NE Moore Court 1.45 +// Hillsboro, OR 97214 1.46 +// U.S.A 1.47 +// 1.48 +// TEL: 1-800-Lattice (USA and Canada) 1.49 +// 503-286-8001 (other locations) 1.50 +// 1.51 +// web: http://www.latticesemi.com/ 1.52 +// email: techsupport@latticesemi.com 1.53 +// 1.54 +// -------------------------------------------------------------------- 1.55 // FILE DETAILS 1.56 // Project : LatticeMico32 1.57 // File : JTAGB.v
2.1 diff -r 35dc7ba83714 -r 73de224304c1 er1.v 2.2 --- a/er1.v Sun Mar 06 21:14:43 2011 +0000 2.3 +++ b/er1.v Sat Aug 06 00:02:46 2011 +0100 2.4 @@ -1,18 +1,39 @@ 2.5 -// ============================================================================= 2.6 -// COPYRIGHT NOTICE 2.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 2.8 -// ALL RIGHTS RESERVED 2.9 -// This confidential and proprietary software may be used only as authorised by 2.10 -// a licensing agreement from Lattice Semiconductor Corporation. 2.11 -// The entire notice above must be reproduced on all authorized copies and 2.12 -// copies may only be made to the extent permitted by a licensing agreement from 2.13 -// Lattice Semiconductor Corporation. 2.14 +// ================================================================== 2.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 2.16 +// ------------------------------------------------------------------ 2.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 2.18 +// ALL RIGHTS RESERVED 2.19 +// ------------------------------------------------------------------ 2.20 +// 2.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 2.22 +// 2.23 +// Permission: 2.24 +// 2.25 +// Lattice Semiconductor grants permission to use this code 2.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 2.27 +// Open Source License Agreement. 2.28 +// 2.29 +// Disclaimer: 2.30 // 2.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 2.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 2.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 2.34 -// U.S.A email: techsupport@latticesemi.com 2.35 -// =============================================================================/ 2.36 +// Lattice Semiconductor provides no warranty regarding the use or 2.37 +// functionality of this code. It is the user's responsibility to 2.38 +// verify the user’s design for consistency and functionality through 2.39 +// the use of formal verification methods. 2.40 +// 2.41 +// -------------------------------------------------------------------- 2.42 +// 2.43 +// Lattice Semiconductor Corporation 2.44 +// 5555 NE Moore Court 2.45 +// Hillsboro, OR 97214 2.46 +// U.S.A 2.47 +// 2.48 +// TEL: 1-800-Lattice (USA and Canada) 2.49 +// 503-286-8001 (other locations) 2.50 +// 2.51 +// web: http://www.latticesemi.com/ 2.52 +// email: techsupport@latticesemi.com 2.53 +// 2.54 +// -------------------------------------------------------------------- 2.55 // FILE DETAILS 2.56 // Project : LatticeMico32 2.57 // File : er1.v
3.1 diff -r 35dc7ba83714 -r 73de224304c1 jtag_cores.v 3.2 --- a/jtag_cores.v Sun Mar 06 21:14:43 2011 +0000 3.3 +++ b/jtag_cores.v Sat Aug 06 00:02:46 2011 +0100 3.4 @@ -1,18 +1,39 @@ 3.5 -// ============================================================================ 3.6 -// COPYRIGHT NOTICE 3.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 3.8 -// ALL RIGHTS RESERVED 3.9 -// This confidential and proprietary software may be used only as authorised by 3.10 -// a licensing agreement from Lattice Semiconductor Corporation. 3.11 -// The entire notice above must be reproduced on all authorized copies and 3.12 -// copies may only be made to the extent permitted by a licensing agreement from 3.13 -// Lattice Semiconductor Corporation. 3.14 +// ================================================================== 3.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3.16 +// ------------------------------------------------------------------ 3.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 3.18 +// ALL RIGHTS RESERVED 3.19 +// ------------------------------------------------------------------ 3.20 +// 3.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 3.22 +// 3.23 +// Permission: 3.24 +// 3.25 +// Lattice Semiconductor grants permission to use this code 3.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 3.27 +// Open Source License Agreement. 3.28 +// 3.29 +// Disclaimer: 3.30 // 3.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 3.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 3.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 3.34 -// U.S.A email: techsupport@latticesemi.com 3.35 -// ============================================================================/ 3.36 +// Lattice Semiconductor provides no warranty regarding the use or 3.37 +// functionality of this code. It is the user's responsibility to 3.38 +// verify the user’s design for consistency and functionality through 3.39 +// the use of formal verification methods. 3.40 +// 3.41 +// -------------------------------------------------------------------- 3.42 +// 3.43 +// Lattice Semiconductor Corporation 3.44 +// 5555 NE Moore Court 3.45 +// Hillsboro, OR 97214 3.46 +// U.S.A 3.47 +// 3.48 +// TEL: 1-800-Lattice (USA and Canada) 3.49 +// 503-286-8001 (other locations) 3.50 +// 3.51 +// web: http://www.latticesemi.com/ 3.52 +// email: techsupport@latticesemi.com 3.53 +// 3.54 +// -------------------------------------------------------------------- 3.55 // FILE DETAILS 3.56 // Project : LatticeMico32 3.57 // File : jtag_cores.v
4.1 diff -r 35dc7ba83714 -r 73de224304c1 jtag_lm32.v 4.2 --- a/jtag_lm32.v Sun Mar 06 21:14:43 2011 +0000 4.3 +++ b/jtag_lm32.v Sat Aug 06 00:02:46 2011 +0100 4.4 @@ -1,18 +1,39 @@ 4.5 -// ============================================================================= 4.6 -// COPYRIGHT NOTICE 4.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 4.8 -// ALL RIGHTS RESERVED 4.9 -// This confidential and proprietary software may be used only as authorised by 4.10 -// a licensing agreement from Lattice Semiconductor Corporation. 4.11 -// The entire notice above must be reproduced on all authorized copies and 4.12 -// copies may only be made to the extent permitted by a licensing agreement from 4.13 -// Lattice Semiconductor Corporation. 4.14 +// ================================================================== 4.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 4.16 +// ------------------------------------------------------------------ 4.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 4.18 +// ALL RIGHTS RESERVED 4.19 +// ------------------------------------------------------------------ 4.20 +// 4.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 4.22 +// 4.23 +// Permission: 4.24 +// 4.25 +// Lattice Semiconductor grants permission to use this code 4.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 4.27 +// Open Source License Agreement. 4.28 +// 4.29 +// Disclaimer: 4.30 // 4.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 4.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 4.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 4.34 -// U.S.A email: techsupport@latticesemi.com 4.35 -// =============================================================================/ 4.36 +// Lattice Semiconductor provides no warranty regarding the use or 4.37 +// functionality of this code. It is the user's responsibility to 4.38 +// verify the user’s design for consistency and functionality through 4.39 +// the use of formal verification methods. 4.40 +// 4.41 +// -------------------------------------------------------------------- 4.42 +// 4.43 +// Lattice Semiconductor Corporation 4.44 +// 5555 NE Moore Court 4.45 +// Hillsboro, OR 97214 4.46 +// U.S.A 4.47 +// 4.48 +// TEL: 1-800-Lattice (USA and Canada) 4.49 +// 503-286-8001 (other locations) 4.50 +// 4.51 +// web: http://www.latticesemi.com/ 4.52 +// email: techsupport@latticesemi.com 4.53 +// 4.54 +// -------------------------------------------------------------------- 4.55 // FILE DETAILS 4.56 // Project : LatticeMico32 4.57 // File : jtag_lm32.v
5.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_adder.v 5.2 --- a/lm32_adder.v Sun Mar 06 21:14:43 2011 +0000 5.3 +++ b/lm32_adder.v Sat Aug 06 00:02:46 2011 +0100 5.4 @@ -1,18 +1,39 @@ 5.5 -// ============================================================================= 5.6 -// COPYRIGHT NOTICE 5.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 5.8 -// ALL RIGHTS RESERVED 5.9 -// This confidential and proprietary software may be used only as authorised by 5.10 -// a licensing agreement from Lattice Semiconductor Corporation. 5.11 -// The entire notice above must be reproduced on all authorized copies and 5.12 -// copies may only be made to the extent permitted by a licensing agreement from 5.13 -// Lattice Semiconductor Corporation. 5.14 +// ================================================================== 5.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 5.16 +// ------------------------------------------------------------------ 5.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 5.18 +// ALL RIGHTS RESERVED 5.19 +// ------------------------------------------------------------------ 5.20 +// 5.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 5.22 +// 5.23 +// Permission: 5.24 +// 5.25 +// Lattice Semiconductor grants permission to use this code 5.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 5.27 +// Open Source License Agreement. 5.28 +// 5.29 +// Disclaimer: 5.30 // 5.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 5.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 5.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 5.34 -// U.S.A email: techsupport@latticesemi.com 5.35 -// ============================================================================/ 5.36 +// Lattice Semiconductor provides no warranty regarding the use or 5.37 +// functionality of this code. It is the user's responsibility to 5.38 +// verify the user’s design for consistency and functionality through 5.39 +// the use of formal verification methods. 5.40 +// 5.41 +// -------------------------------------------------------------------- 5.42 +// 5.43 +// Lattice Semiconductor Corporation 5.44 +// 5555 NE Moore Court 5.45 +// Hillsboro, OR 97214 5.46 +// U.S.A 5.47 +// 5.48 +// TEL: 1-800-Lattice (USA and Canada) 5.49 +// 503-286-8001 (other locations) 5.50 +// 5.51 +// web: http://www.latticesemi.com/ 5.52 +// email: techsupport@latticesemi.com 5.53 +// 5.54 +// -------------------------------------------------------------------- 5.55 // FILE DETAILS 5.56 // Project : LatticeMico32 5.57 // File : lm32_adder.v
6.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_addsub.v 6.2 --- a/lm32_addsub.v Sun Mar 06 21:14:43 2011 +0000 6.3 +++ b/lm32_addsub.v Sat Aug 06 00:02:46 2011 +0100 6.4 @@ -1,18 +1,39 @@ 6.5 -// ============================================================================= 6.6 -// COPYRIGHT NOTICE 6.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 6.8 -// ALL RIGHTS RESERVED 6.9 -// This confidential and proprietary software may be used only as authorised by 6.10 -// a licensing agreement from Lattice Semiconductor Corporation. 6.11 -// The entire notice above must be reproduced on all authorized copies and 6.12 -// copies may only be made to the extent permitted by a licensing agreement from 6.13 -// Lattice Semiconductor Corporation. 6.14 +// ================================================================== 6.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 6.16 +// ------------------------------------------------------------------ 6.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 6.18 +// ALL RIGHTS RESERVED 6.19 +// ------------------------------------------------------------------ 6.20 +// 6.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 6.22 +// 6.23 +// Permission: 6.24 +// 6.25 +// Lattice Semiconductor grants permission to use this code 6.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 6.27 +// Open Source License Agreement. 6.28 +// 6.29 +// Disclaimer: 6.30 // 6.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 6.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 6.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 6.34 -// U.S.A email: techsupport@latticesemi.com 6.35 -// =============================================================================/ 6.36 +// Lattice Semiconductor provides no warranty regarding the use or 6.37 +// functionality of this code. It is the user's responsibility to 6.38 +// verify the user’s design for consistency and functionality through 6.39 +// the use of formal verification methods. 6.40 +// 6.41 +// -------------------------------------------------------------------- 6.42 +// 6.43 +// Lattice Semiconductor Corporation 6.44 +// 5555 NE Moore Court 6.45 +// Hillsboro, OR 97214 6.46 +// U.S.A 6.47 +// 6.48 +// TEL: 1-800-Lattice (USA and Canada) 6.49 +// 503-286-8001 (other locations) 6.50 +// 6.51 +// web: http://www.latticesemi.com/ 6.52 +// email: techsupport@latticesemi.com 6.53 +// 6.54 +// -------------------------------------------------------------------- 6.55 // FILE DETAILS 6.56 // Project : LatticeMico32 6.57 // File : lm32_addsub.v
7.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_cpu.v 7.2 --- a/lm32_cpu.v Sun Mar 06 21:14:43 2011 +0000 7.3 +++ b/lm32_cpu.v Sat Aug 06 00:02:46 2011 +0100 7.4 @@ -1,24 +1,50 @@ 7.5 -// ============================================================================= 7.6 -// COPYRIGHT NOTICE 7.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 7.8 -// ALL RIGHTS RESERVED 7.9 -// This confidential and proprietary software may be used only as authorised by 7.10 -// a licensing agreement from Lattice Semiconductor Corporation. 7.11 -// The entire notice above must be reproduced on all authorized copies and 7.12 -// copies may only be made to the extent permitted by a licensing agreement from 7.13 -// Lattice Semiconductor Corporation. 7.14 +// ================================================================== 7.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 7.16 +// ------------------------------------------------------------------ 7.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 7.18 +// ALL RIGHTS RESERVED 7.19 +// ------------------------------------------------------------------ 7.20 +// 7.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 7.22 +// 7.23 +// Permission: 7.24 +// 7.25 +// Lattice Semiconductor grants permission to use this code 7.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 7.27 +// Open Source License Agreement. 7.28 +// 7.29 +// Disclaimer: 7.30 // 7.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 7.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 7.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 7.34 -// U.S.A email: techsupport@latticesemi.com 7.35 -// =============================================================================/ 7.36 +// Lattice Semiconductor provides no warranty regarding the use or 7.37 +// functionality of this code. It is the user's responsibility to 7.38 +// verify the user’s design for consistency and functionality through 7.39 +// the use of formal verification methods. 7.40 +// 7.41 +// -------------------------------------------------------------------- 7.42 +// 7.43 +// Lattice Semiconductor Corporation 7.44 +// 5555 NE Moore Court 7.45 +// Hillsboro, OR 97214 7.46 +// U.S.A 7.47 +// 7.48 +// TEL: 1-800-Lattice (USA and Canada) 7.49 +// 503-286-8001 (other locations) 7.50 +// 7.51 +// web: http://www.latticesemi.com/ 7.52 +// email: techsupport@latticesemi.com 7.53 +// 7.54 +// -------------------------------------------------------------------- 7.55 // FILE DETAILS 7.56 // Project : LatticeMico32 7.57 // File : lm32_cpu.v 7.58 // Title : Top-level of CPU. 7.59 // Dependencies : lm32_include.v 7.60 // 7.61 +// Version 3.8 7.62 +// 1. Feature: Support for dynamically switching EBA to DEBA via a GPIO. 7.63 +// 2. Bug: EA now reports instruction that caused the data abort, rather than 7.64 +// next instruction. 7.65 +// 7.66 // Version 3.4 7.67 // 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 7.68 // never serviced. 7.69 @@ -75,6 +101,11 @@ 7.70 clk_n_i, 7.71 `endif 7.72 rst_i, 7.73 +`ifdef CFG_DEBUG_ENABLED 7.74 + `ifdef CFG_ALTERNATE_EBA 7.75 + at_debug, 7.76 + `endif 7.77 +`endif 7.78 // From external devices 7.79 `ifdef CFG_INTERRUPTS_ENABLED 7.80 interrupt_n, 7.81 @@ -212,6 +243,12 @@ 7.82 `endif 7.83 input rst_i; // Reset 7.84 7.85 +`ifdef CFG_DEBUG_ENABLED 7.86 + `ifdef CFG_ALTERNATE_EBA 7.87 + input at_debug; // GPIO input that maps EBA to DEBA 7.88 + `endif 7.89 +`endif 7.90 + 7.91 `ifdef CFG_INTERRUPTS_ENABLED 7.92 input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low 7.93 `endif 7.94 @@ -751,6 +788,11 @@ 7.95 // ----- Inputs ------- 7.96 .clk_i (clk_i), 7.97 .rst_i (rst_i), 7.98 +`ifdef CFG_DEBUG_ENABLED 7.99 + `ifdef CFG_ALTERNATE_EBA 7.100 + .at_debug (at_debug), 7.101 + `endif 7.102 +`endif 7.103 // From pipeline 7.104 .stall_a (stall_a), 7.105 .stall_f (stall_f), 7.106 @@ -1256,15 +1298,15 @@ 7.107 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.108 if (rst_i == `TRUE) 7.109 begin 7.110 - regfile_raw_0 <= 1'b0; 7.111 - regfile_raw_1 <= 1'b0; 7.112 - w_result_d <= 32'b0; 7.113 + regfile_raw_0 <= #1 1'b0; 7.114 + regfile_raw_1 <= #1 1'b0; 7.115 + w_result_d <= #1 32'b0; 7.116 end 7.117 else 7.118 begin 7.119 - regfile_raw_0 <= regfile_raw_0_nxt; 7.120 - regfile_raw_1 <= regfile_raw_1_nxt; 7.121 - w_result_d <= w_result; 7.122 + regfile_raw_0 <= #1 regfile_raw_0_nxt; 7.123 + regfile_raw_1 <= #1 regfile_raw_1_nxt; 7.124 + w_result_d <= #1 w_result; 7.125 end 7.126 7.127 /*---------------------------------------------------------------------- 7.128 @@ -2090,14 +2132,14 @@ 7.129 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.130 begin 7.131 if (rst_i == `TRUE) 7.132 - eba <= eba_reset[`LM32_PC_WIDTH+2-1:8]; 7.133 + eba <= #1 eba_reset[`LM32_PC_WIDTH+2-1:8]; 7.134 else 7.135 begin 7.136 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE)) 7.137 - eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 7.138 + eba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8]; 7.139 `ifdef CFG_HW_DEBUG_ENABLED 7.140 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA)) 7.141 - eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 7.142 + eba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 7.143 `endif 7.144 end 7.145 end 7.146 @@ -2107,14 +2149,14 @@ 7.147 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.148 begin 7.149 if (rst_i == `TRUE) 7.150 - deba <= deba_reset[`LM32_PC_WIDTH+2-1:8]; 7.151 + deba <= #1 deba_reset[`LM32_PC_WIDTH+2-1:8]; 7.152 else 7.153 begin 7.154 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE)) 7.155 - deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 7.156 + deba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8]; 7.157 `ifdef CFG_HW_DEBUG_ENABLED 7.158 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA)) 7.159 - deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 7.160 + deba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 7.161 `endif 7.162 end 7.163 end 7.164 @@ -2125,9 +2167,9 @@ 7.165 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.166 begin 7.167 if (rst_i == `TRUE) 7.168 - cc <= {`LM32_WORD_WIDTH{1'b0}}; 7.169 + cc <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.170 else 7.171 - cc <= cc + 1'b1; 7.172 + cc <= #1 cc + 1'b1; 7.173 end 7.174 `endif 7.175 7.176 @@ -2136,15 +2178,15 @@ 7.177 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.178 begin 7.179 if (rst_i == `TRUE) 7.180 - data_bus_error_seen <= `FALSE; 7.181 + data_bus_error_seen <= #1 `FALSE; 7.182 else 7.183 begin 7.184 // Set flag when bus error is detected 7.185 if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE)) 7.186 - data_bus_error_seen <= `TRUE; 7.187 + data_bus_error_seen <= #1 `TRUE; 7.188 // Clear flag when exception is taken 7.189 if ((exception_m == `TRUE) && (kill_m == `FALSE)) 7.190 - data_bus_error_seen <= `FALSE; 7.191 + data_bus_error_seen <= #1 `FALSE; 7.192 end 7.193 end 7.194 `endif 7.195 @@ -2195,48 +2237,48 @@ 7.196 begin 7.197 if (rst_i == `TRUE) 7.198 begin 7.199 - valid_f <= `FALSE; 7.200 - valid_d <= `FALSE; 7.201 - valid_x <= `FALSE; 7.202 - valid_m <= `FALSE; 7.203 - valid_w <= `FALSE; 7.204 + valid_f <= #1 `FALSE; 7.205 + valid_d <= #1 `FALSE; 7.206 + valid_x <= #1 `FALSE; 7.207 + valid_m <= #1 `FALSE; 7.208 + valid_w <= #1 `FALSE; 7.209 end 7.210 else 7.211 begin 7.212 if ((kill_f == `TRUE) || (stall_a == `FALSE)) 7.213 `ifdef LM32_CACHE_ENABLED 7.214 - valid_f <= valid_a; 7.215 + valid_f <= #1 valid_a; 7.216 `else 7.217 - valid_f <= `TRUE; 7.218 + valid_f <= #1 `TRUE; 7.219 `endif 7.220 else if (stall_f == `FALSE) 7.221 - valid_f <= `FALSE; 7.222 + valid_f <= #1 `FALSE; 7.223 7.224 if (kill_d == `TRUE) 7.225 - valid_d <= `FALSE; 7.226 + valid_d <= #1 `FALSE; 7.227 else if (stall_f == `FALSE) 7.228 - valid_d <= valid_f & !kill_f; 7.229 + valid_d <= #1 valid_f & !kill_f; 7.230 else if (stall_d == `FALSE) 7.231 - valid_d <= `FALSE; 7.232 + valid_d <= #1 `FALSE; 7.233 7.234 if (stall_d == `FALSE) 7.235 - valid_x <= valid_d & !kill_d; 7.236 + valid_x <= #1 valid_d & !kill_d; 7.237 else if (kill_x == `TRUE) 7.238 - valid_x <= `FALSE; 7.239 + valid_x <= #1 `FALSE; 7.240 else if (stall_x == `FALSE) 7.241 - valid_x <= `FALSE; 7.242 + valid_x <= #1 `FALSE; 7.243 7.244 if (kill_m == `TRUE) 7.245 - valid_m <= `FALSE; 7.246 + valid_m <= #1 `FALSE; 7.247 else if (stall_x == `FALSE) 7.248 - valid_m <= valid_x & !kill_x; 7.249 + valid_m <= #1 valid_x & !kill_x; 7.250 else if (stall_m == `FALSE) 7.251 - valid_m <= `FALSE; 7.252 + valid_m <= #1 `FALSE; 7.253 7.254 if (stall_m == `FALSE) 7.255 - valid_w <= valid_m & !kill_m; 7.256 + valid_w <= #1 valid_m & !kill_m; 7.257 else 7.258 - valid_w <= `FALSE; 7.259 + valid_w <= #1 `FALSE; 7.260 end 7.261 end 7.262 7.263 @@ -2246,113 +2288,113 @@ 7.264 if (rst_i == `TRUE) 7.265 begin 7.266 `ifdef CFG_USER_ENABLED 7.267 - user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}}; 7.268 + user_opcode <= #1 {`LM32_USER_OPCODE_WIDTH{1'b0}}; 7.269 `endif 7.270 - operand_0_x <= {`LM32_WORD_WIDTH{1'b0}}; 7.271 - operand_1_x <= {`LM32_WORD_WIDTH{1'b0}}; 7.272 - store_operand_x <= {`LM32_WORD_WIDTH{1'b0}}; 7.273 - branch_target_x <= {`LM32_WORD_WIDTH{1'b0}}; 7.274 - x_result_sel_csr_x <= `FALSE; 7.275 + operand_0_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.276 + operand_1_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.277 + store_operand_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.278 + branch_target_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.279 + x_result_sel_csr_x <= #1 `FALSE; 7.280 `ifdef LM32_MC_ARITHMETIC_ENABLED 7.281 - x_result_sel_mc_arith_x <= `FALSE; 7.282 + x_result_sel_mc_arith_x <= #1 `FALSE; 7.283 `endif 7.284 `ifdef LM32_NO_BARREL_SHIFT 7.285 - x_result_sel_shift_x <= `FALSE; 7.286 + x_result_sel_shift_x <= #1 `FALSE; 7.287 `endif 7.288 `ifdef CFG_SIGN_EXTEND_ENABLED 7.289 - x_result_sel_sext_x <= `FALSE; 7.290 + x_result_sel_sext_x <= #1 `FALSE; 7.291 `endif 7.292 - x_result_sel_logic_x <= `FALSE; 7.293 + x_result_sel_logic_x <= #1 `FALSE; 7.294 `ifdef CFG_USER_ENABLED 7.295 - x_result_sel_user_x <= `FALSE; 7.296 + x_result_sel_user_x <= #1 `FALSE; 7.297 `endif 7.298 - x_result_sel_add_x <= `FALSE; 7.299 - m_result_sel_compare_x <= `FALSE; 7.300 + x_result_sel_add_x <= #1 `FALSE; 7.301 + m_result_sel_compare_x <= #1 `FALSE; 7.302 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.303 - m_result_sel_shift_x <= `FALSE; 7.304 + m_result_sel_shift_x <= #1 `FALSE; 7.305 `endif 7.306 - w_result_sel_load_x <= `FALSE; 7.307 + w_result_sel_load_x <= #1 `FALSE; 7.308 `ifdef CFG_PL_MULTIPLY_ENABLED 7.309 - w_result_sel_mul_x <= `FALSE; 7.310 + w_result_sel_mul_x <= #1 `FALSE; 7.311 `endif 7.312 - x_bypass_enable_x <= `FALSE; 7.313 - m_bypass_enable_x <= `FALSE; 7.314 - write_enable_x <= `FALSE; 7.315 - write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}}; 7.316 - csr_x <= {`LM32_CSR_WIDTH{1'b0}}; 7.317 - load_x <= `FALSE; 7.318 - store_x <= `FALSE; 7.319 - size_x <= {`LM32_SIZE_WIDTH{1'b0}}; 7.320 - sign_extend_x <= `FALSE; 7.321 - adder_op_x <= `FALSE; 7.322 - adder_op_x_n <= `FALSE; 7.323 - logic_op_x <= 4'h0; 7.324 + x_bypass_enable_x <= #1 `FALSE; 7.325 + m_bypass_enable_x <= #1 `FALSE; 7.326 + write_enable_x <= #1 `FALSE; 7.327 + write_idx_x <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 7.328 + csr_x <= #1 {`LM32_CSR_WIDTH{1'b0}}; 7.329 + load_x <= #1 `FALSE; 7.330 + store_x <= #1 `FALSE; 7.331 + size_x <= #1 {`LM32_SIZE_WIDTH{1'b0}}; 7.332 + sign_extend_x <= #1 `FALSE; 7.333 + adder_op_x <= #1 `FALSE; 7.334 + adder_op_x_n <= #1 `FALSE; 7.335 + logic_op_x <= #1 4'h0; 7.336 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.337 - direction_x <= `FALSE; 7.338 + direction_x <= #1 `FALSE; 7.339 `endif 7.340 `ifdef CFG_ROTATE_ENABLED 7.341 - rotate_x <= `FALSE; 7.342 + rotate_x <= #1 `FALSE; 7.343 7.344 `endif 7.345 - branch_x <= `FALSE; 7.346 - branch_predict_x <= `FALSE; 7.347 - branch_predict_taken_x <= `FALSE; 7.348 - condition_x <= `LM32_CONDITION_U1; 7.349 + branch_x <= #1 `FALSE; 7.350 + branch_predict_x <= #1 `FALSE; 7.351 + branch_predict_taken_x <= #1 `FALSE; 7.352 + condition_x <= #1 `LM32_CONDITION_U1; 7.353 `ifdef CFG_DEBUG_ENABLED 7.354 - break_x <= `FALSE; 7.355 + break_x <= #1 `FALSE; 7.356 `endif 7.357 - scall_x <= `FALSE; 7.358 - eret_x <= `FALSE; 7.359 + scall_x <= #1 `FALSE; 7.360 + eret_x <= #1 `FALSE; 7.361 `ifdef CFG_DEBUG_ENABLED 7.362 - bret_x <= `FALSE; 7.363 + bret_x <= #1 `FALSE; 7.364 `endif 7.365 `ifdef CFG_BUS_ERRORS_ENABLED 7.366 - bus_error_x <= `FALSE; 7.367 - data_bus_error_exception_m <= `FALSE; 7.368 + bus_error_x <= #1 `FALSE; 7.369 + data_bus_error_exception_m <= #1 `FALSE; 7.370 `endif 7.371 - csr_write_enable_x <= `FALSE; 7.372 - operand_m <= {`LM32_WORD_WIDTH{1'b0}}; 7.373 - branch_target_m <= {`LM32_WORD_WIDTH{1'b0}}; 7.374 - m_result_sel_compare_m <= `FALSE; 7.375 + csr_write_enable_x <= #1 `FALSE; 7.376 + operand_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.377 + branch_target_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.378 + m_result_sel_compare_m <= #1 `FALSE; 7.379 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.380 - m_result_sel_shift_m <= `FALSE; 7.381 + m_result_sel_shift_m <= #1 `FALSE; 7.382 `endif 7.383 - w_result_sel_load_m <= `FALSE; 7.384 + w_result_sel_load_m <= #1 `FALSE; 7.385 `ifdef CFG_PL_MULTIPLY_ENABLED 7.386 - w_result_sel_mul_m <= `FALSE; 7.387 + w_result_sel_mul_m <= #1 `FALSE; 7.388 `endif 7.389 - m_bypass_enable_m <= `FALSE; 7.390 - branch_m <= `FALSE; 7.391 - branch_predict_m <= `FALSE; 7.392 - branch_predict_taken_m <= `FALSE; 7.393 - exception_m <= `FALSE; 7.394 - load_m <= `FALSE; 7.395 - store_m <= `FALSE; 7.396 - write_enable_m <= `FALSE; 7.397 - write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}}; 7.398 - condition_met_m <= `FALSE; 7.399 + m_bypass_enable_m <= #1 `FALSE; 7.400 + branch_m <= #1 `FALSE; 7.401 + branch_predict_m <= #1 `FALSE; 7.402 + branch_predict_taken_m <= #1 `FALSE; 7.403 + exception_m <= #1 `FALSE; 7.404 + load_m <= #1 `FALSE; 7.405 + store_m <= #1 `FALSE; 7.406 + write_enable_m <= #1 `FALSE; 7.407 + write_idx_m <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 7.408 + condition_met_m <= #1 `FALSE; 7.409 `ifdef CFG_DCACHE_ENABLED 7.410 - dflush_m <= `FALSE; 7.411 + dflush_m <= #1 `FALSE; 7.412 `endif 7.413 `ifdef CFG_DEBUG_ENABLED 7.414 - debug_exception_m <= `FALSE; 7.415 - non_debug_exception_m <= `FALSE; 7.416 + debug_exception_m <= #1 `FALSE; 7.417 + non_debug_exception_m <= #1 `FALSE; 7.418 `endif 7.419 - operand_w <= {`LM32_WORD_WIDTH{1'b0}}; 7.420 - w_result_sel_load_w <= `FALSE; 7.421 + operand_w <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.422 + w_result_sel_load_w <= #1 `FALSE; 7.423 `ifdef CFG_PL_MULTIPLY_ENABLED 7.424 - w_result_sel_mul_w <= `FALSE; 7.425 + w_result_sel_mul_w <= #1 `FALSE; 7.426 `endif 7.427 - write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}}; 7.428 - write_enable_w <= `FALSE; 7.429 + write_idx_w <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 7.430 + write_enable_w <= #1 `FALSE; 7.431 `ifdef CFG_DEBUG_ENABLED 7.432 - debug_exception_w <= `FALSE; 7.433 - non_debug_exception_w <= `FALSE; 7.434 + debug_exception_w <= #1 `FALSE; 7.435 + non_debug_exception_w <= #1 `FALSE; 7.436 `else 7.437 - exception_w <= `FALSE; 7.438 + exception_w <= #1 `FALSE; 7.439 `endif 7.440 `ifdef CFG_BUS_ERRORS_ENABLED 7.441 - memop_pc_w <= {`LM32_PC_WIDTH{1'b0}}; 7.442 + memop_pc_w <= #1 {`LM32_PC_WIDTH{1'b0}}; 7.443 `endif 7.444 end 7.445 else 7.446 @@ -2362,105 +2404,105 @@ 7.447 if (stall_x == `FALSE) 7.448 begin 7.449 `ifdef CFG_USER_ENABLED 7.450 - user_opcode <= user_opcode_d; 7.451 + user_opcode <= #1 user_opcode_d; 7.452 `endif 7.453 - operand_0_x <= d_result_0; 7.454 - operand_1_x <= d_result_1; 7.455 - store_operand_x <= bypass_data_1; 7.456 - branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 7.457 - x_result_sel_csr_x <= x_result_sel_csr_d; 7.458 + operand_0_x <= #1 d_result_0; 7.459 + operand_1_x <= #1 d_result_1; 7.460 + store_operand_x <= #1 bypass_data_1; 7.461 + branch_target_x <= #1 branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 7.462 + x_result_sel_csr_x <= #1 x_result_sel_csr_d; 7.463 `ifdef LM32_MC_ARITHMETIC_ENABLED 7.464 - x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d; 7.465 + x_result_sel_mc_arith_x <= #1 x_result_sel_mc_arith_d; 7.466 `endif 7.467 `ifdef LM32_NO_BARREL_SHIFT 7.468 - x_result_sel_shift_x <= x_result_sel_shift_d; 7.469 + x_result_sel_shift_x <= #1 x_result_sel_shift_d; 7.470 `endif 7.471 `ifdef CFG_SIGN_EXTEND_ENABLED 7.472 - x_result_sel_sext_x <= x_result_sel_sext_d; 7.473 + x_result_sel_sext_x <= #1 x_result_sel_sext_d; 7.474 `endif 7.475 - x_result_sel_logic_x <= x_result_sel_logic_d; 7.476 + x_result_sel_logic_x <= #1 x_result_sel_logic_d; 7.477 `ifdef CFG_USER_ENABLED 7.478 - x_result_sel_user_x <= x_result_sel_user_d; 7.479 + x_result_sel_user_x <= #1 x_result_sel_user_d; 7.480 `endif 7.481 - x_result_sel_add_x <= x_result_sel_add_d; 7.482 - m_result_sel_compare_x <= m_result_sel_compare_d; 7.483 + x_result_sel_add_x <= #1 x_result_sel_add_d; 7.484 + m_result_sel_compare_x <= #1 m_result_sel_compare_d; 7.485 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.486 - m_result_sel_shift_x <= m_result_sel_shift_d; 7.487 + m_result_sel_shift_x <= #1 m_result_sel_shift_d; 7.488 `endif 7.489 - w_result_sel_load_x <= w_result_sel_load_d; 7.490 + w_result_sel_load_x <= #1 w_result_sel_load_d; 7.491 `ifdef CFG_PL_MULTIPLY_ENABLED 7.492 - w_result_sel_mul_x <= w_result_sel_mul_d; 7.493 + w_result_sel_mul_x <= #1 w_result_sel_mul_d; 7.494 `endif 7.495 - x_bypass_enable_x <= x_bypass_enable_d; 7.496 - m_bypass_enable_x <= m_bypass_enable_d; 7.497 - load_x <= load_d; 7.498 - store_x <= store_d; 7.499 - branch_x <= branch_d; 7.500 - branch_predict_x <= branch_predict_d; 7.501 - branch_predict_taken_x <= branch_predict_taken_d; 7.502 - write_idx_x <= write_idx_d; 7.503 - csr_x <= csr_d; 7.504 - size_x <= size_d; 7.505 - sign_extend_x <= sign_extend_d; 7.506 - adder_op_x <= adder_op_d; 7.507 - adder_op_x_n <= ~adder_op_d; 7.508 - logic_op_x <= logic_op_d; 7.509 + x_bypass_enable_x <= #1 x_bypass_enable_d; 7.510 + m_bypass_enable_x <= #1 m_bypass_enable_d; 7.511 + load_x <= #1 load_d; 7.512 + store_x <= #1 store_d; 7.513 + branch_x <= #1 branch_d; 7.514 + branch_predict_x <= #1 branch_predict_d; 7.515 + branch_predict_taken_x <= #1 branch_predict_taken_d; 7.516 + write_idx_x <= #1 write_idx_d; 7.517 + csr_x <= #1 csr_d; 7.518 + size_x <= #1 size_d; 7.519 + sign_extend_x <= #1 sign_extend_d; 7.520 + adder_op_x <= #1 adder_op_d; 7.521 + adder_op_x_n <= #1 ~adder_op_d; 7.522 + logic_op_x <= #1 logic_op_d; 7.523 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.524 - direction_x <= direction_d; 7.525 + direction_x <= #1 direction_d; 7.526 `endif 7.527 `ifdef CFG_ROTATE_ENABLED 7.528 - rotate_x <= rotate_d; 7.529 + rotate_x <= #1 rotate_d; 7.530 `endif 7.531 - condition_x <= condition_d; 7.532 - csr_write_enable_x <= csr_write_enable_d; 7.533 + condition_x <= #1 condition_d; 7.534 + csr_write_enable_x <= #1 csr_write_enable_d; 7.535 `ifdef CFG_DEBUG_ENABLED 7.536 - break_x <= break_d; 7.537 + break_x <= #1 break_d; 7.538 `endif 7.539 - scall_x <= scall_d; 7.540 + scall_x <= #1 scall_d; 7.541 `ifdef CFG_BUS_ERRORS_ENABLED 7.542 - bus_error_x <= bus_error_d; 7.543 + bus_error_x <= #1 bus_error_d; 7.544 `endif 7.545 - eret_x <= eret_d; 7.546 + eret_x <= #1 eret_d; 7.547 `ifdef CFG_DEBUG_ENABLED 7.548 - bret_x <= bret_d; 7.549 + bret_x <= #1 bret_d; 7.550 `endif 7.551 - write_enable_x <= write_enable_d; 7.552 + write_enable_x <= #1 write_enable_d; 7.553 end 7.554 7.555 // X/M stage registers 7.556 7.557 if (stall_m == `FALSE) 7.558 begin 7.559 - operand_m <= x_result; 7.560 - m_result_sel_compare_m <= m_result_sel_compare_x; 7.561 + operand_m <= #1 x_result; 7.562 + m_result_sel_compare_m <= #1 m_result_sel_compare_x; 7.563 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.564 - m_result_sel_shift_m <= m_result_sel_shift_x; 7.565 + m_result_sel_shift_m <= #1 m_result_sel_shift_x; 7.566 `endif 7.567 if (exception_x == `TRUE) 7.568 begin 7.569 - w_result_sel_load_m <= `FALSE; 7.570 + w_result_sel_load_m <= #1 `FALSE; 7.571 `ifdef CFG_PL_MULTIPLY_ENABLED 7.572 - w_result_sel_mul_m <= `FALSE; 7.573 + w_result_sel_mul_m <= #1 `FALSE; 7.574 `endif 7.575 end 7.576 else 7.577 begin 7.578 - w_result_sel_load_m <= w_result_sel_load_x; 7.579 + w_result_sel_load_m <= #1 w_result_sel_load_x; 7.580 `ifdef CFG_PL_MULTIPLY_ENABLED 7.581 - w_result_sel_mul_m <= w_result_sel_mul_x; 7.582 + w_result_sel_mul_m <= #1 w_result_sel_mul_x; 7.583 `endif 7.584 end 7.585 - m_bypass_enable_m <= m_bypass_enable_x; 7.586 + m_bypass_enable_m <= #1 m_bypass_enable_x; 7.587 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.588 `endif 7.589 - load_m <= load_x; 7.590 - store_m <= store_x; 7.591 + load_m <= #1 load_x; 7.592 + store_m <= #1 store_x; 7.593 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH 7.594 - branch_m <= branch_x && !branch_taken_x; 7.595 + branch_m <= #1 branch_x && !branch_taken_x; 7.596 `else 7.597 - branch_m <= branch_x; 7.598 - branch_predict_m <= branch_predict_x; 7.599 - branch_predict_taken_m <= branch_predict_taken_x; 7.600 + branch_m <= #1 branch_x; 7.601 + branch_predict_m <= #1 branch_predict_x; 7.602 + branch_predict_taken_m <= #1 branch_predict_taken_x; 7.603 `endif 7.604 `ifdef CFG_DEBUG_ENABLED 7.605 // Data bus errors are generated by the wishbone and are 7.606 @@ -2469,45 +2511,48 @@ 7.607 // in same cycle (causing a debug exception). Handle non 7.608 // -debug exception first! 7.609 if (non_debug_exception_x == `TRUE) 7.610 - write_idx_m <= `LM32_EA_REG; 7.611 + write_idx_m <= #1 `LM32_EA_REG; 7.612 else if (debug_exception_x == `TRUE) 7.613 - write_idx_m <= `LM32_BA_REG; 7.614 + write_idx_m <= #1 `LM32_BA_REG; 7.615 else 7.616 - write_idx_m <= write_idx_x; 7.617 + write_idx_m <= #1 write_idx_x; 7.618 `else 7.619 if (exception_x == `TRUE) 7.620 - write_idx_m <= `LM32_EA_REG; 7.621 + write_idx_m <= #1 `LM32_EA_REG; 7.622 else 7.623 - write_idx_m <= write_idx_x; 7.624 + write_idx_m <= #1 write_idx_x; 7.625 `endif 7.626 - condition_met_m <= condition_met_x; 7.627 + condition_met_m <= #1 condition_met_x; 7.628 `ifdef CFG_DEBUG_ENABLED 7.629 if (exception_x == `TRUE) 7.630 if ((dc_re == `TRUE) 7.631 + `ifdef CFG_ALTERNATE_EBA 7.632 + || (at_debug == `TRUE) 7.633 + `endif 7.634 || ((debug_exception_x == `TRUE) 7.635 && (non_debug_exception_x == `FALSE))) 7.636 - branch_target_m <= {deba, eid_x, {3{1'b0}}}; 7.637 + branch_target_m <= #1 {deba, eid_x, {3{1'b0}}}; 7.638 else 7.639 - branch_target_m <= {eba, eid_x, {3{1'b0}}}; 7.640 + branch_target_m <= #1 {eba, eid_x, {3{1'b0}}}; 7.641 else 7.642 - branch_target_m <= branch_target_x; 7.643 + branch_target_m <= #1 branch_target_x; 7.644 `else 7.645 - branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 7.646 + branch_target_m <= #1 exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 7.647 `endif 7.648 `ifdef CFG_TRACE_ENABLED 7.649 - eid_m <= eid_x; 7.650 + eid_m <= #1 eid_x; 7.651 `endif 7.652 `ifdef CFG_DCACHE_ENABLED 7.653 - dflush_m <= dflush_x; 7.654 + dflush_m <= #1 dflush_x; 7.655 `endif 7.656 - eret_m <= eret_q_x; 7.657 + eret_m <= #1 eret_q_x; 7.658 `ifdef CFG_DEBUG_ENABLED 7.659 - bret_m <= bret_q_x; 7.660 + bret_m <= #1 bret_q_x; 7.661 `endif 7.662 - write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x; 7.663 + write_enable_m <= #1 exception_x == `TRUE ? `TRUE : write_enable_x; 7.664 `ifdef CFG_DEBUG_ENABLED 7.665 - debug_exception_m <= debug_exception_x; 7.666 - non_debug_exception_m <= non_debug_exception_x; 7.667 + debug_exception_m <= #1 debug_exception_x; 7.668 + non_debug_exception_m <= #1 non_debug_exception_x; 7.669 `endif 7.670 end 7.671 7.672 @@ -2515,11 +2560,11 @@ 7.673 if (stall_m == `FALSE) 7.674 begin 7.675 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 7.676 - exception_m <= `TRUE; 7.677 + exception_m <= #1 `TRUE; 7.678 else 7.679 - exception_m <= `FALSE; 7.680 + exception_m <= #1 `FALSE; 7.681 `ifdef CFG_BUS_ERRORS_ENABLED 7.682 - data_bus_error_exception_m <= (data_bus_error_exception == `TRUE) 7.683 + data_bus_error_exception_m <= #1 (data_bus_error_exception == `TRUE) 7.684 `ifdef CFG_DEBUG_ENABLED 7.685 && (reset_exception == `FALSE) 7.686 `endif 7.687 @@ -2529,36 +2574,37 @@ 7.688 7.689 // M/W stage registers 7.690 `ifdef CFG_BUS_ERRORS_ENABLED 7.691 - operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 7.692 + operand_w <= #1 exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 7.693 `else 7.694 - operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 7.695 + operand_w <= #1 exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 7.696 `endif 7.697 - w_result_sel_load_w <= w_result_sel_load_m; 7.698 + w_result_sel_load_w <= #1 w_result_sel_load_m; 7.699 `ifdef CFG_PL_MULTIPLY_ENABLED 7.700 - w_result_sel_mul_w <= w_result_sel_mul_m; 7.701 + w_result_sel_mul_w <= #1 w_result_sel_mul_m; 7.702 `endif 7.703 - write_idx_w <= write_idx_m; 7.704 + write_idx_w <= #1 write_idx_m; 7.705 `ifdef CFG_TRACE_ENABLED 7.706 - eid_w <= eid_m; 7.707 - eret_w <= eret_m; 7.708 + eid_w <= #1 eid_m; 7.709 + eret_w <= #1 eret_m; 7.710 `ifdef CFG_DEBUG_ENABLED 7.711 - bret_w <= bret_m; 7.712 + bret_w <= #1 bret_m; 7.713 `endif 7.714 `endif 7.715 - write_enable_w <= write_enable_m; 7.716 + write_enable_w <= #1 write_enable_m; 7.717 `ifdef CFG_DEBUG_ENABLED 7.718 - debug_exception_w <= debug_exception_m; 7.719 - non_debug_exception_w <= non_debug_exception_m; 7.720 + debug_exception_w <= #1 debug_exception_m; 7.721 + non_debug_exception_w <= #1 non_debug_exception_m; 7.722 `else 7.723 - exception_w <= exception_m; 7.724 + exception_w <= #1 exception_m; 7.725 `endif 7.726 `ifdef CFG_BUS_ERRORS_ENABLED 7.727 if ( (stall_m == `FALSE) 7.728 + && (data_bus_error_exception == `FALSE) 7.729 && ( (load_q_m == `TRUE) 7.730 || (store_q_m == `TRUE) 7.731 ) 7.732 ) 7.733 - memop_pc_w <= pc_m; 7.734 + memop_pc_w <= #1 pc_m; 7.735 `endif 7.736 end 7.737 end 7.738 @@ -2570,26 +2616,26 @@ 7.739 begin 7.740 if (rst_i == `TRUE) 7.741 begin 7.742 - use_buf <= `FALSE; 7.743 - reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}}; 7.744 - reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}}; 7.745 + use_buf <= #1 `FALSE; 7.746 + reg_data_buf_0 <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.747 + reg_data_buf_1 <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.748 end 7.749 else 7.750 begin 7.751 if (stall_d == `FALSE) 7.752 - use_buf <= `FALSE; 7.753 + use_buf <= #1 `FALSE; 7.754 else if (use_buf == `FALSE) 7.755 begin 7.756 - reg_data_buf_0 <= reg_data_live_0; 7.757 - reg_data_buf_1 <= reg_data_live_1; 7.758 - use_buf <= `TRUE; 7.759 + reg_data_buf_0 <= #1 reg_data_live_0; 7.760 + reg_data_buf_1 <= #1 reg_data_live_1; 7.761 + use_buf <= #1 `TRUE; 7.762 end 7.763 if (reg_write_enable_q_w == `TRUE) 7.764 begin 7.765 if (write_idx_w == read_idx_0_d) 7.766 - reg_data_buf_0 <= w_result; 7.767 + reg_data_buf_0 <= #1 w_result; 7.768 if (write_idx_w == read_idx_1_d) 7.769 - reg_data_buf_1 <= w_result; 7.770 + reg_data_buf_1 <= #1 w_result; 7.771 end 7.772 end 7.773 end 7.774 @@ -2601,42 +2647,42 @@ 7.775 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.776 begin 7.777 if (rst_i == `TRUE) begin 7.778 - registers[0] <= {`LM32_WORD_WIDTH{1'b0}}; 7.779 - registers[1] <= {`LM32_WORD_WIDTH{1'b0}}; 7.780 - registers[2] <= {`LM32_WORD_WIDTH{1'b0}}; 7.781 - registers[3] <= {`LM32_WORD_WIDTH{1'b0}}; 7.782 - registers[4] <= {`LM32_WORD_WIDTH{1'b0}}; 7.783 - registers[5] <= {`LM32_WORD_WIDTH{1'b0}}; 7.784 - registers[6] <= {`LM32_WORD_WIDTH{1'b0}}; 7.785 - registers[7] <= {`LM32_WORD_WIDTH{1'b0}}; 7.786 - registers[8] <= {`LM32_WORD_WIDTH{1'b0}}; 7.787 - registers[9] <= {`LM32_WORD_WIDTH{1'b0}}; 7.788 - registers[10] <= {`LM32_WORD_WIDTH{1'b0}}; 7.789 - registers[11] <= {`LM32_WORD_WIDTH{1'b0}}; 7.790 - registers[12] <= {`LM32_WORD_WIDTH{1'b0}}; 7.791 - registers[13] <= {`LM32_WORD_WIDTH{1'b0}}; 7.792 - registers[14] <= {`LM32_WORD_WIDTH{1'b0}}; 7.793 - registers[15] <= {`LM32_WORD_WIDTH{1'b0}}; 7.794 - registers[16] <= {`LM32_WORD_WIDTH{1'b0}}; 7.795 - registers[17] <= {`LM32_WORD_WIDTH{1'b0}}; 7.796 - registers[18] <= {`LM32_WORD_WIDTH{1'b0}}; 7.797 - registers[19] <= {`LM32_WORD_WIDTH{1'b0}}; 7.798 - registers[20] <= {`LM32_WORD_WIDTH{1'b0}}; 7.799 - registers[21] <= {`LM32_WORD_WIDTH{1'b0}}; 7.800 - registers[22] <= {`LM32_WORD_WIDTH{1'b0}}; 7.801 - registers[23] <= {`LM32_WORD_WIDTH{1'b0}}; 7.802 - registers[24] <= {`LM32_WORD_WIDTH{1'b0}}; 7.803 - registers[25] <= {`LM32_WORD_WIDTH{1'b0}}; 7.804 - registers[26] <= {`LM32_WORD_WIDTH{1'b0}}; 7.805 - registers[27] <= {`LM32_WORD_WIDTH{1'b0}}; 7.806 - registers[28] <= {`LM32_WORD_WIDTH{1'b0}}; 7.807 - registers[29] <= {`LM32_WORD_WIDTH{1'b0}}; 7.808 - registers[30] <= {`LM32_WORD_WIDTH{1'b0}}; 7.809 - registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 7.810 + registers[0] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.811 + registers[1] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.812 + registers[2] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.813 + registers[3] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.814 + registers[4] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.815 + registers[5] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.816 + registers[6] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.817 + registers[7] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.818 + registers[8] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.819 + registers[9] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.820 + registers[10] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.821 + registers[11] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.822 + registers[12] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.823 + registers[13] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.824 + registers[14] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.825 + registers[15] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.826 + registers[16] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.827 + registers[17] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.828 + registers[18] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.829 + registers[19] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.830 + registers[20] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.831 + registers[21] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.832 + registers[22] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.833 + registers[23] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.834 + registers[24] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.835 + registers[25] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.836 + registers[26] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.837 + registers[27] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.838 + registers[28] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.839 + registers[29] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.840 + registers[30] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.841 + registers[31] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 7.842 end 7.843 else begin 7.844 if (reg_write_enable_q_w == `TRUE) 7.845 - registers[write_idx_w] <= w_result; 7.846 + registers[write_idx_w] <= #1 w_result; 7.847 end 7.848 end 7.849 `endif 7.850 @@ -2647,19 +2693,19 @@ 7.851 begin 7.852 if (rst_i == `TRUE) 7.853 begin 7.854 - trace_pc_valid <= `FALSE; 7.855 - trace_pc <= {`LM32_PC_WIDTH{1'b0}}; 7.856 - trace_exception <= `FALSE; 7.857 - trace_eid <= `LM32_EID_RESET; 7.858 - trace_eret <= `FALSE; 7.859 + trace_pc_valid <= #1 `FALSE; 7.860 + trace_pc <= #1 {`LM32_PC_WIDTH{1'b0}}; 7.861 + trace_exception <= #1 `FALSE; 7.862 + trace_eid <= #1 `LM32_EID_RESET; 7.863 + trace_eret <= #1 `FALSE; 7.864 `ifdef CFG_DEBUG_ENABLED 7.865 - trace_bret <= `FALSE; 7.866 + trace_bret <= #1 `FALSE; 7.867 `endif 7.868 - pc_c <= `CFG_EBA_RESET/4; 7.869 + pc_c <= #1 `CFG_EBA_RESET/4; 7.870 end 7.871 else 7.872 begin 7.873 - trace_pc_valid <= `FALSE; 7.874 + trace_pc_valid <= #1 `FALSE; 7.875 // Has an exception occured 7.876 `ifdef CFG_DEBUG_ENABLED 7.877 if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE)) 7.878 @@ -2667,13 +2713,13 @@ 7.879 if (exception_q_w == `TRUE) 7.880 `endif 7.881 begin 7.882 - trace_exception <= `TRUE; 7.883 - trace_pc_valid <= `TRUE; 7.884 - trace_pc <= pc_w; 7.885 - trace_eid <= eid_w; 7.886 + trace_exception <= #1 `TRUE; 7.887 + trace_pc_valid <= #1 `TRUE; 7.888 + trace_pc <= #1 pc_w; 7.889 + trace_eid <= #1 eid_w; 7.890 end 7.891 else 7.892 - trace_exception <= `FALSE; 7.893 + trace_exception <= #1 `FALSE; 7.894 7.895 if ((valid_w == `TRUE) && (!kill_w)) 7.896 begin 7.897 @@ -2681,22 +2727,22 @@ 7.898 if (pc_c + 1'b1 != pc_w) 7.899 begin 7.900 // Non-sequential instruction 7.901 - trace_pc_valid <= `TRUE; 7.902 - trace_pc <= pc_w; 7.903 + trace_pc_valid <= #1 `TRUE; 7.904 + trace_pc <= #1 pc_w; 7.905 end 7.906 // Record PC so we can determine if next instruction is sequential or not 7.907 - pc_c <= pc_w; 7.908 + pc_c <= #1 pc_w; 7.909 // Indicate if it was an eret/bret instruction 7.910 - trace_eret <= eret_w; 7.911 + trace_eret <= #1 eret_w; 7.912 `ifdef CFG_DEBUG_ENABLED 7.913 - trace_bret <= bret_w; 7.914 + trace_bret <= #1 bret_w; 7.915 `endif 7.916 end 7.917 else 7.918 begin 7.919 - trace_eret <= `FALSE; 7.920 + trace_eret <= #1 `FALSE; 7.921 `ifdef CFG_DEBUG_ENABLED 7.922 - trace_bret <= `FALSE; 7.923 + trace_bret <= #1 `FALSE; 7.924 `endif 7.925 end 7.926 end
8.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_dcache.v 8.2 --- a/lm32_dcache.v Sun Mar 06 21:14:43 2011 +0000 8.3 +++ b/lm32_dcache.v Sat Aug 06 00:02:46 2011 +0100 8.4 @@ -1,18 +1,39 @@ 8.5 -// ============================================================================= 8.6 -// COPYRIGHT NOTICE 8.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 8.8 -// ALL RIGHTS RESERVED 8.9 -// This confidential and proprietary software may be used only as authorised by 8.10 -// a licensing agreement from Lattice Semiconductor Corporation. 8.11 -// The entire notice above must be reproduced on all authorized copies and 8.12 -// copies may only be made to the extent permitted by a licensing agreement from 8.13 -// Lattice Semiconductor Corporation. 8.14 +// ================================================================== 8.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 8.16 +// ------------------------------------------------------------------ 8.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 8.18 +// ALL RIGHTS RESERVED 8.19 +// ------------------------------------------------------------------ 8.20 +// 8.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 8.22 +// 8.23 +// Permission: 8.24 +// 8.25 +// Lattice Semiconductor grants permission to use this code 8.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 8.27 +// Open Source License Agreement. 8.28 +// 8.29 +// Disclaimer: 8.30 // 8.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 8.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 8.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 8.34 -// U.S.A email: techsupport@latticesemi.com 8.35 -// =============================================================================/ 8.36 +// Lattice Semiconductor provides no warranty regarding the use or 8.37 +// functionality of this code. It is the user's responsibility to 8.38 +// verify the user’s design for consistency and functionality through 8.39 +// the use of formal verification methods. 8.40 +// 8.41 +// -------------------------------------------------------------------- 8.42 +// 8.43 +// Lattice Semiconductor Corporation 8.44 +// 5555 NE Moore Court 8.45 +// Hillsboro, OR 97214 8.46 +// U.S.A 8.47 +// 8.48 +// TEL: 1-800-Lattice (USA and Canada) 8.49 +// 503-286-8001 (other locations) 8.50 +// 8.51 +// web: http://www.latticesemi.com/ 8.52 +// email: techsupport@latticesemi.com 8.53 +// 8.54 +// -------------------------------------------------------------------- 8.55 // FILE DETAILS 8.56 // Project : LatticeMico32 8.57 // File : lm32_dcache.v 8.58 @@ -420,11 +441,11 @@ 8.59 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 8.60 begin 8.61 if (rst_i == `TRUE) 8.62 - refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 8.63 + refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1}; 8.64 else 8.65 begin 8.66 if (refill_request == `TRUE) 8.67 - refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 8.68 + refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]}; 8.69 end 8.70 end 8.71 end 8.72 @@ -434,9 +455,9 @@ 8.73 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 8.74 begin 8.75 if (rst_i == `TRUE) 8.76 - refilling <= `FALSE; 8.77 + refilling <= #1 `FALSE; 8.78 else 8.79 - refilling <= refill; 8.80 + refilling <= #1 refill; 8.81 end 8.82 8.83 // Instruction cache control FSM 8.84 @@ -444,11 +465,11 @@ 8.85 begin 8.86 if (rst_i == `TRUE) 8.87 begin 8.88 - state <= `LM32_DC_STATE_FLUSH; 8.89 - flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 8.90 - refill_request <= `FALSE; 8.91 - refill_address <= {`LM32_WORD_WIDTH{1'bx}}; 8.92 - restart_request <= `FALSE; 8.93 + state <= #1 `LM32_DC_STATE_FLUSH; 8.94 + flush_set <= #1 {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 8.95 + refill_request <= #1 `FALSE; 8.96 + refill_address <= #1 {`LM32_WORD_WIDTH{1'bx}}; 8.97 + restart_request <= #1 `FALSE; 8.98 end 8.99 else 8.100 begin 8.101 @@ -458,35 +479,35 @@ 8.102 `LM32_DC_STATE_FLUSH: 8.103 begin 8.104 if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}}) 8.105 - state <= `LM32_DC_STATE_CHECK; 8.106 - flush_set <= flush_set - 1'b1; 8.107 + state <= #1 `LM32_DC_STATE_CHECK; 8.108 + flush_set <= #1 flush_set - 1'b1; 8.109 end 8.110 8.111 // Check for cache misses 8.112 `LM32_DC_STATE_CHECK: 8.113 begin 8.114 if (stall_a == `FALSE) 8.115 - restart_request <= `FALSE; 8.116 + restart_request <= #1 `FALSE; 8.117 if (miss == `TRUE) 8.118 begin 8.119 - refill_request <= `TRUE; 8.120 - refill_address <= address_m; 8.121 - state <= `LM32_DC_STATE_REFILL; 8.122 + refill_request <= #1 `TRUE; 8.123 + refill_address <= #1 address_m; 8.124 + state <= #1 `LM32_DC_STATE_REFILL; 8.125 end 8.126 else if (dflush == `TRUE) 8.127 - state <= `LM32_DC_STATE_FLUSH; 8.128 + state <= #1 `LM32_DC_STATE_FLUSH; 8.129 end 8.130 8.131 // Refill a cache line 8.132 `LM32_DC_STATE_REFILL: 8.133 begin 8.134 - refill_request <= `FALSE; 8.135 + refill_request <= #1 `FALSE; 8.136 if (refill_ready == `TRUE) 8.137 begin 8.138 if (last_refill == `TRUE) 8.139 begin 8.140 - restart_request <= `TRUE; 8.141 - state <= `LM32_DC_STATE_CHECK; 8.142 + restart_request <= #1 `TRUE; 8.143 + state <= #1 `LM32_DC_STATE_CHECK; 8.144 end 8.145 end 8.146 end 8.147 @@ -502,7 +523,7 @@ 8.148 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 8.149 begin 8.150 if (rst_i == `TRUE) 8.151 - refill_offset <= {addr_offset_width{1'b0}}; 8.152 + refill_offset <= #1 {addr_offset_width{1'b0}}; 8.153 else 8.154 begin 8.155 case (state) 8.156 @@ -511,14 +532,14 @@ 8.157 `LM32_DC_STATE_CHECK: 8.158 begin 8.159 if (miss == `TRUE) 8.160 - refill_offset <= {addr_offset_width{1'b0}}; 8.161 + refill_offset <= #1 {addr_offset_width{1'b0}}; 8.162 end 8.163 8.164 // Refill a cache line 8.165 `LM32_DC_STATE_REFILL: 8.166 begin 8.167 if (refill_ready == `TRUE) 8.168 - refill_offset <= refill_offset + 1'b1; 8.169 + refill_offset <= #1 refill_offset + 1'b1; 8.170 end 8.171 8.172 endcase
9.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_debug.v 9.2 --- a/lm32_debug.v Sun Mar 06 21:14:43 2011 +0000 9.3 +++ b/lm32_debug.v Sat Aug 06 00:02:46 2011 +0100 9.4 @@ -1,18 +1,39 @@ 9.5 -// ============================================================================= 9.6 -// COPYRIGHT NOTICE 9.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 9.8 -// ALL RIGHTS RESERVED 9.9 -// This confidential and proprietary software may be used only as authorised by 9.10 -// a licensing agreement from Lattice Semiconductor Corporation. 9.11 -// The entire notice above must be reproduced on all authorized copies and 9.12 -// copies may only be made to the extent permitted by a licensing agreement from 9.13 -// Lattice Semiconductor Corporation. 9.14 +// ================================================================== 9.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 9.16 +// ------------------------------------------------------------------ 9.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 9.18 +// ALL RIGHTS RESERVED 9.19 +// ------------------------------------------------------------------ 9.20 +// 9.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 9.22 +// 9.23 +// Permission: 9.24 +// 9.25 +// Lattice Semiconductor grants permission to use this code 9.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 9.27 +// Open Source License Agreement. 9.28 +// 9.29 +// Disclaimer: 9.30 // 9.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 9.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 9.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 9.34 -// U.S.A email: techsupport@latticesemi.com 9.35 -// =============================================================================/ 9.36 +// Lattice Semiconductor provides no warranty regarding the use or 9.37 +// functionality of this code. It is the user's responsibility to 9.38 +// verify the user’s design for consistency and functionality through 9.39 +// the use of formal verification methods. 9.40 +// 9.41 +// -------------------------------------------------------------------- 9.42 +// 9.43 +// Lattice Semiconductor Corporation 9.44 +// 5555 NE Moore Court 9.45 +// Hillsboro, OR 97214 9.46 +// U.S.A 9.47 +// 9.48 +// TEL: 1-800-Lattice (USA and Canada) 9.49 +// 503-286-8001 (other locations) 9.50 +// 9.51 +// web: http://www.latticesemi.com/ 9.52 +// email: techsupport@latticesemi.com 9.53 +// 9.54 +// -------------------------------------------------------------------- 9.55 // FILE DETAILS 9.56 // Project : LatticeMico32 9.57 // File : lm32_debug.v 9.58 @@ -226,15 +247,15 @@ 9.59 begin 9.60 if (rst_i == `TRUE) 9.61 begin 9.62 - bp_a[i] <= {`LM32_PC_WIDTH{1'bx}}; 9.63 - bp_e[i] <= `FALSE; 9.64 + bp_a[i] <= #1 {`LM32_PC_WIDTH{1'bx}}; 9.65 + bp_e[i] <= #1 `FALSE; 9.66 end 9.67 else 9.68 begin 9.69 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i)) 9.70 begin 9.71 - bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG]; 9.72 - bp_e[i] <= debug_csr_write_data[0]; 9.73 + bp_a[i] <= #1 debug_csr_write_data[`LM32_PC_RNG]; 9.74 + bp_e[i] <= #1 debug_csr_write_data[0]; 9.75 end 9.76 end 9.77 end 9.78 @@ -249,17 +270,17 @@ 9.79 begin 9.80 if (rst_i == `TRUE) 9.81 begin 9.82 - wp[i] <= {`LM32_WORD_WIDTH{1'bx}}; 9.83 - wpc_c[i] <= `LM32_WPC_C_DISABLED; 9.84 + wp[i] <= #1 {`LM32_WORD_WIDTH{1'bx}}; 9.85 + wpc_c[i] <= #1 `LM32_WPC_C_DISABLED; 9.86 end 9.87 else 9.88 begin 9.89 if (debug_csr_write_enable == `TRUE) 9.90 begin 9.91 if (debug_csr == `LM32_CSR_DC) 9.92 - wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; 9.93 + wpc_c[i] <= #1 debug_csr_write_data[3+i*2:2+i*2]; 9.94 if (debug_csr == `LM32_CSR_WP0 + i) 9.95 - wp[i] <= debug_csr_write_data; 9.96 + wp[i] <= #1 debug_csr_write_data; 9.97 end 9.98 end 9.99 end 9.100 @@ -270,11 +291,11 @@ 9.101 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 9.102 begin 9.103 if (rst_i == `TRUE) 9.104 - dc_re <= `FALSE; 9.105 + dc_re <= #1 `FALSE; 9.106 else 9.107 begin 9.108 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 9.109 - dc_re <= debug_csr_write_data[1]; 9.110 + dc_re <= #1 debug_csr_write_data[1]; 9.111 end 9.112 end 9.113 9.114 @@ -284,18 +305,18 @@ 9.115 begin 9.116 if (rst_i == `TRUE) 9.117 begin 9.118 - state <= `LM32_DEBUG_SS_STATE_IDLE; 9.119 - dc_ss <= `FALSE; 9.120 + state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 9.121 + dc_ss <= #1 `FALSE; 9.122 end 9.123 else 9.124 begin 9.125 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 9.126 begin 9.127 - dc_ss <= debug_csr_write_data[0]; 9.128 + dc_ss <= #1 debug_csr_write_data[0]; 9.129 if (debug_csr_write_data[0] == `FALSE) 9.130 - state <= `LM32_DEBUG_SS_STATE_IDLE; 9.131 + state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 9.132 else 9.133 - state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 9.134 + state <= #1 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 9.135 end 9.136 case (state) 9.137 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET: 9.138 @@ -306,26 +327,26 @@ 9.139 ) 9.140 && (stall_x == `FALSE) 9.141 ) 9.142 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.143 + state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.144 end 9.145 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN: 9.146 begin 9.147 // Wait for an instruction to be executed 9.148 if ((q_x == `TRUE) && (stall_x == `FALSE)) 9.149 - state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 9.150 + state <= #1 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 9.151 end 9.152 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT: 9.153 begin 9.154 // Wait for exception to be raised 9.155 `ifdef CFG_DCACHE_ENABLED 9.156 if (dcache_refill_request == `TRUE) 9.157 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.158 + state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.159 else 9.160 `endif 9.161 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 9.162 begin 9.163 - dc_ss <= `FALSE; 9.164 - state <= `LM32_DEBUG_SS_STATE_RESTART; 9.165 + dc_ss <= #1 `FALSE; 9.166 + state <= #1 `LM32_DEBUG_SS_STATE_RESTART; 9.167 end 9.168 end 9.169 `LM32_DEBUG_SS_STATE_RESTART: 9.170 @@ -333,10 +354,10 @@ 9.171 // Watch to see if stepped instruction is restarted due to a cache miss 9.172 `ifdef CFG_DCACHE_ENABLED 9.173 if (dcache_refill_request == `TRUE) 9.174 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.175 + state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.176 else 9.177 `endif 9.178 - state <= `LM32_DEBUG_SS_STATE_IDLE; 9.179 + state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 9.180 end 9.181 endcase 9.182 end
10.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_decoder.v 10.2 --- a/lm32_decoder.v Sun Mar 06 21:14:43 2011 +0000 10.3 +++ b/lm32_decoder.v Sat Aug 06 00:02:46 2011 +0100 10.4 @@ -1,18 +1,39 @@ 10.5 -// ============================================================================= 10.6 -// COPYRIGHT NOTICE 10.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 10.8 -// ALL RIGHTS RESERVED 10.9 -// This confidential and proprietary software may be used only as authorised by 10.10 -// a licensing agreement from Lattice Semiconductor Corporation. 10.11 -// The entire notice above must be reproduced on all authorized copies and 10.12 -// copies may only be made to the extent permitted by a licensing agreement from 10.13 -// Lattice Semiconductor Corporation. 10.14 +// ================================================================== 10.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 10.16 +// ------------------------------------------------------------------ 10.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 10.18 +// ALL RIGHTS RESERVED 10.19 +// ------------------------------------------------------------------ 10.20 +// 10.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 10.22 +// 10.23 +// Permission: 10.24 +// 10.25 +// Lattice Semiconductor grants permission to use this code 10.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 10.27 +// Open Source License Agreement. 10.28 +// 10.29 +// Disclaimer: 10.30 // 10.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 10.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 10.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 10.34 -// U.S.A email: techsupport@latticesemi.com 10.35 -// =============================================================================/ 10.36 +// Lattice Semiconductor provides no warranty regarding the use or 10.37 +// functionality of this code. It is the user's responsibility to 10.38 +// verify the user’s design for consistency and functionality through 10.39 +// the use of formal verification methods. 10.40 +// 10.41 +// -------------------------------------------------------------------- 10.42 +// 10.43 +// Lattice Semiconductor Corporation 10.44 +// 5555 NE Moore Court 10.45 +// Hillsboro, OR 97214 10.46 +// U.S.A 10.47 +// 10.48 +// TEL: 1-800-Lattice (USA and Canada) 10.49 +// 503-286-8001 (other locations) 10.50 +// 10.51 +// web: http://www.latticesemi.com/ 10.52 +// email: techsupport@latticesemi.com 10.53 +// 10.54 +// -------------------------------------------------------------------- 10.55 // FILE DETAILS 10.56 // Project : LatticeMico32 10.57 // File : lm32_decoder.v
11.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_functions.v 11.2 --- a/lm32_functions.v Sun Mar 06 21:14:43 2011 +0000 11.3 +++ b/lm32_functions.v Sat Aug 06 00:02:46 2011 +0100 11.4 @@ -1,18 +1,39 @@ 11.5 -// ============================================================================= 11.6 -// COPYRIGHT NOTICE 11.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 11.8 -// ALL RIGHTS RESERVED 11.9 -// This confidential and proprietary software may be used only as authorised by 11.10 -// a licensing agreement from Lattice Semiconductor Corporation. 11.11 -// The entire notice above must be reproduced on all authorized copies and 11.12 -// copies may only be made to the extent permitted by a licensing agreement from 11.13 -// Lattice Semiconductor Corporation. 11.14 +// ================================================================== 11.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 11.16 +// ------------------------------------------------------------------ 11.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 11.18 +// ALL RIGHTS RESERVED 11.19 +// ------------------------------------------------------------------ 11.20 +// 11.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 11.22 +// 11.23 +// Permission: 11.24 +// 11.25 +// Lattice Semiconductor grants permission to use this code 11.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 11.27 +// Open Source License Agreement. 11.28 +// 11.29 +// Disclaimer: 11.30 // 11.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 11.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 11.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 11.34 -// U.S.A email: techsupport@latticesemi.com 11.35 -// =============================================================================/ 11.36 +// Lattice Semiconductor provides no warranty regarding the use or 11.37 +// functionality of this code. It is the user's responsibility to 11.38 +// verify the user’s design for consistency and functionality through 11.39 +// the use of formal verification methods. 11.40 +// 11.41 +// -------------------------------------------------------------------- 11.42 +// 11.43 +// Lattice Semiconductor Corporation 11.44 +// 5555 NE Moore Court 11.45 +// Hillsboro, OR 97214 11.46 +// U.S.A 11.47 +// 11.48 +// TEL: 1-800-Lattice (USA and Canada) 11.49 +// 503-286-8001 (other locations) 11.50 +// 11.51 +// web: http://www.latticesemi.com/ 11.52 +// email: techsupport@latticesemi.com 11.53 +// 11.54 +// -------------------------------------------------------------------- 11.55 // FILE DETAILS 11.56 // Project : LatticeMico32 11.57 // File : lm32_functions.v
12.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_icache.v 12.2 --- a/lm32_icache.v Sun Mar 06 21:14:43 2011 +0000 12.3 +++ b/lm32_icache.v Sat Aug 06 00:02:46 2011 +0100 12.4 @@ -1,18 +1,39 @@ 12.5 -// ============================================================================= 12.6 -// COPYRIGHT NOTICE 12.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 12.8 -// ALL RIGHTS RESERVED 12.9 -// This confidential and proprietary software may be used only as authorised by 12.10 -// a licensing agreement from Lattice Semiconductor Corporation. 12.11 -// The entire notice above must be reproduced on all authorized copies and 12.12 -// copies may only be made to the extent permitted by a licensing agreement from 12.13 -// Lattice Semiconductor Corporation. 12.14 +// ================================================================== 12.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 12.16 +// ------------------------------------------------------------------ 12.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 12.18 +// ALL RIGHTS RESERVED 12.19 +// ------------------------------------------------------------------ 12.20 +// 12.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 12.22 +// 12.23 +// Permission: 12.24 +// 12.25 +// Lattice Semiconductor grants permission to use this code 12.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 12.27 +// Open Source License Agreement. 12.28 +// 12.29 +// Disclaimer: 12.30 // 12.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 12.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 12.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 12.34 -// U.S.A email: techsupport@latticesemi.com 12.35 -// =============================================================================/ 12.36 +// Lattice Semiconductor provides no warranty regarding the use or 12.37 +// functionality of this code. It is the user's responsibility to 12.38 +// verify the user’s design for consistency and functionality through 12.39 +// the use of formal verification methods. 12.40 +// 12.41 +// -------------------------------------------------------------------- 12.42 +// 12.43 +// Lattice Semiconductor Corporation 12.44 +// 5555 NE Moore Court 12.45 +// Hillsboro, OR 97214 12.46 +// U.S.A 12.47 +// 12.48 +// TEL: 1-800-Lattice (USA and Canada) 12.49 +// 503-286-8001 (other locations) 12.50 +// 12.51 +// web: http://www.latticesemi.com/ 12.52 +// email: techsupport@latticesemi.com 12.53 +// 12.54 +// -------------------------------------------------------------------- 12.55 // FILE DETAILS 12.56 // Project : LatticeMico32 12.57 // File : lm32_icache.v 12.58 @@ -359,11 +380,11 @@ 12.59 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 12.60 begin 12.61 if (rst_i == `TRUE) 12.62 - refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 12.63 + refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1}; 12.64 else 12.65 begin 12.66 if (miss == `TRUE) 12.67 - refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 12.68 + refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]}; 12.69 end 12.70 end 12.71 end 12.72 @@ -373,9 +394,9 @@ 12.73 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 12.74 begin 12.75 if (rst_i == `TRUE) 12.76 - refilling <= `FALSE; 12.77 + refilling <= #1 `FALSE; 12.78 else 12.79 - refilling <= refill; 12.80 + refilling <= #1 refill; 12.81 end 12.82 12.83 // Instruction cache control FSM 12.84 @@ -383,10 +404,10 @@ 12.85 begin 12.86 if (rst_i == `TRUE) 12.87 begin 12.88 - state <= `LM32_IC_STATE_FLUSH_INIT; 12.89 - flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 12.90 - refill_address <= {`LM32_PC_WIDTH{1'bx}}; 12.91 - restart_request <= `FALSE; 12.92 + state <= #1 `LM32_IC_STATE_FLUSH_INIT; 12.93 + flush_set <= #1 {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 12.94 + refill_address <= #1 {`LM32_PC_WIDTH{1'bx}}; 12.95 + restart_request <= #1 `FALSE; 12.96 end 12.97 else 12.98 begin 12.99 @@ -396,8 +417,8 @@ 12.100 `LM32_IC_STATE_FLUSH_INIT: 12.101 begin 12.102 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 12.103 - state <= `LM32_IC_STATE_CHECK; 12.104 - flush_set <= flush_set - 1'b1; 12.105 + state <= #1 `LM32_IC_STATE_CHECK; 12.106 + flush_set <= #1 flush_set - 1'b1; 12.107 end 12.108 12.109 // Flush the cache in response to an write to the ICC CSR 12.110 @@ -406,28 +427,28 @@ 12.111 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 12.112 `ifdef CFG_IROM_ENABLED 12.113 if (select_f) 12.114 - state <= `LM32_IC_STATE_REFILL; 12.115 + state <= #1 `LM32_IC_STATE_REFILL; 12.116 else 12.117 `endif 12.118 - state <= `LM32_IC_STATE_CHECK; 12.119 + state <= #1 `LM32_IC_STATE_CHECK; 12.120 12.121 - flush_set <= flush_set - 1'b1; 12.122 + flush_set <= #1 flush_set - 1'b1; 12.123 end 12.124 12.125 // Check for cache misses 12.126 `LM32_IC_STATE_CHECK: 12.127 begin 12.128 if (stall_a == `FALSE) 12.129 - restart_request <= `FALSE; 12.130 + restart_request <= #1 `FALSE; 12.131 if (iflush == `TRUE) 12.132 begin 12.133 - refill_address <= address_f; 12.134 - state <= `LM32_IC_STATE_FLUSH; 12.135 + refill_address <= #1 address_f; 12.136 + state <= #1 `LM32_IC_STATE_FLUSH; 12.137 end 12.138 else if (miss == `TRUE) 12.139 begin 12.140 - refill_address <= address_f; 12.141 - state <= `LM32_IC_STATE_REFILL; 12.142 + refill_address <= #1 address_f; 12.143 + state <= #1 `LM32_IC_STATE_REFILL; 12.144 end 12.145 end 12.146 12.147 @@ -438,8 +459,8 @@ 12.148 begin 12.149 if (last_refill == `TRUE) 12.150 begin 12.151 - restart_request <= `TRUE; 12.152 - state <= `LM32_IC_STATE_CHECK; 12.153 + restart_request <= #1 `TRUE; 12.154 + state <= #1 `LM32_IC_STATE_CHECK; 12.155 end 12.156 end 12.157 end 12.158 @@ -455,7 +476,7 @@ 12.159 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 12.160 begin 12.161 if (rst_i == `TRUE) 12.162 - refill_offset <= {addr_offset_width{1'b0}}; 12.163 + refill_offset <= #1 {addr_offset_width{1'b0}}; 12.164 else 12.165 begin 12.166 case (state) 12.167 @@ -464,16 +485,16 @@ 12.168 `LM32_IC_STATE_CHECK: 12.169 begin 12.170 if (iflush == `TRUE) 12.171 - refill_offset <= {addr_offset_width{1'b0}}; 12.172 + refill_offset <= #1 {addr_offset_width{1'b0}}; 12.173 else if (miss == `TRUE) 12.174 - refill_offset <= {addr_offset_width{1'b0}}; 12.175 + refill_offset <= #1 {addr_offset_width{1'b0}}; 12.176 end 12.177 12.178 // Refill a cache line 12.179 `LM32_IC_STATE_REFILL: 12.180 begin 12.181 if (refill_ready == `TRUE) 12.182 - refill_offset <= refill_offset + 1'b1; 12.183 + refill_offset <= #1 refill_offset + 1'b1; 12.184 end 12.185 12.186 endcase
13.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_include.v 13.2 --- a/lm32_include.v Sun Mar 06 21:14:43 2011 +0000 13.3 +++ b/lm32_include.v Sat Aug 06 00:02:46 2011 +0100 13.4 @@ -1,18 +1,39 @@ 13.5 -// ============================================================================= 13.6 -// COPYRIGHT NOTICE 13.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 13.8 -// ALL RIGHTS RESERVED 13.9 -// This confidential and proprietary software may be used only as authorised by 13.10 -// a licensing agreement from Lattice Semiconductor Corporation. 13.11 -// The entire notice above must be reproduced on all authorized copies and 13.12 -// copies may only be made to the extent permitted by a licensing agreement from 13.13 -// Lattice Semiconductor Corporation. 13.14 +// ================================================================== 13.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 13.16 +// ------------------------------------------------------------------ 13.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 13.18 +// ALL RIGHTS RESERVED 13.19 +// ------------------------------------------------------------------ 13.20 +// 13.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 13.22 +// 13.23 +// Permission: 13.24 +// 13.25 +// Lattice Semiconductor grants permission to use this code 13.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 13.27 +// Open Source License Agreement. 13.28 +// 13.29 +// Disclaimer: 13.30 // 13.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 13.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 13.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 13.34 -// U.S.A email: techsupport@latticesemi.com 13.35 -// =============================================================================/ 13.36 +// Lattice Semiconductor provides no warranty regarding the use or 13.37 +// functionality of this code. It is the user's responsibility to 13.38 +// verify the user’s design for consistency and functionality through 13.39 +// the use of formal verification methods. 13.40 +// 13.41 +// -------------------------------------------------------------------- 13.42 +// 13.43 +// Lattice Semiconductor Corporation 13.44 +// 5555 NE Moore Court 13.45 +// Hillsboro, OR 97214 13.46 +// U.S.A 13.47 +// 13.48 +// TEL: 1-800-Lattice (USA and Canada) 13.49 +// 503-286-8001 (other locations) 13.50 +// 13.51 +// web: http://www.latticesemi.com/ 13.52 +// email: techsupport@latticesemi.com 13.53 +// 13.54 +// -------------------------------------------------------------------- 13.55 // FILE DETAILS 13.56 // Project : LatticeMico32 13.57 // File : lm32_include.v
14.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_instruction_unit.v 14.2 --- a/lm32_instruction_unit.v Sun Mar 06 21:14:43 2011 +0000 14.3 +++ b/lm32_instruction_unit.v Sat Aug 06 00:02:46 2011 +0100 14.4 @@ -1,18 +1,39 @@ 14.5 -// ============================================================================= 14.6 -// COPYRIGHT NOTICE 14.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 14.8 -// ALL RIGHTS RESERVED 14.9 -// This confidential and proprietary software may be used only as authorised by 14.10 -// a licensing agreement from Lattice Semiconductor Corporation. 14.11 -// The entire notice above must be reproduced on all authorized copies and 14.12 -// copies may only be made to the extent permitted by a licensing agreement from 14.13 -// Lattice Semiconductor Corporation. 14.14 +// ================================================================== 14.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 14.16 +// ------------------------------------------------------------------ 14.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 14.18 +// ALL RIGHTS RESERVED 14.19 +// ------------------------------------------------------------------ 14.20 +// 14.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 14.22 +// 14.23 +// Permission: 14.24 +// 14.25 +// Lattice Semiconductor grants permission to use this code 14.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 14.27 +// Open Source License Agreement. 14.28 +// 14.29 +// Disclaimer: 14.30 // 14.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 14.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 14.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 14.34 -// U.S.A email: techsupport@latticesemi.com 14.35 -// =============================================================================/ 14.36 +// Lattice Semiconductor provides no warranty regarding the use or 14.37 +// functionality of this code. It is the user's responsibility to 14.38 +// verify the user’s design for consistency and functionality through 14.39 +// the use of formal verification methods. 14.40 +// 14.41 +// -------------------------------------------------------------------- 14.42 +// 14.43 +// Lattice Semiconductor Corporation 14.44 +// 5555 NE Moore Court 14.45 +// Hillsboro, OR 97214 14.46 +// U.S.A 14.47 +// 14.48 +// TEL: 1-800-Lattice (USA and Canada) 14.49 +// 503-286-8001 (other locations) 14.50 +// 14.51 +// web: http://www.latticesemi.com/ 14.52 +// email: techsupport@latticesemi.com 14.53 +// 14.54 +// -------------------------------------------------------------------- 14.55 // FILE DETAILS 14.56 // Project : LatticeMico32 14.57 // File : lm32_instruction_unit.v 14.58 @@ -42,6 +63,9 @@ 14.59 // : instruction cache) to lock up in to an infinite loop due to a 14.60 // : instruction bus error when EBA was set to instruction inline 14.61 // : memory. 14.62 +// Version : 3.8 14.63 +// : Feature: Support for dynamically switching EBA to DEBA via a 14.64 +// : GPIO. 14.65 // ============================================================================= 14.66 14.67 `include "lm32_include.v" 14.68 @@ -54,6 +78,11 @@ 14.69 // ----- Inputs ------- 14.70 clk_i, 14.71 rst_i, 14.72 +`ifdef CFG_DEBUG_ENABLED 14.73 + `ifdef CFG_ALTERNATE_EBA 14.74 + at_debug, 14.75 + `endif 14.76 +`endif 14.77 // From pipeline 14.78 stall_a, 14.79 stall_f, 14.80 @@ -161,6 +190,12 @@ 14.81 input clk_i; // Clock 14.82 input rst_i; // Reset 14.83 14.84 +`ifdef CFG_DEBUG_ENABLED 14.85 + `ifdef CFG_ALTERNATE_EBA 14.86 + input at_debug; // GPIO input that maps EBA to DEBA 14.87 + `endif 14.88 +`endif 14.89 + 14.90 input stall_a; // Stall A stage instruction 14.91 input stall_f; // Stall F stage instruction 14.92 input stall_d; // Stall D stage instruction 14.93 @@ -334,6 +369,10 @@ 14.94 reg jtag_access; // Indicates if a JTAG WB access is in progress 14.95 `endif 14.96 14.97 +`ifdef CFG_ALTERNATE_EBA 14.98 + reg alternate_eba_taken; 14.99 +`endif 14.100 + 14.101 ///////////////////////////////////////////////////// 14.102 // Functions 14.103 ///////////////////////////////////////////////////// 14.104 @@ -381,8 +420,8 @@ 14.105 .ResetB (rst_i), 14.106 .DataInA ({32{1'b0}}), 14.107 .DataInB (irom_store_data_m), 14.108 - .AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 14.109 - .AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 14.110 + .AddressA (pc_a[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), 14.111 + .AddressB (irom_address_xm[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), 14.112 .ClockEnA (!stall_a), 14.113 .ClockEnB (!stall_x || !stall_m), 14.114 .WrA (`FALSE), 14.115 @@ -469,7 +508,7 @@ 14.116 pc_a = restart_address; 14.117 else 14.118 `endif 14.119 - pc_a = pc_f + 1'b1; 14.120 + pc_a = pc_f + 1'b1; 14.121 end 14.122 14.123 // Select where instruction should be fetched from 14.124 @@ -542,52 +581,63 @@ 14.125 14.126 // PC 14.127 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.128 -begin 14.129 - if (rst_i == `TRUE) 14.130 - begin 14.131 - pc_f <= (`CFG_EBA_RESET-4)/4; 14.132 - pc_d <= {`LM32_PC_WIDTH{1'b0}}; 14.133 - pc_x <= {`LM32_PC_WIDTH{1'b0}}; 14.134 - pc_m <= {`LM32_PC_WIDTH{1'b0}}; 14.135 - pc_w <= {`LM32_PC_WIDTH{1'b0}}; 14.136 - end 14.137 - else 14.138 - begin 14.139 - if (stall_f == `FALSE) 14.140 - pc_f <= pc_a; 14.141 - if (stall_d == `FALSE) 14.142 - pc_d <= pc_f; 14.143 - if (stall_x == `FALSE) 14.144 - pc_x <= pc_d; 14.145 - if (stall_m == `FALSE) 14.146 - pc_m <= pc_x; 14.147 - pc_w <= pc_m; 14.148 - end 14.149 -end 14.150 + begin 14.151 + if (rst_i == `TRUE) 14.152 + begin 14.153 +`ifdef CFG_DEBUG_ENABLED 14.154 + `ifdef CFG_ALTERNATE_EBA 14.155 + if (at_debug == `TRUE) 14.156 + pc_f <= #1 (`CFG_DEBA_RESET-4)/4; 14.157 + else 14.158 + pc_f <= #1 (`CFG_EBA_RESET-4)/4; 14.159 + `else 14.160 + pc_f <= #1 (`CFG_EBA_RESET-4)/4; 14.161 + `endif 14.162 +`else 14.163 + pc_f <= #1 (`CFG_EBA_RESET-4)/4; 14.164 +`endif 14.165 + pc_d <= #1 {`LM32_PC_WIDTH{1'b0}}; 14.166 + pc_x <= #1 {`LM32_PC_WIDTH{1'b0}}; 14.167 + pc_m <= #1 {`LM32_PC_WIDTH{1'b0}}; 14.168 + pc_w <= #1 {`LM32_PC_WIDTH{1'b0}}; 14.169 + end 14.170 + else 14.171 + begin 14.172 + if (stall_f == `FALSE) 14.173 + pc_f <= #1 pc_a; 14.174 + if (stall_d == `FALSE) 14.175 + pc_d <= #1 pc_f; 14.176 + if (stall_x == `FALSE) 14.177 + pc_x <= #1 pc_d; 14.178 + if (stall_m == `FALSE) 14.179 + pc_m <= #1 pc_x; 14.180 + pc_w <= #1 pc_m; 14.181 + end 14.182 + end 14.183 14.184 `ifdef LM32_CACHE_ENABLED 14.185 // Address to restart from after a cache miss has been handled 14.186 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.187 begin 14.188 if (rst_i == `TRUE) 14.189 - restart_address <= {`LM32_PC_WIDTH{1'b0}}; 14.190 + restart_address <= #1 {`LM32_PC_WIDTH{1'b0}}; 14.191 else 14.192 begin 14.193 `ifdef CFG_DCACHE_ENABLED 14.194 `ifdef CFG_ICACHE_ENABLED 14.195 // D-cache restart address must take priority, otherwise instructions will be lost 14.196 if (dcache_refill_request == `TRUE) 14.197 - restart_address <= pc_w; 14.198 + restart_address <= #1 pc_w; 14.199 else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request)) 14.200 - restart_address <= icache_refill_address; 14.201 + restart_address <= #1 icache_refill_address; 14.202 `else 14.203 if (dcache_refill_request == `TRUE) 14.204 - restart_address <= pc_w; 14.205 + restart_address <= #1 pc_w; 14.206 `endif 14.207 `else 14.208 `ifdef CFG_ICACHE_ENABLED 14.209 if (icache_refill_request == `TRUE) 14.210 - restart_address <= icache_refill_address; 14.211 + restart_address <= #1 icache_refill_address; 14.212 `endif 14.213 `endif 14.214 end 14.215 @@ -599,11 +649,11 @@ 14.216 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.217 begin 14.218 if (rst_i == `TRUE) 14.219 - irom_select_f <= `FALSE; 14.220 + irom_select_f <= #1 `FALSE; 14.221 else 14.222 begin 14.223 if (stall_f == `FALSE) 14.224 - irom_select_f <= irom_select_a; 14.225 + irom_select_f <= #1 irom_select_a; 14.226 end 14.227 end 14.228 `endif 14.229 @@ -628,25 +678,25 @@ 14.230 begin 14.231 if (rst_i == `TRUE) 14.232 begin 14.233 - i_cyc_o <= `FALSE; 14.234 - i_stb_o <= `FALSE; 14.235 - i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 14.236 - i_cti_o <= `LM32_CTYPE_END; 14.237 - i_lock_o <= `FALSE; 14.238 - icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.239 - icache_refill_ready <= `FALSE; 14.240 + i_cyc_o <= #1 `FALSE; 14.241 + i_stb_o <= #1 `FALSE; 14.242 + i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 14.243 + i_cti_o <= #1 `LM32_CTYPE_END; 14.244 + i_lock_o <= #1 `FALSE; 14.245 + icache_refill_data <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.246 + icache_refill_ready <= #1 `FALSE; 14.247 `ifdef CFG_BUS_ERRORS_ENABLED 14.248 - bus_error_f <= `FALSE; 14.249 + bus_error_f <= #1 `FALSE; 14.250 `endif 14.251 `ifdef CFG_HW_DEBUG_ENABLED 14.252 - i_we_o <= `FALSE; 14.253 - i_sel_o <= 4'b1111; 14.254 - jtag_access <= `FALSE; 14.255 + i_we_o <= #1 `FALSE; 14.256 + i_sel_o <= #1 4'b1111; 14.257 + jtag_access <= #1 `FALSE; 14.258 `endif 14.259 end 14.260 else 14.261 begin 14.262 - icache_refill_ready <= `FALSE; 14.263 + icache_refill_ready <= #1 `FALSE; 14.264 // Is a cycle in progress? 14.265 if (i_cyc_o == `TRUE) 14.266 begin 14.267 @@ -656,10 +706,10 @@ 14.268 `ifdef CFG_HW_DEBUG_ENABLED 14.269 if (jtag_access == `TRUE) 14.270 begin 14.271 - i_cyc_o <= `FALSE; 14.272 - i_stb_o <= `FALSE; 14.273 - i_we_o <= `FALSE; 14.274 - jtag_access <= `FALSE; 14.275 + i_cyc_o <= #1 `FALSE; 14.276 + i_stb_o <= #1 `FALSE; 14.277 + i_we_o <= #1 `FALSE; 14.278 + jtag_access <= #1 `FALSE; 14.279 end 14.280 else 14.281 `endif 14.282 @@ -667,22 +717,22 @@ 14.283 if (last_word == `TRUE) 14.284 begin 14.285 // Cache line fill complete 14.286 - i_cyc_o <= `FALSE; 14.287 - i_stb_o <= `FALSE; 14.288 - i_lock_o <= `FALSE; 14.289 + i_cyc_o <= #1 `FALSE; 14.290 + i_stb_o <= #1 `FALSE; 14.291 + i_lock_o <= #1 `FALSE; 14.292 end 14.293 // Fetch next word in cache line 14.294 - i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 14.295 - i_cti_o <= next_cycle_type; 14.296 + i_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 14.297 + i_cti_o <= #1 next_cycle_type; 14.298 // Write fetched data into instruction cache 14.299 - icache_refill_ready <= `TRUE; 14.300 - icache_refill_data <= i_dat_i; 14.301 + icache_refill_ready <= #1 `TRUE; 14.302 + icache_refill_data <= #1 i_dat_i; 14.303 end 14.304 end 14.305 `ifdef CFG_BUS_ERRORS_ENABLED 14.306 if (i_err_i == `TRUE) 14.307 begin 14.308 - bus_error_f <= `TRUE; 14.309 + bus_error_f <= #1 `TRUE; 14.310 $display ("Instruction bus error. Address: %x", i_adr_o); 14.311 end 14.312 `endif 14.313 @@ -693,15 +743,15 @@ 14.314 begin 14.315 // Read first word of cache line 14.316 `ifdef CFG_HW_DEBUG_ENABLED 14.317 - i_sel_o <= 4'b1111; 14.318 + i_sel_o <= #1 4'b1111; 14.319 `endif 14.320 - i_adr_o <= {first_address, 2'b00}; 14.321 - i_cyc_o <= `TRUE; 14.322 - i_stb_o <= `TRUE; 14.323 - i_cti_o <= first_cycle_type; 14.324 - //i_lock_o <= `TRUE; 14.325 + i_adr_o <= #1 {first_address, 2'b00}; 14.326 + i_cyc_o <= #1 `TRUE; 14.327 + i_stb_o <= #1 `TRUE; 14.328 + i_cti_o <= #1 first_cycle_type; 14.329 + //i_lock_o <= #1 `TRUE; 14.330 `ifdef CFG_BUS_ERRORS_ENABLED 14.331 - bus_error_f <= `FALSE; 14.332 + bus_error_f <= #1 `FALSE; 14.333 `endif 14.334 end 14.335 `ifdef CFG_HW_DEBUG_ENABLED 14.336 @@ -710,18 +760,18 @@ 14.337 if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE)) 14.338 begin 14.339 case (jtag_address[1:0]) 14.340 - 2'b00: i_sel_o <= 4'b1000; 14.341 - 2'b01: i_sel_o <= 4'b0100; 14.342 - 2'b10: i_sel_o <= 4'b0010; 14.343 - 2'b11: i_sel_o <= 4'b0001; 14.344 + 2'b00: i_sel_o <= #1 4'b1000; 14.345 + 2'b01: i_sel_o <= #1 4'b0100; 14.346 + 2'b10: i_sel_o <= #1 4'b0010; 14.347 + 2'b11: i_sel_o <= #1 4'b0001; 14.348 endcase 14.349 - i_adr_o <= jtag_address; 14.350 - i_dat_o <= {4{jtag_write_data}}; 14.351 - i_cyc_o <= `TRUE; 14.352 - i_stb_o <= `TRUE; 14.353 - i_we_o <= jtag_write_enable; 14.354 - i_cti_o <= `LM32_CTYPE_END; 14.355 - jtag_access <= `TRUE; 14.356 + i_adr_o <= #1 jtag_address; 14.357 + i_dat_o <= #1 {4{jtag_write_data}}; 14.358 + i_cyc_o <= #1 `TRUE; 14.359 + i_stb_o <= #1 `TRUE; 14.360 + i_we_o <= #1 jtag_write_enable; 14.361 + i_cti_o <= #1 `LM32_CTYPE_END; 14.362 + jtag_access <= #1 `TRUE; 14.363 end 14.364 end 14.365 `endif 14.366 @@ -730,10 +780,10 @@ 14.367 // continually generated if exception handler is cached 14.368 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH 14.369 if (branch_taken_x == `TRUE) 14.370 - bus_error_f <= `FALSE; 14.371 + bus_error_f <= #1 `FALSE; 14.372 `endif 14.373 if (branch_taken_m == `TRUE) 14.374 - bus_error_f <= `FALSE; 14.375 + bus_error_f <= #1 `FALSE; 14.376 `endif 14.377 end 14.378 end 14.379 @@ -743,14 +793,14 @@ 14.380 begin 14.381 if (rst_i == `TRUE) 14.382 begin 14.383 - i_cyc_o <= `FALSE; 14.384 - i_stb_o <= `FALSE; 14.385 - i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 14.386 - i_cti_o <= `LM32_CTYPE_END; 14.387 - i_lock_o <= `FALSE; 14.388 - wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.389 + i_cyc_o <= #1 `FALSE; 14.390 + i_stb_o <= #1 `FALSE; 14.391 + i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 14.392 + i_cti_o <= #1 `LM32_CTYPE_END; 14.393 + i_lock_o <= #1 `FALSE; 14.394 + wb_data_f <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.395 `ifdef CFG_BUS_ERRORS_ENABLED 14.396 - bus_error_f <= `FALSE; 14.397 + bus_error_f <= #1 `FALSE; 14.398 `endif 14.399 end 14.400 else 14.401 @@ -762,15 +812,15 @@ 14.402 if((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 14.403 begin 14.404 // Cycle complete 14.405 - i_cyc_o <= `FALSE; 14.406 - i_stb_o <= `FALSE; 14.407 + i_cyc_o <= #1 `FALSE; 14.408 + i_stb_o <= #1 `FALSE; 14.409 // Register fetched instruction 14.410 - wb_data_f <= i_dat_i; 14.411 + wb_data_f <= #1 i_dat_i; 14.412 end 14.413 `ifdef CFG_BUS_ERRORS_ENABLED 14.414 if (i_err_i == `TRUE) 14.415 begin 14.416 - bus_error_f <= `TRUE; 14.417 + bus_error_f <= #1 `TRUE; 14.418 $display ("Instruction bus error. Address: %x", i_adr_o); 14.419 end 14.420 `endif 14.421 @@ -786,13 +836,13 @@ 14.422 begin 14.423 // Fetch instruction 14.424 `ifdef CFG_HW_DEBUG_ENABLED 14.425 - i_sel_o <= 4'b1111; 14.426 + i_sel_o <= #1 4'b1111; 14.427 `endif 14.428 - i_adr_o <= {pc_a, 2'b00}; 14.429 - i_cyc_o <= `TRUE; 14.430 - i_stb_o <= `TRUE; 14.431 + i_adr_o <= #1 {pc_a, 2'b00}; 14.432 + i_cyc_o <= #1 `TRUE; 14.433 + i_stb_o <= #1 `TRUE; 14.434 `ifdef CFG_BUS_ERRORS_ENABLED 14.435 - bus_error_f <= `FALSE; 14.436 + bus_error_f <= #1 `FALSE; 14.437 `endif 14.438 end 14.439 else 14.440 @@ -804,7 +854,7 @@ 14.441 ) 14.442 begin 14.443 `ifdef CFG_BUS_ERRORS_ENABLED 14.444 - bus_error_f <= `FALSE; 14.445 + bus_error_f <= #1 `FALSE; 14.446 `endif 14.447 end 14.448 end 14.449 @@ -819,18 +869,18 @@ 14.450 begin 14.451 if (rst_i == `TRUE) 14.452 begin 14.453 - instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.454 + instruction_d <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.455 `ifdef CFG_BUS_ERRORS_ENABLED 14.456 - bus_error_d <= `FALSE; 14.457 + bus_error_d <= #1 `FALSE; 14.458 `endif 14.459 end 14.460 else 14.461 begin 14.462 if (stall_d == `FALSE) 14.463 begin 14.464 - instruction_d <= instruction_f; 14.465 + instruction_d <= #1 instruction_f; 14.466 `ifdef CFG_BUS_ERRORS_ENABLED 14.467 - bus_error_d <= bus_error_f; 14.468 + bus_error_d <= #1 bus_error_f; 14.469 `endif 14.470 end 14.471 end
15.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_interrupt.v 15.2 --- a/lm32_interrupt.v Sun Mar 06 21:14:43 2011 +0000 15.3 +++ b/lm32_interrupt.v Sat Aug 06 00:02:46 2011 +0100 15.4 @@ -1,18 +1,39 @@ 15.5 -// ============================================================================= 15.6 -// COPYRIGHT NOTICE 15.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 15.8 -// ALL RIGHTS RESERVED 15.9 -// This confidential and proprietary software may be used only as authorised by 15.10 -// a licensing agreement from Lattice Semiconductor Corporation. 15.11 -// The entire notice above must be reproduced on all authorized copies and 15.12 -// copies may only be made to the extent permitted by a licensing agreement from 15.13 -// Lattice Semiconductor Corporation. 15.14 +// ================================================================== 15.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 15.16 +// ------------------------------------------------------------------ 15.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 15.18 +// ALL RIGHTS RESERVED 15.19 +// ------------------------------------------------------------------ 15.20 +// 15.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 15.22 +// 15.23 +// Permission: 15.24 +// 15.25 +// Lattice Semiconductor grants permission to use this code 15.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 15.27 +// Open Source License Agreement. 15.28 +// 15.29 +// Disclaimer: 15.30 // 15.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 15.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 15.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 15.34 -// U.S.A email: techsupport@latticesemi.com 15.35 -// =============================================================================/ 15.36 +// Lattice Semiconductor provides no warranty regarding the use or 15.37 +// functionality of this code. It is the user's responsibility to 15.38 +// verify the user’s design for consistency and functionality through 15.39 +// the use of formal verification methods. 15.40 +// 15.41 +// -------------------------------------------------------------------- 15.42 +// 15.43 +// Lattice Semiconductor Corporation 15.44 +// 5555 NE Moore Court 15.45 +// Hillsboro, OR 97214 15.46 +// U.S.A 15.47 +// 15.48 +// TEL: 1-800-Lattice (USA and Canada) 15.49 +// 503-286-8001 (other locations) 15.50 +// 15.51 +// web: http://www.latticesemi.com/ 15.52 +// email: techsupport@latticesemi.com 15.53 +// 15.54 +// -------------------------------------------------------------------- 15.55 // FILE DETAILS 15.56 // Project : LatticeMico32 15.57 // File : lm32_interrupt.v 15.58 @@ -199,64 +220,64 @@ 15.59 begin 15.60 if (rst_i == `TRUE) 15.61 begin 15.62 - ie <= `FALSE; 15.63 - eie <= `FALSE; 15.64 + ie <= #1 `FALSE; 15.65 + eie <= #1 `FALSE; 15.66 `ifdef CFG_DEBUG_ENABLED 15.67 - bie <= `FALSE; 15.68 + bie <= #1 `FALSE; 15.69 `endif 15.70 - im <= {interrupts{1'b0}}; 15.71 - ip <= {interrupts{1'b0}}; 15.72 + im <= #1 {interrupts{1'b0}}; 15.73 + ip <= #1 {interrupts{1'b0}}; 15.74 end 15.75 else 15.76 begin 15.77 // Set IP bit when interrupt line is asserted 15.78 - ip <= asserted; 15.79 + ip <= #1 asserted; 15.80 `ifdef CFG_DEBUG_ENABLED 15.81 if (non_debug_exception == `TRUE) 15.82 begin 15.83 // Save and then clear interrupt enable 15.84 - eie <= ie; 15.85 - ie <= `FALSE; 15.86 + eie <= #1 ie; 15.87 + ie <= #1 `FALSE; 15.88 end 15.89 else if (debug_exception == `TRUE) 15.90 begin 15.91 // Save and then clear interrupt enable 15.92 - bie <= ie; 15.93 - ie <= `FALSE; 15.94 + bie <= #1 ie; 15.95 + ie <= #1 `FALSE; 15.96 end 15.97 `else 15.98 if (exception == `TRUE) 15.99 begin 15.100 // Save and then clear interrupt enable 15.101 - eie <= ie; 15.102 - ie <= `FALSE; 15.103 + eie <= #1 ie; 15.104 + ie <= #1 `FALSE; 15.105 end 15.106 `endif 15.107 else if (stall_x == `FALSE) 15.108 begin 15.109 if (eret_q_x == `TRUE) 15.110 // Restore interrupt enable 15.111 - ie <= eie; 15.112 + ie <= #1 eie; 15.113 `ifdef CFG_DEBUG_ENABLED 15.114 else if (bret_q_x == `TRUE) 15.115 // Restore interrupt enable 15.116 - ie <= bie; 15.117 + ie <= #1 bie; 15.118 `endif 15.119 else if (csr_write_enable == `TRUE) 15.120 begin 15.121 // Handle wcsr write 15.122 if (csr == `LM32_CSR_IE) 15.123 begin 15.124 - ie <= csr_write_data[0]; 15.125 - eie <= csr_write_data[1]; 15.126 + ie <= #1 csr_write_data[0]; 15.127 + eie <= #1 csr_write_data[1]; 15.128 `ifdef CFG_DEBUG_ENABLED 15.129 - bie <= csr_write_data[2]; 15.130 + bie <= #1 csr_write_data[2]; 15.131 `endif 15.132 end 15.133 if (csr == `LM32_CSR_IM) 15.134 - im <= csr_write_data[interrupts-1:0]; 15.135 + im <= #1 csr_write_data[interrupts-1:0]; 15.136 if (csr == `LM32_CSR_IP) 15.137 - ip <= asserted & ~csr_write_data[interrupts-1:0]; 15.138 + ip <= #1 asserted & ~csr_write_data[interrupts-1:0]; 15.139 end 15.140 end 15.141 end 15.142 @@ -269,61 +290,61 @@ 15.143 begin 15.144 if (rst_i == `TRUE) 15.145 begin 15.146 - ie <= `FALSE; 15.147 - eie <= `FALSE; 15.148 + ie <= #1 `FALSE; 15.149 + eie <= #1 `FALSE; 15.150 `ifdef CFG_DEBUG_ENABLED 15.151 - bie <= `FALSE; 15.152 + bie <= #1 `FALSE; 15.153 `endif 15.154 - ip <= {interrupts{1'b0}}; 15.155 + ip <= #1 {interrupts{1'b0}}; 15.156 end 15.157 else 15.158 begin 15.159 // Set IP bit when interrupt line is asserted 15.160 - ip <= asserted; 15.161 + ip <= #1 asserted; 15.162 `ifdef CFG_DEBUG_ENABLED 15.163 if (non_debug_exception == `TRUE) 15.164 begin 15.165 // Save and then clear interrupt enable 15.166 - eie <= ie; 15.167 - ie <= `FALSE; 15.168 + eie <= #1 ie; 15.169 + ie <= #1 `FALSE; 15.170 end 15.171 else if (debug_exception == `TRUE) 15.172 begin 15.173 // Save and then clear interrupt enable 15.174 - bie <= ie; 15.175 - ie <= `FALSE; 15.176 + bie <= #1 ie; 15.177 + ie <= #1 `FALSE; 15.178 end 15.179 `else 15.180 if (exception == `TRUE) 15.181 begin 15.182 // Save and then clear interrupt enable 15.183 - eie <= ie; 15.184 - ie <= `FALSE; 15.185 + eie <= #1 ie; 15.186 + ie <= #1 `FALSE; 15.187 end 15.188 `endif 15.189 else if (stall_x == `FALSE) 15.190 begin 15.191 if (eret_q_x == `TRUE) 15.192 // Restore interrupt enable 15.193 - ie <= eie; 15.194 + ie <= #1 eie; 15.195 `ifdef CFG_DEBUG_ENABLED 15.196 else if (bret_q_x == `TRUE) 15.197 // Restore interrupt enable 15.198 - ie <= bie; 15.199 + ie <= #1 bie; 15.200 `endif 15.201 else if (csr_write_enable == `TRUE) 15.202 begin 15.203 // Handle wcsr write 15.204 if (csr == `LM32_CSR_IE) 15.205 begin 15.206 - ie <= csr_write_data[0]; 15.207 - eie <= csr_write_data[1]; 15.208 + ie <= #1 csr_write_data[0]; 15.209 + eie <= #1 csr_write_data[1]; 15.210 `ifdef CFG_DEBUG_ENABLED 15.211 - bie <= csr_write_data[2]; 15.212 + bie <= #1 csr_write_data[2]; 15.213 `endif 15.214 end 15.215 if (csr == `LM32_CSR_IP) 15.216 - ip <= asserted & ~csr_write_data[interrupts-1:0]; 15.217 + ip <= #1 asserted & ~csr_write_data[interrupts-1:0]; 15.218 end 15.219 end 15.220 end
16.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_jtag.v 16.2 --- a/lm32_jtag.v Sun Mar 06 21:14:43 2011 +0000 16.3 +++ b/lm32_jtag.v Sat Aug 06 00:02:46 2011 +0100 16.4 @@ -1,18 +1,39 @@ 16.5 -// ============================================================================= 16.6 -// COPYRIGHT NOTICE 16.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 16.8 -// ALL RIGHTS RESERVED 16.9 -// This confidential and proprietary software may be used only as authorised by 16.10 -// a licensing agreement from Lattice Semiconductor Corporation. 16.11 -// The entire notice above must be reproduced on all authorized copies and 16.12 -// copies may only be made to the extent permitted by a licensing agreement from 16.13 -// Lattice Semiconductor Corporation. 16.14 +// ================================================================== 16.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 16.16 +// ------------------------------------------------------------------ 16.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 16.18 +// ALL RIGHTS RESERVED 16.19 +// ------------------------------------------------------------------ 16.20 +// 16.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 16.22 +// 16.23 +// Permission: 16.24 +// 16.25 +// Lattice Semiconductor grants permission to use this code 16.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 16.27 +// Open Source License Agreement. 16.28 +// 16.29 +// Disclaimer: 16.30 // 16.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 16.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 16.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 16.34 -// U.S.A email: techsupport@latticesemi.com 16.35 -// =============================================================================/ 16.36 +// Lattice Semiconductor provides no warranty regarding the use or 16.37 +// functionality of this code. It is the user's responsibility to 16.38 +// verify the user’s design for consistency and functionality through 16.39 +// the use of formal verification methods. 16.40 +// 16.41 +// -------------------------------------------------------------------- 16.42 +// 16.43 +// Lattice Semiconductor Corporation 16.44 +// 5555 NE Moore Court 16.45 +// Hillsboro, OR 97214 16.46 +// U.S.A 16.47 +// 16.48 +// TEL: 1-800-Lattice (USA and Canada) 16.49 +// 503-286-8001 (other locations) 16.50 +// 16.51 +// web: http://www.latticesemi.com/ 16.52 +// email: techsupport@latticesemi.com 16.53 +// 16.54 +// -------------------------------------------------------------------- 16.55 // FILE DETAILS 16.56 // Project : LatticeMico32 16.57 // File : lm32_jtag.v 16.58 @@ -236,9 +257,9 @@ 16.59 always @(negedge jtag_update `CFG_RESET_SENSITIVITY) 16.60 begin 16.61 if (rst_i == `TRUE) 16.62 - rx_toggle <= 1'b0; 16.63 + rx_toggle <= #1 1'b0; 16.64 else 16.65 - rx_toggle <= ~rx_toggle; 16.66 + rx_toggle <= #1 ~rx_toggle; 16.67 end 16.68 16.69 always @(*) 16.70 @@ -252,15 +273,15 @@ 16.71 begin 16.72 if (rst_i == `TRUE) 16.73 begin 16.74 - rx_toggle_r <= 1'b0; 16.75 - rx_toggle_r_r <= 1'b0; 16.76 - rx_toggle_r_r_r <= 1'b0; 16.77 + rx_toggle_r <= #1 1'b0; 16.78 + rx_toggle_r_r <= #1 1'b0; 16.79 + rx_toggle_r_r_r <= #1 1'b0; 16.80 end 16.81 else 16.82 begin 16.83 - rx_toggle_r <= rx_toggle; 16.84 - rx_toggle_r_r <= rx_toggle_r; 16.85 - rx_toggle_r_r_r <= rx_toggle_r_r; 16.86 + rx_toggle_r <= #1 rx_toggle; 16.87 + rx_toggle_r_r <= #1 rx_toggle_r; 16.88 + rx_toggle_r_r_r <= #1 rx_toggle_r_r; 16.89 end 16.90 end 16.91 16.92 @@ -269,24 +290,24 @@ 16.93 begin 16.94 if (rst_i == `TRUE) 16.95 begin 16.96 - state <= `LM32_JTAG_STATE_READ_COMMAND; 16.97 - command <= 4'b0000; 16.98 - jtag_reg_d <= 8'h00; 16.99 + state <= #1 `LM32_JTAG_STATE_READ_COMMAND; 16.100 + command <= #1 4'b0000; 16.101 + jtag_reg_d <= #1 8'h00; 16.102 `ifdef CFG_HW_DEBUG_ENABLED 16.103 - processing <= `FALSE; 16.104 - jtag_csr_write_enable <= `FALSE; 16.105 - jtag_read_enable <= `FALSE; 16.106 - jtag_write_enable <= `FALSE; 16.107 + processing <= #1 `FALSE; 16.108 + jtag_csr_write_enable <= #1 `FALSE; 16.109 + jtag_read_enable <= #1 `FALSE; 16.110 + jtag_write_enable <= #1 `FALSE; 16.111 `endif 16.112 `ifdef CFG_DEBUG_ENABLED 16.113 - jtag_break <= `FALSE; 16.114 - jtag_reset <= `FALSE; 16.115 + jtag_break <= #1 `FALSE; 16.116 + jtag_reset <= #1 `FALSE; 16.117 `endif 16.118 `ifdef CFG_JTAG_UART_ENABLED 16.119 - uart_tx_byte <= 8'h00; 16.120 - uart_tx_valid <= `FALSE; 16.121 - uart_rx_byte <= 8'h00; 16.122 - uart_rx_valid <= `FALSE; 16.123 + uart_tx_byte <= #1 8'h00; 16.124 + uart_tx_valid <= #1 `FALSE; 16.125 + uart_rx_byte <= #1 8'h00; 16.126 + uart_rx_valid <= #1 `FALSE; 16.127 `endif 16.128 end 16.129 else 16.130 @@ -298,13 +319,13 @@ 16.131 `LM32_CSR_JTX: 16.132 begin 16.133 // Set flag indicating data is available 16.134 - uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG]; 16.135 - uart_tx_valid <= `TRUE; 16.136 + uart_tx_byte <= #1 csr_write_data[`LM32_BYTE_0_RNG]; 16.137 + uart_tx_valid <= #1 `TRUE; 16.138 end 16.139 `LM32_CSR_JRX: 16.140 begin 16.141 // Clear flag indidicating data has been received 16.142 - uart_rx_valid <= `FALSE; 16.143 + uart_rx_valid <= #1 `FALSE; 16.144 end 16.145 endcase 16.146 end 16.147 @@ -313,8 +334,8 @@ 16.148 // When an exception has occured, clear the requests 16.149 if (exception_q_w == `TRUE) 16.150 begin 16.151 - jtag_break <= `FALSE; 16.152 - jtag_reset <= `FALSE; 16.153 + jtag_break <= #1 `FALSE; 16.154 + jtag_reset <= #1 `FALSE; 16.155 end 16.156 `endif 16.157 case (state) 16.158 @@ -323,7 +344,7 @@ 16.159 // Wait for rx register to toggle which indicates new data is available 16.160 if (rx_toggle_r_r != rx_toggle_r_r_r) 16.161 begin 16.162 - command <= rx_byte[7:4]; 16.163 + command <= #1 rx_byte[7:4]; 16.164 case (rx_addr) 16.165 `ifdef CFG_DEBUG_ENABLED 16.166 `LM32_DP: 16.167 @@ -331,37 +352,37 @@ 16.168 case (rx_byte[7:4]) 16.169 `ifdef CFG_HW_DEBUG_ENABLED 16.170 `LM32_DP_READ_MEMORY: 16.171 - state <= `LM32_JTAG_STATE_READ_BYTE_0; 16.172 + state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; 16.173 `LM32_DP_READ_SEQUENTIAL: 16.174 begin 16.175 - {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 16.176 - state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 16.177 + {jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1; 16.178 + state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; 16.179 end 16.180 `LM32_DP_WRITE_MEMORY: 16.181 - state <= `LM32_JTAG_STATE_READ_BYTE_0; 16.182 + state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; 16.183 `LM32_DP_WRITE_SEQUENTIAL: 16.184 begin 16.185 - {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 16.186 - state <= 5; 16.187 + {jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1; 16.188 + state <= #1 5; 16.189 end 16.190 `LM32_DP_WRITE_CSR: 16.191 - state <= `LM32_JTAG_STATE_READ_BYTE_0; 16.192 + state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; 16.193 `endif 16.194 `LM32_DP_BREAK: 16.195 begin 16.196 `ifdef CFG_JTAG_UART_ENABLED 16.197 - uart_rx_valid <= `FALSE; 16.198 - uart_tx_valid <= `FALSE; 16.199 + uart_rx_valid <= #1 `FALSE; 16.200 + uart_tx_valid <= #1 `FALSE; 16.201 `endif 16.202 - jtag_break <= `TRUE; 16.203 + jtag_break <= #1 `TRUE; 16.204 end 16.205 `LM32_DP_RESET: 16.206 begin 16.207 `ifdef CFG_JTAG_UART_ENABLED 16.208 - uart_rx_valid <= `FALSE; 16.209 - uart_tx_valid <= `FALSE; 16.210 + uart_rx_valid <= #1 `FALSE; 16.211 + uart_tx_valid <= #1 `FALSE; 16.212 `endif 16.213 - jtag_reset <= `TRUE; 16.214 + jtag_reset <= #1 `TRUE; 16.215 end 16.216 endcase 16.217 end 16.218 @@ -369,13 +390,13 @@ 16.219 `ifdef CFG_JTAG_UART_ENABLED 16.220 `LM32_TX: 16.221 begin 16.222 - uart_rx_byte <= rx_byte; 16.223 - uart_rx_valid <= `TRUE; 16.224 + uart_rx_byte <= #1 rx_byte; 16.225 + uart_rx_valid <= #1 `TRUE; 16.226 end 16.227 `LM32_RX: 16.228 begin 16.229 - jtag_reg_d <= uart_tx_byte; 16.230 - uart_tx_valid <= `FALSE; 16.231 + jtag_reg_d <= #1 uart_tx_byte; 16.232 + uart_tx_valid <= #1 `FALSE; 16.233 end 16.234 `endif 16.235 default: 16.236 @@ -388,43 +409,43 @@ 16.237 begin 16.238 if (rx_toggle_r_r != rx_toggle_r_r_r) 16.239 begin 16.240 - jtag_byte_0 <= rx_byte; 16.241 - state <= `LM32_JTAG_STATE_READ_BYTE_1; 16.242 + jtag_byte_0 <= #1 rx_byte; 16.243 + state <= #1 `LM32_JTAG_STATE_READ_BYTE_1; 16.244 end 16.245 end 16.246 `LM32_JTAG_STATE_READ_BYTE_1: 16.247 begin 16.248 if (rx_toggle_r_r != rx_toggle_r_r_r) 16.249 begin 16.250 - jtag_byte_1 <= rx_byte; 16.251 - state <= `LM32_JTAG_STATE_READ_BYTE_2; 16.252 + jtag_byte_1 <= #1 rx_byte; 16.253 + state <= #1 `LM32_JTAG_STATE_READ_BYTE_2; 16.254 end 16.255 end 16.256 `LM32_JTAG_STATE_READ_BYTE_2: 16.257 begin 16.258 if (rx_toggle_r_r != rx_toggle_r_r_r) 16.259 begin 16.260 - jtag_byte_2 <= rx_byte; 16.261 - state <= `LM32_JTAG_STATE_READ_BYTE_3; 16.262 + jtag_byte_2 <= #1 rx_byte; 16.263 + state <= #1 `LM32_JTAG_STATE_READ_BYTE_3; 16.264 end 16.265 end 16.266 `LM32_JTAG_STATE_READ_BYTE_3: 16.267 begin 16.268 if (rx_toggle_r_r != rx_toggle_r_r_r) 16.269 begin 16.270 - jtag_byte_3 <= rx_byte; 16.271 + jtag_byte_3 <= #1 rx_byte; 16.272 if (command == `LM32_DP_READ_MEMORY) 16.273 - state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 16.274 + state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; 16.275 else 16.276 - state <= `LM32_JTAG_STATE_READ_BYTE_4; 16.277 + state <= #1 `LM32_JTAG_STATE_READ_BYTE_4; 16.278 end 16.279 end 16.280 `LM32_JTAG_STATE_READ_BYTE_4: 16.281 begin 16.282 if (rx_toggle_r_r != rx_toggle_r_r_r) 16.283 begin 16.284 - jtag_byte_4 <= rx_byte; 16.285 - state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 16.286 + jtag_byte_4 <= #1 rx_byte; 16.287 + state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; 16.288 end 16.289 end 16.290 `LM32_JTAG_STATE_PROCESS_COMMAND: 16.291 @@ -433,22 +454,22 @@ 16.292 `LM32_DP_READ_MEMORY, 16.293 `LM32_DP_READ_SEQUENTIAL: 16.294 begin 16.295 - jtag_read_enable <= `TRUE; 16.296 - processing <= `TRUE; 16.297 - state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 16.298 + jtag_read_enable <= #1 `TRUE; 16.299 + processing <= #1 `TRUE; 16.300 + state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 16.301 end 16.302 `LM32_DP_WRITE_MEMORY, 16.303 `LM32_DP_WRITE_SEQUENTIAL: 16.304 begin 16.305 - jtag_write_enable <= `TRUE; 16.306 - processing <= `TRUE; 16.307 - state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 16.308 + jtag_write_enable <= #1 `TRUE; 16.309 + processing <= #1 `TRUE; 16.310 + state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 16.311 end 16.312 `LM32_DP_WRITE_CSR: 16.313 begin 16.314 - jtag_csr_write_enable <= `TRUE; 16.315 - processing <= `TRUE; 16.316 - state <= `LM32_JTAG_STATE_WAIT_FOR_CSR; 16.317 + jtag_csr_write_enable <= #1 `TRUE; 16.318 + processing <= #1 `TRUE; 16.319 + state <= #1 `LM32_JTAG_STATE_WAIT_FOR_CSR; 16.320 end 16.321 endcase 16.322 end 16.323 @@ -456,18 +477,18 @@ 16.324 begin 16.325 if (jtag_access_complete == `TRUE) 16.326 begin 16.327 - jtag_read_enable <= `FALSE; 16.328 - jtag_reg_d <= jtag_read_data; 16.329 - jtag_write_enable <= `FALSE; 16.330 - processing <= `FALSE; 16.331 - state <= `LM32_JTAG_STATE_READ_COMMAND; 16.332 + jtag_read_enable <= #1 `FALSE; 16.333 + jtag_reg_d <= #1 jtag_read_data; 16.334 + jtag_write_enable <= #1 `FALSE; 16.335 + processing <= #1 `FALSE; 16.336 + state <= #1 `LM32_JTAG_STATE_READ_COMMAND; 16.337 end 16.338 end 16.339 `LM32_JTAG_STATE_WAIT_FOR_CSR: 16.340 begin 16.341 - jtag_csr_write_enable <= `FALSE; 16.342 - processing <= `FALSE; 16.343 - state <= `LM32_JTAG_STATE_READ_COMMAND; 16.344 + jtag_csr_write_enable <= #1 `FALSE; 16.345 + processing <= #1 `FALSE; 16.346 + state <= #1 `LM32_JTAG_STATE_READ_COMMAND; 16.347 end 16.348 `endif 16.349 endcase
17.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_load_store_unit.v 17.2 --- a/lm32_load_store_unit.v Sun Mar 06 21:14:43 2011 +0000 17.3 +++ b/lm32_load_store_unit.v Sat Aug 06 00:02:46 2011 +0100 17.4 @@ -1,18 +1,39 @@ 17.5 -// ============================================================================= 17.6 -// COPYRIGHT NOTICE 17.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 17.8 -// ALL RIGHTS RESERVED 17.9 -// This confidential and proprietary software may be used only as authorised by 17.10 -// a licensing agreement from Lattice Semiconductor Corporation. 17.11 -// The entire notice above must be reproduced on all authorized copies and 17.12 -// copies may only be made to the extent permitted by a licensing agreement from 17.13 -// Lattice Semiconductor Corporation. 17.14 +// ================================================================== 17.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 17.16 +// ------------------------------------------------------------------ 17.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 17.18 +// ALL RIGHTS RESERVED 17.19 +// ------------------------------------------------------------------ 17.20 +// 17.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 17.22 +// 17.23 +// Permission: 17.24 +// 17.25 +// Lattice Semiconductor grants permission to use this code 17.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 17.27 +// Open Source License Agreement. 17.28 +// 17.29 +// Disclaimer: 17.30 // 17.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 17.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 17.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 17.34 -// U.S.A email: techsupport@latticesemi.com 17.35 -// =============================================================================/ 17.36 +// Lattice Semiconductor provides no warranty regarding the use or 17.37 +// functionality of this code. It is the user's responsibility to 17.38 +// verify the user’s design for consistency and functionality through 17.39 +// the use of formal verification methods. 17.40 +// 17.41 +// -------------------------------------------------------------------- 17.42 +// 17.43 +// Lattice Semiconductor Corporation 17.44 +// 5555 NE Moore Court 17.45 +// Hillsboro, OR 97214 17.46 +// U.S.A 17.47 +// 17.48 +// TEL: 1-800-Lattice (USA and Canada) 17.49 +// 503-286-8001 (other locations) 17.50 +// 17.51 +// web: http://www.latticesemi.com/ 17.52 +// email: techsupport@latticesemi.com 17.53 +// 17.54 +// -------------------------------------------------------------------- 17.55 // FILE DETAILS 17.56 // Project : LatticeMico32 17.57 // File : lm32_load_store_unit.v 17.58 @@ -302,8 +323,8 @@ 17.59 .ResetB (rst_i), 17.60 .DataInA ({32{1'b0}}), 17.61 .DataInB (dram_store_data_m), 17.62 - .AddressA (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]), 17.63 - .AddressB (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]), 17.64 + .AddressA (load_store_address_x[clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]), 17.65 + .AddressB (load_store_address_m[clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]), 17.66 // .ClockEnA (!stall_x & (load_x | store_x)), 17.67 .ClockEnA (!stall_x), 17.68 .ClockEnB (!stall_m), 17.69 @@ -322,13 +343,13 @@ 17.70 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 17.71 if (rst_i == `TRUE) 17.72 begin 17.73 - dram_bypass_en <= `FALSE; 17.74 - dram_bypass_data <= 0; 17.75 + dram_bypass_en <= #1 `FALSE; 17.76 + dram_bypass_data <= #1 0; 17.77 end 17.78 else 17.79 begin 17.80 if (stall_x == `FALSE) 17.81 - dram_bypass_data <= dram_store_data_m; 17.82 + dram_bypass_data <= #1 dram_store_data_m; 17.83 17.84 if ( (stall_m == `FALSE) 17.85 && (stall_x == `FALSE) 17.86 @@ -338,12 +359,12 @@ 17.87 ) 17.88 && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2]) 17.89 ) 17.90 - dram_bypass_en <= `TRUE; 17.91 + dram_bypass_en <= #1 `TRUE; 17.92 else 17.93 if ( (dram_bypass_en == `TRUE) 17.94 && (stall_x == `FALSE) 17.95 ) 17.96 - dram_bypass_en <= `FALSE; 17.97 + dram_bypass_en <= #1 `FALSE; 17.98 end 17.99 17.100 assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out; 17.101 @@ -603,26 +624,26 @@ 17.102 begin 17.103 if (rst_i == `TRUE) 17.104 begin 17.105 - d_cyc_o <= `FALSE; 17.106 - d_stb_o <= `FALSE; 17.107 - d_dat_o <= {`LM32_WORD_WIDTH{1'b0}}; 17.108 - d_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 17.109 - d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}}; 17.110 - d_we_o <= `FALSE; 17.111 - d_cti_o <= `LM32_CTYPE_END; 17.112 - d_lock_o <= `FALSE; 17.113 - wb_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 17.114 - wb_load_complete <= `FALSE; 17.115 - stall_wb_load <= `FALSE; 17.116 + d_cyc_o <= #1 `FALSE; 17.117 + d_stb_o <= #1 `FALSE; 17.118 + d_dat_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 17.119 + d_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 17.120 + d_sel_o <= #1 {`LM32_BYTE_SELECT_WIDTH{`FALSE}}; 17.121 + d_we_o <= #1 `FALSE; 17.122 + d_cti_o <= #1 `LM32_CTYPE_END; 17.123 + d_lock_o <= #1 `FALSE; 17.124 + wb_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 17.125 + wb_load_complete <= #1 `FALSE; 17.126 + stall_wb_load <= #1 `FALSE; 17.127 `ifdef CFG_DCACHE_ENABLED 17.128 - dcache_refill_ready <= `FALSE; 17.129 + dcache_refill_ready <= #1 `FALSE; 17.130 `endif 17.131 end 17.132 else 17.133 begin 17.134 `ifdef CFG_DCACHE_ENABLED 17.135 // Refill ready should only be asserted for a single cycle 17.136 - dcache_refill_ready <= `FALSE; 17.137 + dcache_refill_ready <= #1 `FALSE; 17.138 `endif 17.139 // Is a Wishbone cycle already in progress? 17.140 if (d_cyc_o == `TRUE) 17.141 @@ -634,25 +655,25 @@ 17.142 if ((dcache_refilling == `TRUE) && (!last_word)) 17.143 begin 17.144 // Fetch next word of cache line 17.145 - d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 17.146 + d_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 17.147 end 17.148 else 17.149 `endif 17.150 begin 17.151 // Refill/access complete 17.152 - d_cyc_o <= `FALSE; 17.153 - d_stb_o <= `FALSE; 17.154 - d_lock_o <= `FALSE; 17.155 + d_cyc_o <= #1 `FALSE; 17.156 + d_stb_o <= #1 `FALSE; 17.157 + d_lock_o <= #1 `FALSE; 17.158 end 17.159 `ifdef CFG_DCACHE_ENABLED 17.160 - d_cti_o <= next_cycle_type; 17.161 + d_cti_o <= #1 next_cycle_type; 17.162 // If we are performing a refill, indicate to cache next word of data is ready 17.163 - dcache_refill_ready <= dcache_refilling; 17.164 + dcache_refill_ready <= #1 dcache_refilling; 17.165 `endif 17.166 // Register data read from Wishbone interface 17.167 - wb_data_m <= d_dat_i; 17.168 + wb_data_m <= #1 d_dat_i; 17.169 // Don't set when stores complete - otherwise we'll deadlock if load in m stage 17.170 - wb_load_complete <= !d_we_o; 17.171 + wb_load_complete <= #1 !d_we_o; 17.172 end 17.173 // synthesis translate_off 17.174 if (d_err_i == `TRUE) 17.175 @@ -665,13 +686,13 @@ 17.176 if (dcache_refill_request == `TRUE) 17.177 begin 17.178 // Start cache refill 17.179 - d_adr_o <= first_address; 17.180 - d_cyc_o <= `TRUE; 17.181 - d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}}; 17.182 - d_stb_o <= `TRUE; 17.183 - d_we_o <= `FALSE; 17.184 - d_cti_o <= first_cycle_type; 17.185 - //d_lock_o <= `TRUE; 17.186 + d_adr_o <= #1 first_address; 17.187 + d_cyc_o <= #1 `TRUE; 17.188 + d_sel_o <= #1 {`LM32_WORD_WIDTH/8{`TRUE}}; 17.189 + d_stb_o <= #1 `TRUE; 17.190 + d_we_o <= #1 `FALSE; 17.191 + d_cti_o <= #1 first_cycle_type; 17.192 + //d_lock_o <= #1 `TRUE; 17.193 end 17.194 else 17.195 `endif 17.196 @@ -686,13 +707,13 @@ 17.197 ) 17.198 begin 17.199 // Data cache is write through, so all stores go to memory 17.200 - d_dat_o <= store_data_m; 17.201 - d_adr_o <= load_store_address_m; 17.202 - d_cyc_o <= `TRUE; 17.203 - d_sel_o <= byte_enable_m; 17.204 - d_stb_o <= `TRUE; 17.205 - d_we_o <= `TRUE; 17.206 - d_cti_o <= `LM32_CTYPE_END; 17.207 + d_dat_o <= #1 store_data_m; 17.208 + d_adr_o <= #1 load_store_address_m; 17.209 + d_cyc_o <= #1 `TRUE; 17.210 + d_sel_o <= #1 byte_enable_m; 17.211 + d_stb_o <= #1 `TRUE; 17.212 + d_we_o <= #1 `TRUE; 17.213 + d_cti_o <= #1 `LM32_CTYPE_END; 17.214 end 17.215 else if ( (load_q_m == `TRUE) 17.216 && (wb_select_m == `TRUE) 17.217 @@ -701,24 +722,24 @@ 17.218 ) 17.219 begin 17.220 // Read requested address 17.221 - stall_wb_load <= `FALSE; 17.222 - d_adr_o <= load_store_address_m; 17.223 - d_cyc_o <= `TRUE; 17.224 - d_sel_o <= byte_enable_m; 17.225 - d_stb_o <= `TRUE; 17.226 - d_we_o <= `FALSE; 17.227 - d_cti_o <= `LM32_CTYPE_END; 17.228 + stall_wb_load <= #1 `FALSE; 17.229 + d_adr_o <= #1 load_store_address_m; 17.230 + d_cyc_o <= #1 `TRUE; 17.231 + d_sel_o <= #1 byte_enable_m; 17.232 + d_stb_o <= #1 `TRUE; 17.233 + d_we_o <= #1 `FALSE; 17.234 + d_cti_o <= #1 `LM32_CTYPE_END; 17.235 end 17.236 end 17.237 // Clear load/store complete flag when instruction leaves M stage 17.238 if (stall_m == `FALSE) 17.239 - wb_load_complete <= `FALSE; 17.240 + wb_load_complete <= #1 `FALSE; 17.241 // When a Wishbone load first enters the M stage, we need to stall it 17.242 if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE)) 17.243 - stall_wb_load <= `TRUE; 17.244 + stall_wb_load <= #1 `TRUE; 17.245 // Clear stall request if load instruction is killed 17.246 if ((kill_m == `TRUE) || (exception_m == `TRUE)) 17.247 - stall_wb_load <= `FALSE; 17.248 + stall_wb_load <= #1 `FALSE; 17.249 end 17.250 end 17.251 17.252 @@ -729,39 +750,39 @@ 17.253 begin 17.254 if (rst_i == `TRUE) 17.255 begin 17.256 - sign_extend_m <= `FALSE; 17.257 - size_m <= 2'b00; 17.258 - byte_enable_m <= `FALSE; 17.259 - store_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 17.260 + sign_extend_m <= #1 `FALSE; 17.261 + size_m <= #1 2'b00; 17.262 + byte_enable_m <= #1 `FALSE; 17.263 + store_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 17.264 `ifdef CFG_DCACHE_ENABLED 17.265 - dcache_select_m <= `FALSE; 17.266 + dcache_select_m <= #1 `FALSE; 17.267 `endif 17.268 `ifdef CFG_DRAM_ENABLED 17.269 - dram_select_m <= `FALSE; 17.270 + dram_select_m <= #1 `FALSE; 17.271 `endif 17.272 `ifdef CFG_IROM_ENABLED 17.273 - irom_select_m <= `FALSE; 17.274 + irom_select_m <= #1 `FALSE; 17.275 `endif 17.276 - wb_select_m <= `FALSE; 17.277 + wb_select_m <= #1 `FALSE; 17.278 end 17.279 else 17.280 begin 17.281 if (stall_m == `FALSE) 17.282 begin 17.283 - sign_extend_m <= sign_extend_x; 17.284 - size_m <= size_x; 17.285 - byte_enable_m <= byte_enable_x; 17.286 - store_data_m <= store_data_x; 17.287 + sign_extend_m <= #1 sign_extend_x; 17.288 + size_m <= #1 size_x; 17.289 + byte_enable_m <= #1 byte_enable_x; 17.290 + store_data_m <= #1 store_data_x; 17.291 `ifdef CFG_DCACHE_ENABLED 17.292 - dcache_select_m <= dcache_select_x; 17.293 + dcache_select_m <= #1 dcache_select_x; 17.294 `endif 17.295 `ifdef CFG_DRAM_ENABLED 17.296 - dram_select_m <= dram_select_x; 17.297 + dram_select_m <= #1 dram_select_x; 17.298 `endif 17.299 `ifdef CFG_IROM_ENABLED 17.300 - irom_select_m <= irom_select_x; 17.301 + irom_select_m <= #1 irom_select_x; 17.302 `endif 17.303 - wb_select_m <= wb_select_x; 17.304 + wb_select_m <= #1 wb_select_x; 17.305 end 17.306 end 17.307 end 17.308 @@ -771,15 +792,15 @@ 17.309 begin 17.310 if (rst_i == `TRUE) 17.311 begin 17.312 - size_w <= 2'b00; 17.313 - data_w <= {`LM32_WORD_WIDTH{1'b0}}; 17.314 - sign_extend_w <= `FALSE; 17.315 + size_w <= #1 2'b00; 17.316 + data_w <= #1 {`LM32_WORD_WIDTH{1'b0}}; 17.317 + sign_extend_w <= #1 `FALSE; 17.318 end 17.319 else 17.320 begin 17.321 - size_w <= size_m; 17.322 - data_w <= data_m; 17.323 - sign_extend_w <= sign_extend_m; 17.324 + size_w <= #1 size_m; 17.325 + data_w <= #1 data_m; 17.326 + sign_extend_w <= #1 sign_extend_m; 17.327 end 17.328 end 17.329
18.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_logic_op.v 18.2 --- a/lm32_logic_op.v Sun Mar 06 21:14:43 2011 +0000 18.3 +++ b/lm32_logic_op.v Sat Aug 06 00:02:46 2011 +0100 18.4 @@ -1,18 +1,39 @@ 18.5 -// ============================================================================= 18.6 -// COPYRIGHT NOTICE 18.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 18.8 -// ALL RIGHTS RESERVED 18.9 -// This confidential and proprietary software may be used only as authorised by 18.10 -// a licensing agreement from Lattice Semiconductor Corporation. 18.11 -// The entire notice above must be reproduced on all authorized copies and 18.12 -// copies may only be made to the extent permitted by a licensing agreement from 18.13 -// Lattice Semiconductor Corporation. 18.14 +// ================================================================== 18.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 18.16 +// ------------------------------------------------------------------ 18.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 18.18 +// ALL RIGHTS RESERVED 18.19 +// ------------------------------------------------------------------ 18.20 +// 18.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 18.22 +// 18.23 +// Permission: 18.24 +// 18.25 +// Lattice Semiconductor grants permission to use this code 18.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 18.27 +// Open Source License Agreement. 18.28 +// 18.29 +// Disclaimer: 18.30 // 18.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 18.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 18.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 18.34 -// U.S.A email: techsupport@latticesemi.com 18.35 -// =============================================================================/ 18.36 +// Lattice Semiconductor provides no warranty regarding the use or 18.37 +// functionality of this code. It is the user's responsibility to 18.38 +// verify the user’s design for consistency and functionality through 18.39 +// the use of formal verification methods. 18.40 +// 18.41 +// -------------------------------------------------------------------- 18.42 +// 18.43 +// Lattice Semiconductor Corporation 18.44 +// 5555 NE Moore Court 18.45 +// Hillsboro, OR 97214 18.46 +// U.S.A 18.47 +// 18.48 +// TEL: 1-800-Lattice (USA and Canada) 18.49 +// 503-286-8001 (other locations) 18.50 +// 18.51 +// web: http://www.latticesemi.com/ 18.52 +// email: techsupport@latticesemi.com 18.53 +// 18.54 +// -------------------------------------------------------------------- 18.55 // FILE DETAILS 18.56 // Project : LatticeMico32 18.57 // File : lm32_logic_op.v
19.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_mc_arithmetic.v 19.2 --- a/lm32_mc_arithmetic.v Sun Mar 06 21:14:43 2011 +0000 19.3 +++ b/lm32_mc_arithmetic.v Sat Aug 06 00:02:46 2011 +0100 19.4 @@ -1,18 +1,39 @@ 19.5 -// ============================================================================= 19.6 -// COPYRIGHT NOTICE 19.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 19.8 -// ALL RIGHTS RESERVED 19.9 -// This confidential and proprietary software may be used only as authorised by 19.10 -// a licensing agreement from Lattice Semiconductor Corporation. 19.11 -// The entire notice above must be reproduced on all authorized copies and 19.12 -// copies may only be made to the extent permitted by a licensing agreement from 19.13 -// Lattice Semiconductor Corporation. 19.14 +// ================================================================== 19.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 19.16 +// ------------------------------------------------------------------ 19.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 19.18 +// ALL RIGHTS RESERVED 19.19 +// ------------------------------------------------------------------ 19.20 +// 19.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 19.22 +// 19.23 +// Permission: 19.24 +// 19.25 +// Lattice Semiconductor grants permission to use this code 19.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 19.27 +// Open Source License Agreement. 19.28 +// 19.29 +// Disclaimer: 19.30 // 19.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 19.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 19.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 19.34 -// U.S.A email: techsupport@latticesemi.com 19.35 -// =============================================================================/ 19.36 +// Lattice Semiconductor provides no warranty regarding the use or 19.37 +// functionality of this code. It is the user's responsibility to 19.38 +// verify the user’s design for consistency and functionality through 19.39 +// the use of formal verification methods. 19.40 +// 19.41 +// -------------------------------------------------------------------- 19.42 +// 19.43 +// Lattice Semiconductor Corporation 19.44 +// 5555 NE Moore Court 19.45 +// Hillsboro, OR 97214 19.46 +// U.S.A 19.47 +// 19.48 +// TEL: 1-800-Lattice (USA and Canada) 19.49 +// 503-286-8001 (other locations) 19.50 +// 19.51 +// web: http://www.latticesemi.com/ 19.52 +// email: techsupport@latticesemi.com 19.53 +// 19.54 +// -------------------------------------------------------------------- 19.55 // FILE DETAILS 19.56 // Project : LatticeMico32 19.57 // File : lm_mc_arithmetic.v 19.58 @@ -149,59 +170,59 @@ 19.59 begin 19.60 if (rst_i == `TRUE) 19.61 begin 19.62 - cycles <= {6{1'b0}}; 19.63 - p <= {`LM32_WORD_WIDTH{1'b0}}; 19.64 - a <= {`LM32_WORD_WIDTH{1'b0}}; 19.65 - b <= {`LM32_WORD_WIDTH{1'b0}}; 19.66 + cycles <= #1 {6{1'b0}}; 19.67 + p <= #1 {`LM32_WORD_WIDTH{1'b0}}; 19.68 + a <= #1 {`LM32_WORD_WIDTH{1'b0}}; 19.69 + b <= #1 {`LM32_WORD_WIDTH{1'b0}}; 19.70 `ifdef CFG_MC_BARREL_SHIFT_ENABLED 19.71 - sign_extend_x <= 1'b0; 19.72 + sign_extend_x <= #1 1'b0; 19.73 `endif 19.74 `ifdef CFG_MC_DIVIDE_ENABLED 19.75 - divide_by_zero_x <= `FALSE; 19.76 + divide_by_zero_x <= #1 `FALSE; 19.77 `endif 19.78 - result_x <= {`LM32_WORD_WIDTH{1'b0}}; 19.79 - state <= `LM32_MC_STATE_IDLE; 19.80 + result_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 19.81 + state <= #1 `LM32_MC_STATE_IDLE; 19.82 end 19.83 else 19.84 begin 19.85 `ifdef CFG_MC_DIVIDE_ENABLED 19.86 - divide_by_zero_x <= `FALSE; 19.87 + divide_by_zero_x <= #1 `FALSE; 19.88 `endif 19.89 case (state) 19.90 `LM32_MC_STATE_IDLE: 19.91 begin 19.92 if (stall_d == `FALSE) 19.93 begin 19.94 - cycles <= `LM32_WORD_WIDTH; 19.95 - p <= 32'b0; 19.96 - a <= operand_0_d; 19.97 - b <= operand_1_d; 19.98 + cycles <= #1 `LM32_WORD_WIDTH; 19.99 + p <= #1 32'b0; 19.100 + a <= #1 operand_0_d; 19.101 + b <= #1 operand_1_d; 19.102 `ifdef CFG_MC_DIVIDE_ENABLED 19.103 if (divide_d == `TRUE) 19.104 - state <= `LM32_MC_STATE_DIVIDE; 19.105 + state <= #1 `LM32_MC_STATE_DIVIDE; 19.106 if (modulus_d == `TRUE) 19.107 - state <= `LM32_MC_STATE_MODULUS; 19.108 + state <= #1 `LM32_MC_STATE_MODULUS; 19.109 `endif 19.110 `ifdef CFG_MC_MULTIPLY_ENABLED 19.111 if (multiply_d == `TRUE) 19.112 - state <= `LM32_MC_STATE_MULTIPLY; 19.113 + state <= #1 `LM32_MC_STATE_MULTIPLY; 19.114 `endif 19.115 `ifdef CFG_MC_BARREL_SHIFT_ENABLED 19.116 if (shift_left_d == `TRUE) 19.117 begin 19.118 - state <= `LM32_MC_STATE_SHIFT_LEFT; 19.119 - sign_extend_x <= sign_extend_d; 19.120 - cycles <= operand_1_d[4:0]; 19.121 - a <= operand_0_d; 19.122 - b <= operand_0_d; 19.123 + state <= #1 `LM32_MC_STATE_SHIFT_LEFT; 19.124 + sign_extend_x <= #1 sign_extend_d; 19.125 + cycles <= #1 operand_1_d[4:0]; 19.126 + a <= #1 operand_0_d; 19.127 + b <= #1 operand_0_d; 19.128 end 19.129 if (shift_right_d == `TRUE) 19.130 begin 19.131 - state <= `LM32_MC_STATE_SHIFT_RIGHT; 19.132 - sign_extend_x <= sign_extend_d; 19.133 - cycles <= operand_1_d[4:0]; 19.134 - a <= operand_0_d; 19.135 - b <= operand_0_d; 19.136 + state <= #1 `LM32_MC_STATE_SHIFT_RIGHT; 19.137 + sign_extend_x <= #1 sign_extend_d; 19.138 + cycles <= #1 operand_1_d[4:0]; 19.139 + a <= #1 operand_0_d; 19.140 + b <= #1 operand_0_d; 19.141 end 19.142 `endif 19.143 end 19.144 @@ -211,74 +232,74 @@ 19.145 begin 19.146 if (t[32] == 1'b0) 19.147 begin 19.148 - p <= t[31:0]; 19.149 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 19.150 + p <= #1 t[31:0]; 19.151 + a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 19.152 end 19.153 else 19.154 begin 19.155 - p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 19.156 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.157 + p <= #1 {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 19.158 + a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.159 end 19.160 - result_x <= a; 19.161 + result_x <= #1 a; 19.162 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.163 begin 19.164 // Check for divide by zero 19.165 - divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}}; 19.166 - state <= `LM32_MC_STATE_IDLE; 19.167 + divide_by_zero_x <= #1 b == {`LM32_WORD_WIDTH{1'b0}}; 19.168 + state <= #1 `LM32_MC_STATE_IDLE; 19.169 end 19.170 - cycles <= cycles - 1'b1; 19.171 + cycles <= #1 cycles - 1'b1; 19.172 end 19.173 `LM32_MC_STATE_MODULUS: 19.174 begin 19.175 if (t[32] == 1'b0) 19.176 begin 19.177 - p <= t[31:0]; 19.178 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 19.179 + p <= #1 t[31:0]; 19.180 + a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 19.181 end 19.182 else 19.183 begin 19.184 - p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 19.185 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.186 + p <= #1 {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 19.187 + a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.188 end 19.189 - result_x <= p; 19.190 + result_x <= #1 p; 19.191 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.192 begin 19.193 // Check for divide by zero 19.194 - divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}}; 19.195 - state <= `LM32_MC_STATE_IDLE; 19.196 + divide_by_zero_x <= #1 b == {`LM32_WORD_WIDTH{1'b0}}; 19.197 + state <= #1 `LM32_MC_STATE_IDLE; 19.198 end 19.199 - cycles <= cycles - 1'b1; 19.200 + cycles <= #1 cycles - 1'b1; 19.201 end 19.202 `endif 19.203 `ifdef CFG_MC_MULTIPLY_ENABLED 19.204 `LM32_MC_STATE_MULTIPLY: 19.205 begin 19.206 if (b[0] == 1'b1) 19.207 - p <= p + a; 19.208 - b <= {1'b0, b[`LM32_WORD_WIDTH-1:1]}; 19.209 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.210 - result_x <= p; 19.211 + p <= #1 p + a; 19.212 + b <= #1 {1'b0, b[`LM32_WORD_WIDTH-1:1]}; 19.213 + a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.214 + result_x <= #1 p; 19.215 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.216 - state <= `LM32_MC_STATE_IDLE; 19.217 - cycles <= cycles - 1'b1; 19.218 + state <= #1 `LM32_MC_STATE_IDLE; 19.219 + cycles <= #1 cycles - 1'b1; 19.220 end 19.221 `endif 19.222 `ifdef CFG_MC_BARREL_SHIFT_ENABLED 19.223 `LM32_MC_STATE_SHIFT_LEFT: 19.224 begin 19.225 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.226 - result_x <= a; 19.227 + a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.228 + result_x <= #1 a; 19.229 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.230 - state <= `LM32_MC_STATE_IDLE; 19.231 - cycles <= cycles - 1'b1; 19.232 + state <= #1 `LM32_MC_STATE_IDLE; 19.233 + cycles <= #1 cycles - 1'b1; 19.234 end 19.235 `LM32_MC_STATE_SHIFT_RIGHT: 19.236 begin 19.237 - b <= {fill_value, b[`LM32_WORD_WIDTH-1:1]}; 19.238 - result_x <= b; 19.239 + b <= #1 {fill_value, b[`LM32_WORD_WIDTH-1:1]}; 19.240 + result_x <= #1 b; 19.241 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.242 - state <= `LM32_MC_STATE_IDLE; 19.243 - cycles <= cycles - 1'b1; 19.244 + state <= #1 `LM32_MC_STATE_IDLE; 19.245 + cycles <= #1 cycles - 1'b1; 19.246 end 19.247 `endif 19.248 endcase
20.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_monitor.v 20.2 --- a/lm32_monitor.v Sun Mar 06 21:14:43 2011 +0000 20.3 +++ b/lm32_monitor.v Sat Aug 06 00:02:46 2011 +0100 20.4 @@ -1,18 +1,39 @@ 20.5 -// ============================================================================= 20.6 -// COPYRIGHT NOTICE 20.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 20.8 -// ALL RIGHTS RESERVED 20.9 -// This confidential and proprietary software may be used only as authorised by 20.10 -// a licensing agreement from Lattice Semiconductor Corporation. 20.11 -// The entire notice above must be reproduced on all authorized copies and 20.12 -// copies may only be made to the extent permitted by a licensing agreement from 20.13 -// Lattice Semiconductor Corporation. 20.14 +// ================================================================== 20.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 20.16 +// ------------------------------------------------------------------ 20.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 20.18 +// ALL RIGHTS RESERVED 20.19 +// ------------------------------------------------------------------ 20.20 +// 20.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 20.22 +// 20.23 +// Permission: 20.24 +// 20.25 +// Lattice Semiconductor grants permission to use this code 20.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 20.27 +// Open Source License Agreement. 20.28 +// 20.29 +// Disclaimer: 20.30 // 20.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 20.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 20.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 20.34 -// U.S.A email: techsupport@latticesemi.com 20.35 -// =============================================================================/ 20.36 +// Lattice Semiconductor provides no warranty regarding the use or 20.37 +// functionality of this code. It is the user's responsibility to 20.38 +// verify the user’s design for consistency and functionality through 20.39 +// the use of formal verification methods. 20.40 +// 20.41 +// -------------------------------------------------------------------- 20.42 +// 20.43 +// Lattice Semiconductor Corporation 20.44 +// 5555 NE Moore Court 20.45 +// Hillsboro, OR 97214 20.46 +// U.S.A 20.47 +// 20.48 +// TEL: 1-800-Lattice (USA and Canada) 20.49 +// 503-286-8001 (other locations) 20.50 +// 20.51 +// web: http://www.latticesemi.com/ 20.52 +// email: techsupport@latticesemi.com 20.53 +// 20.54 +// -------------------------------------------------------------------- 20.55 // FILE DETAILS 20.56 // Project : LatticeMico32 20.57 // File : lm32_monitor.v 20.58 @@ -123,10 +144,10 @@ 20.59 begin 20.60 if (rst_i == `TRUE) 20.61 begin 20.62 - write_enable <= `FALSE; 20.63 - MON_ACK_O <= `FALSE; 20.64 - MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 20.65 - state <= 2'b00; 20.66 + write_enable <= #1 `FALSE; 20.67 + MON_ACK_O <= #1 `FALSE; 20.68 + MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}}; 20.69 + state <= #1 2'b00; 20.70 end 20.71 else 20.72 begin 20.73 @@ -134,33 +155,33 @@ 20.74 2'b01: 20.75 begin 20.76 // Output read data to Wishbone 20.77 - MON_ACK_O <= `TRUE; 20.78 - MON_DAT_O <= data; 20.79 + MON_ACK_O <= #1 `TRUE; 20.80 + MON_DAT_O <= #1 data; 20.81 // Sub-word writes are performed using read-modify-write 20.82 // as the Lattice EBRs don't support byte enables 20.83 if (MON_WE_I == `TRUE) 20.84 - write_enable <= `TRUE; 20.85 - write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0]; 20.86 - write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8]; 20.87 - write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16]; 20.88 - write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24]; 20.89 - state <= 2'b10; 20.90 + write_enable <= #1 `TRUE; 20.91 + write_data[7:0] <= #1 MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0]; 20.92 + write_data[15:8] <= #1 MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8]; 20.93 + write_data[23:16] <= #1 MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16]; 20.94 + write_data[31:24] <= #1 MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24]; 20.95 + state <= #1 2'b10; 20.96 end 20.97 2'b10: 20.98 begin 20.99 // Wishbone access occurs in this cycle 20.100 - write_enable <= `FALSE; 20.101 - MON_ACK_O <= `FALSE; 20.102 - MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 20.103 - state <= 2'b00; 20.104 + write_enable <= #1 `FALSE; 20.105 + MON_ACK_O <= #1 `FALSE; 20.106 + MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}}; 20.107 + state <= #1 2'b00; 20.108 end 20.109 default: 20.110 begin 20.111 - write_enable <= `FALSE; 20.112 - MON_ACK_O <= `FALSE; 20.113 + write_enable <= #1 `FALSE; 20.114 + MON_ACK_O <= #1 `FALSE; 20.115 // Wait for a Wishbone access 20.116 if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE)) 20.117 - state <= 2'b01; 20.118 + state <= #1 2'b01; 20.119 end 20.120 endcase 20.121 end
21.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_monitor_ram.v 21.2 --- a/lm32_monitor_ram.v Sun Mar 06 21:14:43 2011 +0000 21.3 +++ b/lm32_monitor_ram.v Sat Aug 06 00:02:46 2011 +0100 21.4 @@ -1,18 +1,39 @@ 21.5 -// ============================================================================= 21.6 -// COPYRIGHT NOTICE 21.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 21.8 -// ALL RIGHTS RESERVED 21.9 -// This confidential and proprietary software may be used only as authorised by 21.10 -// a licensing agreement from Lattice Semiconductor Corporation. 21.11 -// The entire notice above must be reproduced on all authorized copies and 21.12 -// copies may only be made to the extent permitted by a licensing agreement from 21.13 -// Lattice Semiconductor Corporation. 21.14 +// ================================================================== 21.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 21.16 +// ------------------------------------------------------------------ 21.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 21.18 +// ALL RIGHTS RESERVED 21.19 +// ------------------------------------------------------------------ 21.20 +// 21.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 21.22 +// 21.23 +// Permission: 21.24 +// 21.25 +// Lattice Semiconductor grants permission to use this code 21.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 21.27 +// Open Source License Agreement. 21.28 +// 21.29 +// Disclaimer: 21.30 // 21.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 21.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 21.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 21.34 -// U.S.A email: techsupport@latticesemi.com 21.35 -// =============================================================================/ 21.36 +// Lattice Semiconductor provides no warranty regarding the use or 21.37 +// functionality of this code. It is the user's responsibility to 21.38 +// verify the user’s design for consistency and functionality through 21.39 +// the use of formal verification methods. 21.40 +// 21.41 +// -------------------------------------------------------------------- 21.42 +// 21.43 +// Lattice Semiconductor Corporation 21.44 +// 5555 NE Moore Court 21.45 +// Hillsboro, OR 97214 21.46 +// U.S.A 21.47 +// 21.48 +// TEL: 1-800-Lattice (USA and Canada) 21.49 +// 503-286-8001 (other locations) 21.50 +// 21.51 +// web: http://www.latticesemi.com/ 21.52 +// email: techsupport@latticesemi.com 21.53 +// 21.54 +// -------------------------------------------------------------------- 21.55 // FILE DETAILS 21.56 // Project : LatticeMico32 21.57 // File : lm32_monitor_ram.v
22.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_multiplier.v 22.2 --- a/lm32_multiplier.v Sun Mar 06 21:14:43 2011 +0000 22.3 +++ b/lm32_multiplier.v Sat Aug 06 00:02:46 2011 +0100 22.4 @@ -1,18 +1,39 @@ 22.5 -// ============================================================================= 22.6 -// COPYRIGHT NOTICE 22.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 22.8 -// ALL RIGHTS RESERVED 22.9 -// This confidential and proprietary software may be used only as authorised by 22.10 -// a licensing agreement from Lattice Semiconductor Corporation. 22.11 -// The entire notice above must be reproduced on all authorized copies and 22.12 -// copies may only be made to the extent permitted by a licensing agreement from 22.13 -// Lattice Semiconductor Corporation. 22.14 +// ================================================================== 22.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 22.16 +// ------------------------------------------------------------------ 22.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 22.18 +// ALL RIGHTS RESERVED 22.19 +// ------------------------------------------------------------------ 22.20 +// 22.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 22.22 +// 22.23 +// Permission: 22.24 +// 22.25 +// Lattice Semiconductor grants permission to use this code 22.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 22.27 +// Open Source License Agreement. 22.28 +// 22.29 +// Disclaimer: 22.30 // 22.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 22.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 22.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 22.34 -// U.S.A email: techsupport@latticesemi.com 22.35 -// =============================================================================/ 22.36 +// Lattice Semiconductor provides no warranty regarding the use or 22.37 +// functionality of this code. It is the user's responsibility to 22.38 +// verify the user’s design for consistency and functionality through 22.39 +// the use of formal verification methods. 22.40 +// 22.41 +// -------------------------------------------------------------------- 22.42 +// 22.43 +// Lattice Semiconductor Corporation 22.44 +// 5555 NE Moore Court 22.45 +// Hillsboro, OR 97214 22.46 +// U.S.A 22.47 +// 22.48 +// TEL: 1-800-Lattice (USA and Canada) 22.49 +// 503-286-8001 (other locations) 22.50 +// 22.51 +// web: http://www.latticesemi.com/ 22.52 +// email: techsupport@latticesemi.com 22.53 +// 22.54 +// -------------------------------------------------------------------- 22.55 // FILE DETAILS 22.56 // Project : LatticeMico32 22.57 // File : lm32_multiplier.v 22.58 @@ -78,21 +99,21 @@ 22.59 begin 22.60 if (rst_i == `TRUE) 22.61 begin 22.62 - muliplicand <= {`LM32_WORD_WIDTH{1'b0}}; 22.63 - multiplier <= {`LM32_WORD_WIDTH{1'b0}}; 22.64 - product <= {`LM32_WORD_WIDTH{1'b0}}; 22.65 - result <= {`LM32_WORD_WIDTH{1'b0}}; 22.66 + muliplicand <= #1 {`LM32_WORD_WIDTH{1'b0}}; 22.67 + multiplier <= #1 {`LM32_WORD_WIDTH{1'b0}}; 22.68 + product <= #1 {`LM32_WORD_WIDTH{1'b0}}; 22.69 + result <= #1 {`LM32_WORD_WIDTH{1'b0}}; 22.70 end 22.71 else 22.72 begin 22.73 if (stall_x == `FALSE) 22.74 begin 22.75 - muliplicand <= operand_0; 22.76 - multiplier <= operand_1; 22.77 + muliplicand <= #1 operand_0; 22.78 + multiplier <= #1 operand_1; 22.79 end 22.80 if (stall_m == `FALSE) 22.81 - product <= muliplicand * multiplier; 22.82 - result <= product; 22.83 + product <= #1 muliplicand * multiplier; 22.84 + result <= #1 product; 22.85 end 22.86 end 22.87
23.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_ram.v 23.2 --- a/lm32_ram.v Sun Mar 06 21:14:43 2011 +0000 23.3 +++ b/lm32_ram.v Sat Aug 06 00:02:46 2011 +0100 23.4 @@ -1,18 +1,39 @@ 23.5 -// ============================================================================= 23.6 -// COPYRIGHT NOTICE 23.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 23.8 -// ALL RIGHTS RESERVED 23.9 -// This confidential and proprietary software may be used only as authorised by 23.10 -// a licensing agreement from Lattice Semiconductor Corporation. 23.11 -// The entire notice above must be reproduced on all authorized copies and 23.12 -// copies may only be made to the extent permitted by a licensing agreement from 23.13 -// Lattice Semiconductor Corporation. 23.14 +// ================================================================== 23.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 23.16 +// ------------------------------------------------------------------ 23.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 23.18 +// ALL RIGHTS RESERVED 23.19 +// ------------------------------------------------------------------ 23.20 +// 23.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 23.22 +// 23.23 +// Permission: 23.24 +// 23.25 +// Lattice Semiconductor grants permission to use this code 23.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 23.27 +// Open Source License Agreement. 23.28 +// 23.29 +// Disclaimer: 23.30 // 23.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 23.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 23.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 23.34 -// U.S.A email: techsupport@latticesemi.com 23.35 -// =============================================================================/ 23.36 +// Lattice Semiconductor provides no warranty regarding the use or 23.37 +// functionality of this code. It is the user's responsibility to 23.38 +// verify the user’s design for consistency and functionality through 23.39 +// the use of formal verification methods. 23.40 +// 23.41 +// -------------------------------------------------------------------- 23.42 +// 23.43 +// Lattice Semiconductor Corporation 23.44 +// 5555 NE Moore Court 23.45 +// Hillsboro, OR 97214 23.46 +// U.S.A 23.47 +// 23.48 +// TEL: 1-800-Lattice (USA and Canada) 23.49 +// 503-286-8001 (other locations) 23.50 +// 23.51 +// web: http://www.latticesemi.com/ 23.52 +// email: techsupport@latticesemi.com 23.53 +// 23.54 +// -------------------------------------------------------------------- 23.55 // FILE DETAILS 23.56 // Project : LatticeMico32 23.57 // File : lm32_ram.v 23.58 @@ -252,7 +273,7 @@ 23.59 23.60 always @(posedge read_clk) 23.61 if (enable_read) 23.62 - ra <= read_address; 23.63 + ra <= #1 read_address; 23.64 end 23.65 23.66 else 23.67 @@ -275,12 +296,12 @@ 23.68 // Write port 23.69 always @(posedge write_clk) 23.70 if ((write_enable == `TRUE) && (enable_write == `TRUE)) 23.71 - mem[write_address] <= write_data; 23.72 + mem[write_address] <= #1 write_data; 23.73 23.74 // Register read address for use on next cycle 23.75 always @(posedge read_clk) 23.76 if (enable_read) 23.77 - ra <= read_address; 23.78 + ra <= #1 read_address; 23.79 23.80 end 23.81
24.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_shifter.v 24.2 --- a/lm32_shifter.v Sun Mar 06 21:14:43 2011 +0000 24.3 +++ b/lm32_shifter.v Sat Aug 06 00:02:46 2011 +0100 24.4 @@ -1,18 +1,39 @@ 24.5 -// ============================================================================= 24.6 -// COPYRIGHT NOTICE 24.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 24.8 -// ALL RIGHTS RESERVED 24.9 -// This confidential and proprietary software may be used only as authorised by 24.10 -// a licensing agreement from Lattice Semiconductor Corporation. 24.11 -// The entire notice above must be reproduced on all authorized copies and 24.12 -// copies may only be made to the extent permitted by a licensing agreement from 24.13 -// Lattice Semiconductor Corporation. 24.14 +// ================================================================== 24.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 24.16 +// ------------------------------------------------------------------ 24.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 24.18 +// ALL RIGHTS RESERVED 24.19 +// ------------------------------------------------------------------ 24.20 +// 24.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 24.22 +// 24.23 +// Permission: 24.24 +// 24.25 +// Lattice Semiconductor grants permission to use this code 24.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 24.27 +// Open Source License Agreement. 24.28 +// 24.29 +// Disclaimer: 24.30 // 24.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 24.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 24.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 24.34 -// U.S.A email: techsupport@latticesemi.com 24.35 -// =============================================================================/ 24.36 +// Lattice Semiconductor provides no warranty regarding the use or 24.37 +// functionality of this code. It is the user's responsibility to 24.38 +// verify the user’s design for consistency and functionality through 24.39 +// the use of formal verification methods. 24.40 +// 24.41 +// -------------------------------------------------------------------- 24.42 +// 24.43 +// Lattice Semiconductor Corporation 24.44 +// 5555 NE Moore Court 24.45 +// Hillsboro, OR 97214 24.46 +// U.S.A 24.47 +// 24.48 +// TEL: 1-800-Lattice (USA and Canada) 24.49 +// 503-286-8001 (other locations) 24.50 +// 24.51 +// web: http://www.latticesemi.com/ 24.52 +// email: techsupport@latticesemi.com 24.53 +// 24.54 +// -------------------------------------------------------------------- 24.55 // FILE DETAILS 24.56 // Project : LatticeMico32 24.57 // File : lm32_shifter.v 24.58 @@ -118,15 +139,15 @@ 24.59 begin 24.60 if (rst_i == `TRUE) 24.61 begin 24.62 - right_shift_result <= {`LM32_WORD_WIDTH{1'b0}}; 24.63 - direction_m <= `FALSE; 24.64 + right_shift_result <= #1 {`LM32_WORD_WIDTH{1'b0}}; 24.65 + direction_m <= #1 `FALSE; 24.66 end 24.67 else 24.68 begin 24.69 if (stall_x == `FALSE) 24.70 begin 24.71 - right_shift_result <= {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG]; 24.72 - direction_m <= direction_x; 24.73 + right_shift_result <= #1 {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG]; 24.74 + direction_m <= #1 direction_x; 24.75 end 24.76 end 24.77 end
25.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_top.v 25.2 --- a/lm32_top.v Sun Mar 06 21:14:43 2011 +0000 25.3 +++ b/lm32_top.v Sat Aug 06 00:02:46 2011 +0100 25.4 @@ -1,18 +1,39 @@ 25.5 -// ============================================================================= 25.6 -// COPYRIGHT NOTICE 25.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 25.8 -// ALL RIGHTS RESERVED 25.9 -// This confidential and proprietary software may be used only as authorised by 25.10 -// a licensing agreement from Lattice Semiconductor Corporation. 25.11 -// The entire notice above must be reproduced on all authorized copies and 25.12 -// copies may only be made to the extent permitted by a licensing agreement from 25.13 -// Lattice Semiconductor Corporation. 25.14 +// ================================================================== 25.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 25.16 +// ------------------------------------------------------------------ 25.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 25.18 +// ALL RIGHTS RESERVED 25.19 +// ------------------------------------------------------------------ 25.20 +// 25.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 25.22 +// 25.23 +// Permission: 25.24 +// 25.25 +// Lattice Semiconductor grants permission to use this code 25.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 25.27 +// Open Source License Agreement. 25.28 +// 25.29 +// Disclaimer: 25.30 // 25.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 25.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 25.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 25.34 -// U.S.A email: techsupport@latticesemi.com 25.35 -// =============================================================================/ 25.36 +// Lattice Semiconductor provides no warranty regarding the use or 25.37 +// functionality of this code. It is the user's responsibility to 25.38 +// verify the user’s design for consistency and functionality through 25.39 +// the use of formal verification methods. 25.40 +// 25.41 +// -------------------------------------------------------------------- 25.42 +// 25.43 +// Lattice Semiconductor Corporation 25.44 +// 5555 NE Moore Court 25.45 +// Hillsboro, OR 97214 25.46 +// U.S.A 25.47 +// 25.48 +// TEL: 1-800-Lattice (USA and Canada) 25.49 +// 503-286-8001 (other locations) 25.50 +// 25.51 +// web: http://www.latticesemi.com/ 25.52 +// email: techsupport@latticesemi.com 25.53 +// 25.54 +// -------------------------------------------------------------------- 25.55 // FILE DETAILS 25.56 // Project : LatticeMico32 25.57 // File : lm32_top.v 25.58 @@ -36,6 +57,11 @@ 25.59 // ----- Inputs ------- 25.60 clk_i, 25.61 rst_i, 25.62 +`ifdef CFG_DEBUG_ENABLED 25.63 + `ifdef CFG_ALTERNATE_EBA 25.64 + at_debug, 25.65 + `endif 25.66 +`endif 25.67 // From external devices 25.68 `ifdef CFG_INTERRUPTS_ENABLED 25.69 interrupt_n, 25.70 @@ -110,6 +136,12 @@ 25.71 input clk_i; // Clock 25.72 input rst_i; // Reset 25.73 25.74 +`ifdef CFG_DEBUG_ENABLED 25.75 + `ifdef CFG_ALTERNATE_EBA 25.76 + input at_debug; // GPIO input that maps EBA to DEBA 25.77 + `endif 25.78 +`endif 25.79 + 25.80 `ifdef CFG_INTERRUPTS_ENABLED 25.81 input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low 25.82 `endif 25.83 @@ -249,6 +281,11 @@ 25.84 .clk_n_i (clk_n), 25.85 `endif 25.86 .rst_i (rst_i), 25.87 +`ifdef CFG_DEBUG_ENABLED 25.88 + `ifdef CFG_ALTERNATE_EBA 25.89 + .at_debug (at_debug), 25.90 + `endif 25.91 +`endif 25.92 // From external devices 25.93 `ifdef CFG_INTERRUPTS_ENABLED 25.94 .interrupt_n (interrupt_n),
26.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_trace.v 26.2 --- a/lm32_trace.v Sun Mar 06 21:14:43 2011 +0000 26.3 +++ b/lm32_trace.v Sat Aug 06 00:02:46 2011 +0100 26.4 @@ -1,18 +1,39 @@ 26.5 -// ============================================================================= 26.6 -// COPYRIGHT NOTICE 26.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 26.8 -// ALL RIGHTS RESERVED 26.9 -// This confidential and proprietary software may be used only as authorised by 26.10 -// a licensing agreement from Lattice Semiconductor Corporation. 26.11 -// The entire notice above must be reproduced on all authorized copies and 26.12 -// copies may only be made to the extent permitted by a licensing agreement from 26.13 -// Lattice Semiconductor Corporation. 26.14 +// ================================================================== 26.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 26.16 +// ------------------------------------------------------------------ 26.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 26.18 +// ALL RIGHTS RESERVED 26.19 +// ------------------------------------------------------------------ 26.20 +// 26.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 26.22 +// 26.23 +// Permission: 26.24 +// 26.25 +// Lattice Semiconductor grants permission to use this code 26.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 26.27 +// Open Source License Agreement. 26.28 +// 26.29 +// Disclaimer: 26.30 // 26.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 26.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 26.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 26.34 -// U.S.A email: techsupport@latticesemi.com 26.35 -// =============================================================================/ 26.36 +// Lattice Semiconductor provides no warranty regarding the use or 26.37 +// functionality of this code. It is the user's responsibility to 26.38 +// verify the user’s design for consistency and functionality through 26.39 +// the use of formal verification methods. 26.40 +// 26.41 +// -------------------------------------------------------------------- 26.42 +// 26.43 +// Lattice Semiconductor Corporation 26.44 +// 5555 NE Moore Court 26.45 +// Hillsboro, OR 97214 26.46 +// U.S.A 26.47 +// 26.48 +// TEL: 1-800-Lattice (USA and Canada) 26.49 +// 503-286-8001 (other locations) 26.50 +// 26.51 +// web: http://www.latticesemi.com/ 26.52 +// email: techsupport@latticesemi.com 26.53 +// 26.54 +// -------------------------------------------------------------------- 26.55 // FILE DETAILS 26.56 // Project : LatticeMico32 26.57 // File : lm32_trace.v 26.58 @@ -24,6 +45,8 @@ 26.59 // : No Change 26.60 // Version : 3.1 26.61 // : No Change 26.62 +// Version : 3.7 26.63 +// : Removed syntax error. 26.64 // ============================================================================= 26.65 26.66 `include "lm32_include.v" 26.67 @@ -123,65 +146,65 @@ 26.68 assign dat_o = (rw_creg ? reg_dat_o : trace_dat_o); 26.69 26.70 initial begin 26.71 - trig_type <= 0; 26.72 - stop_type <= 0; 26.73 - trace_len <= 0; 26.74 - pc_low <= 0; 26.75 - pc_high <= 0; 26.76 - trace_start <= 0; 26.77 - trace_stop <= 0; 26.78 - ack_o <= 0; 26.79 - reg_dat_o <= 0; 26.80 - mem_valid <= 0; 26.81 - started <= 0; 26.82 - capturing <= 0; 26.83 + trig_type <= #1 0; 26.84 + stop_type <= #1 0; 26.85 + trace_len <= #1 0; 26.86 + pc_low <= #1 0; 26.87 + pc_high <= #1 0; 26.88 + trace_start <= #1 0; 26.89 + trace_stop <= #1 0; 26.90 + ack_o <= #1 0; 26.91 + reg_dat_o <= #1 0; 26.92 + mem_valid <= #1 0; 26.93 + started <= #1 0; 26.94 + capturing <= #1 0; 26.95 end 26.96 26.97 // the host side control 26.98 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 26.99 begin 26.100 if (rst_i == `TRUE) begin 26.101 - trig_type <= 0; 26.102 - trace_stop <= 0; 26.103 - trace_start <= 0; 26.104 - pc_low <= 0; 26.105 - pc_high <= 0; 26.106 - ack_o <= 0; 26.107 + trig_type <= #1 0; 26.108 + trace_stop <= #1 0; 26.109 + trace_start <= #1 0; 26.110 + pc_low <= #1 0; 26.111 + pc_high <= #1 0; 26.112 + ack_o <= #1 0; 26.113 end else begin 26.114 if (stb_i == `TRUE && ack_o == `FALSE) begin 26.115 if (rw_creg) begin // control register access 26.116 - ack_o <= `TRUE; 26.117 + ack_o <= #1 `TRUE; 26.118 if (we_i == `TRUE) begin 26.119 case ({adr_i[11:2],2'b0}) 26.120 // write to trig type 26.121 12'd0: 26.122 begin 26.123 if (sel_i[0]) begin 26.124 - trig_type[4:0] <= dat_i[4:0]; 26.125 + trig_type[4:0] <= #1 dat_i[4:0]; 26.126 end 26.127 if (sel_i[3]) begin 26.128 - trace_start <= dat_i[31]; 26.129 - trace_stop <= dat_i[30]; 26.130 + trace_start <= #1 dat_i[31]; 26.131 + trace_stop <= #1 dat_i[30]; 26.132 end 26.133 end 26.134 12'd8: 26.135 begin 26.136 - if (sel_i[3]) pc_low[31:24] <= dat_i[31:24]; 26.137 - if (sel_i[2]) pc_low[23:16] <= dat_i[23:16]; 26.138 - if (sel_i[1]) pc_low[15:8] <= dat_i[15:8]; 26.139 - if (sel_i[0]) pc_low[7:0] <= dat_i[7:0]; 26.140 + if (sel_i[3]) pc_low[31:24] <= #1 dat_i[31:24]; 26.141 + if (sel_i[2]) pc_low[23:16] <= #1 dat_i[23:16]; 26.142 + if (sel_i[1]) pc_low[15:8] <= #1 dat_i[15:8]; 26.143 + if (sel_i[0]) pc_low[7:0] <= #1 dat_i[7:0]; 26.144 end 26.145 12'd12: 26.146 begin 26.147 - if (sel_i[3]) pc_high[31:24] <= dat_i[31:24]; 26.148 - if (sel_i[2]) pc_high[23:16] <= dat_i[23:16]; 26.149 - if (sel_i[1]) pc_high[15:8] <= dat_i[15:8]; 26.150 - if (sel_i[0]) pc_high[7:0] <= dat_i[7:0]; 26.151 + if (sel_i[3]) pc_high[31:24] <= #1 dat_i[31:24]; 26.152 + if (sel_i[2]) pc_high[23:16] <= #1 dat_i[23:16]; 26.153 + if (sel_i[1]) pc_high[15:8] <= #1 dat_i[15:8]; 26.154 + if (sel_i[0]) pc_high[7:0] <= #1 dat_i[7:0]; 26.155 end 26.156 12'd16: 26.157 begin 26.158 if (sel_i[0])begin 26.159 - stop_type[4:0] <= dat_i[4:0]; 26.160 + stop_type[4:0] <= #1 dat_i[4:0]; 26.161 end 26.162 end 26.163 endcase 26.164 @@ -189,27 +212,27 @@ 26.165 case ({adr_i[11:2],2'b0}) 26.166 // read the trig type 26.167 12'd0: 26.168 - reg_dat_o <= {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 26.169 + reg_dat_o <= #1 {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 26.170 12'd4: 26.171 - reg_dat_o <= trace_len; 26.172 + reg_dat_o <= #1 trace_len; 26.173 12'd8: 26.174 - reg_dat_o <= pc_low; 26.175 + reg_dat_o <= #1 pc_low; 26.176 12'd12: 26.177 - reg_dat_o <= pc_high; 26.178 + reg_dat_o <= #1 pc_high; 26.179 default: 26.180 - reg_dat_o <= {27'b0,stop_type}; 26.181 + reg_dat_o <= #1 {27'b0,stop_type}; 26.182 endcase 26.183 end // else: !if(we_i == `TRUE) 26.184 end else // read / write memory 26.185 if (we_i == `FALSE) begin 26.186 - ack_o <= `TRUE; 26.187 + ack_o <= #1 `TRUE; 26.188 end else 26.189 - ack_o <= `FALSE; 26.190 + ack_o <= #1 `FALSE; 26.191 // not allowed to write to trace memory 26.192 end else begin // if (stb_i == `TRUE) 26.193 - trace_start <= `FALSE; 26.194 - trace_stop <= `FALSE; 26.195 - ack_o <= `FALSE; 26.196 + trace_start <= #1 `FALSE; 26.197 + trace_stop <= #1 `FALSE; 26.198 + ack_o <= #1 `FALSE; 26.199 end // else: !if(stb_i == `TRUE) 26.200 end // else: !if(rst_i == `TRUE) 26.201 end 26.202 @@ -245,31 +268,31 @@ 26.203 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 26.204 begin 26.205 if (rst_i == `TRUE) begin 26.206 - tstate <= 0; 26.207 - trace_we <= 0; 26.208 - trace_len <= 0; 26.209 - ovrflw <= `FALSE; 26.210 - mem_valid <= 0; 26.211 - started <= 0; 26.212 - capturing <= 0; 26.213 + tstate <= #1 0; 26.214 + trace_we <= #1 0; 26.215 + trace_len <= #1 0; 26.216 + ovrflw <= #1 `FALSE; 26.217 + mem_valid <= #1 0; 26.218 + started <= #1 0; 26.219 + capturing <= #1 0; 26.220 end else begin 26.221 case (tstate) 26.222 3'd0: 26.223 // start capture 26.224 if (trace_start) begin 26.225 - tstate <= 3'd1; 26.226 - mem_valid <= 0; 26.227 - started <= 1; 26.228 + tstate <= #1 3'd1; 26.229 + mem_valid <= #1 0; 26.230 + started <= #1 1; 26.231 end 26.232 3'd1: 26.233 begin 26.234 // wait for trigger 26.235 if (trace_begin) begin 26.236 - capturing <= 1; 26.237 - tstate <= 3'd2; 26.238 - trace_we <= `TRUE; 26.239 - trace_len <= 0; 26.240 - ovrflw <= `FALSE; 26.241 + capturing <= #1 1; 26.242 + tstate <= #1 3'd2; 26.243 + trace_we <= #1 `TRUE; 26.244 + trace_len <= #1 0; 26.245 + ovrflw <= #1 `FALSE; 26.246 end 26.247 end // case: 3'd1 26.248 26.249 @@ -277,18 +300,18 @@ 26.250 begin 26.251 if (trace_pc_valid) begin 26.252 if (trace_len[mem_addr_width]) 26.253 - trace_len <= 0; 26.254 + trace_len <= #1 0; 26.255 else 26.256 - trace_len <= trace_len + 1; 26.257 + trace_len <= #1 trace_len + 1; 26.258 end 26.259 - if (!ovrflw) ovrflw <= trace_len[mem_addr_width]; 26.260 + if (!ovrflw) ovrflw <= #1 trace_len[mem_addr_width]; 26.261 // wait for stop condition 26.262 if (trace_end) begin 26.263 - tstate <= 3'd0; 26.264 - trace_we <= 0; 26.265 - mem_valid <= 1; 26.266 - started <= 0; 26.267 - capturing <= 0; 26.268 + tstate <= #1 3'd0; 26.269 + trace_we <= #1 0; 26.270 + mem_valid <= #1 1; 26.271 + started <= #1 0; 26.272 + capturing <= #1 0; 26.273 end 26.274 end // case: 3'd2 26.275 endcase
27.1 diff -r 35dc7ba83714 -r 73de224304c1 spiprog.v 27.2 --- a/spiprog.v Sun Mar 06 21:14:43 2011 +0000 27.3 +++ b/spiprog.v Sat Aug 06 00:02:46 2011 +0100 27.4 @@ -1,18 +1,39 @@ 27.5 -// ============================================================================= 27.6 -// COPYRIGHT NOTICE 27.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 27.8 -// ALL RIGHTS RESERVED 27.9 -// This confidential and proprietary software may be used only as authorised by 27.10 -// a licensing agreement from Lattice Semiconductor Corporation. 27.11 -// The entire notice above must be reproduced on all authorized copies and 27.12 -// copies may only be made to the extent permitted by a licensing agreement from 27.13 -// Lattice Semiconductor Corporation. 27.14 +// ================================================================== 27.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 27.16 +// ------------------------------------------------------------------ 27.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 27.18 +// ALL RIGHTS RESERVED 27.19 +// ------------------------------------------------------------------ 27.20 +// 27.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 27.22 +// 27.23 +// Permission: 27.24 +// 27.25 +// Lattice Semiconductor grants permission to use this code 27.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 27.27 +// Open Source License Agreement. 27.28 +// 27.29 +// Disclaimer: 27.30 // 27.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 27.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 27.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 27.34 -// U.S.A email: techsupport@latticesemi.com 27.35 -// =============================================================================/ 27.36 +// Lattice Semiconductor provides no warranty regarding the use or 27.37 +// functionality of this code. It is the user's responsibility to 27.38 +// verify the user’s design for consistency and functionality through 27.39 +// the use of formal verification methods. 27.40 +// 27.41 +// -------------------------------------------------------------------- 27.42 +// 27.43 +// Lattice Semiconductor Corporation 27.44 +// 5555 NE Moore Court 27.45 +// Hillsboro, OR 97214 27.46 +// U.S.A 27.47 +// 27.48 +// TEL: 1-800-Lattice (USA and Canada) 27.49 +// 503-286-8001 (other locations) 27.50 +// 27.51 +// web: http://www.latticesemi.com/ 27.52 +// email: techsupport@latticesemi.com 27.53 +// 27.54 +// -------------------------------------------------------------------- 27.55 // FILE DETAILS 27.56 // Project : LatticeMico32 27.57 // File : SPIPROG.v
28.1 diff -r 35dc7ba83714 -r 73de224304c1 typea.v 28.2 --- a/typea.v Sun Mar 06 21:14:43 2011 +0000 28.3 +++ b/typea.v Sat Aug 06 00:02:46 2011 +0100 28.4 @@ -1,18 +1,39 @@ 28.5 -// ============================================================================= 28.6 -// COPYRIGHT NOTICE 28.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 28.8 -// ALL RIGHTS RESERVED 28.9 -// This confidential and proprietary software may be used only as authorised by 28.10 -// a licensing agreement from Lattice Semiconductor Corporation. 28.11 -// The entire notice above must be reproduced on all authorized copies and 28.12 -// copies may only be made to the extent permitted by a licensing agreement from 28.13 -// Lattice Semiconductor Corporation. 28.14 +// ================================================================== 28.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 28.16 +// ------------------------------------------------------------------ 28.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 28.18 +// ALL RIGHTS RESERVED 28.19 +// ------------------------------------------------------------------ 28.20 +// 28.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 28.22 +// 28.23 +// Permission: 28.24 +// 28.25 +// Lattice Semiconductor grants permission to use this code 28.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 28.27 +// Open Source License Agreement. 28.28 +// 28.29 +// Disclaimer: 28.30 // 28.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 28.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 28.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 28.34 -// U.S.A email: techsupport@latticesemi.com 28.35 -// =============================================================================/ 28.36 +// Lattice Semiconductor provides no warranty regarding the use or 28.37 +// functionality of this code. It is the user's responsibility to 28.38 +// verify the user’s design for consistency and functionality through 28.39 +// the use of formal verification methods. 28.40 +// 28.41 +// -------------------------------------------------------------------- 28.42 +// 28.43 +// Lattice Semiconductor Corporation 28.44 +// 5555 NE Moore Court 28.45 +// Hillsboro, OR 97214 28.46 +// U.S.A 28.47 +// 28.48 +// TEL: 1-800-Lattice (USA and Canada) 28.49 +// 503-286-8001 (other locations) 28.50 +// 28.51 +// web: http://www.latticesemi.com/ 28.52 +// email: techsupport@latticesemi.com 28.53 +// 28.54 +// -------------------------------------------------------------------- 28.55 // FILE DETAILS 28.56 // Project : LatticeMico32 28.57 // File : TYPEA.v 28.58 @@ -59,13 +80,13 @@ 28.59 always @ (negedge CLK or negedge RESET_N) 28.60 begin 28.61 if (RESET_N == 1'b0) 28.62 - tdoInt <= 1'b0; 28.63 + tdoInt <= #1 1'b0; 28.64 else if (CLK == 1'b0) 28.65 if (CLKEN == 1'b1) 28.66 if (CAPTURE_DR == 1'b0) 28.67 - tdoInt <= TDI; 28.68 + tdoInt <= #1 TDI; 28.69 else 28.70 - tdoInt <= DATA_IN; 28.71 + tdoInt <= #1 DATA_IN; 28.72 end 28.73 28.74 assign TDO = tdoInt; 28.75 @@ -73,9 +94,9 @@ 28.76 always @ (negedge CLK or negedge RESET_N) 28.77 begin 28.78 if (RESET_N == 1'b0) 28.79 - DATA_OUT <= 1'b0; 28.80 + DATA_OUT <= #1 1'b0; 28.81 else if (CLK == 1'b0) 28.82 if (UPDATE_DR == 1'b1) 28.83 - DATA_OUT <= tdoInt; 28.84 + DATA_OUT <= #1 tdoInt; 28.85 end 28.86 endmodule
29.1 diff -r 35dc7ba83714 -r 73de224304c1 typeb.v 29.2 --- a/typeb.v Sun Mar 06 21:14:43 2011 +0000 29.3 +++ b/typeb.v Sat Aug 06 00:02:46 2011 +0100 29.4 @@ -1,18 +1,39 @@ 29.5 -// ============================================================================= 29.6 -// COPYRIGHT NOTICE 29.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 29.8 -// ALL RIGHTS RESERVED 29.9 -// This confidential and proprietary software may be used only as authorised by 29.10 -// a licensing agreement from Lattice Semiconductor Corporation. 29.11 -// The entire notice above must be reproduced on all authorized copies and 29.12 -// copies may only be made to the extent permitted by a licensing agreement from 29.13 -// Lattice Semiconductor Corporation. 29.14 +// ================================================================== 29.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 29.16 +// ------------------------------------------------------------------ 29.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 29.18 +// ALL RIGHTS RESERVED 29.19 +// ------------------------------------------------------------------ 29.20 +// 29.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 29.22 +// 29.23 +// Permission: 29.24 +// 29.25 +// Lattice Semiconductor grants permission to use this code 29.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 29.27 +// Open Source License Agreement. 29.28 +// 29.29 +// Disclaimer: 29.30 // 29.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 29.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 29.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 29.34 -// U.S.A email: techsupport@latticesemi.com 29.35 -// =============================================================================/ 29.36 +// Lattice Semiconductor provides no warranty regarding the use or 29.37 +// functionality of this code. It is the user's responsibility to 29.38 +// verify the user’s design for consistency and functionality through 29.39 +// the use of formal verification methods. 29.40 +// 29.41 +// -------------------------------------------------------------------- 29.42 +// 29.43 +// Lattice Semiconductor Corporation 29.44 +// 5555 NE Moore Court 29.45 +// Hillsboro, OR 97214 29.46 +// U.S.A 29.47 +// 29.48 +// TEL: 1-800-Lattice (USA and Canada) 29.49 +// 503-286-8001 (other locations) 29.50 +// 29.51 +// web: http://www.latticesemi.com/ 29.52 +// email: techsupport@latticesemi.com 29.53 +// 29.54 +// -------------------------------------------------------------------- 29.55 // FILE DETAILS 29.56 // Project : LatticeMico32 29.57 // File : TYPEB.v 29.58 @@ -43,13 +64,13 @@ 29.59 always @ (negedge CLK or negedge RESET_N) 29.60 begin 29.61 if (RESET_N== 1'b0) 29.62 - tdoInt <= 1'b0; 29.63 + tdoInt <= #1 1'b0; 29.64 else if (CLK == 1'b0) 29.65 if (CLKEN==1'b1) 29.66 if (CAPTURE_DR==1'b0) 29.67 - tdoInt <= TDI; 29.68 + tdoInt <= #1 TDI; 29.69 else 29.70 - tdoInt <= DATA_IN; 29.71 + tdoInt <= #1 DATA_IN; 29.72 end 29.73 29.74 assign TDO = tdoInt;