Sat, 06 Aug 2011 01:26:56 +0100
remove synthesis delay entities to ease merge
| lm32_cpu.v | file | annotate | diff | revisions | |
| lm32_dcache.v | file | annotate | diff | revisions | |
| lm32_debug.v | file | annotate | diff | revisions | |
| lm32_icache.v | file | annotate | diff | revisions | |
| lm32_instruction_unit.v | file | annotate | diff | revisions | |
| lm32_interrupt.v | file | annotate | diff | revisions | |
| lm32_jtag.v | file | annotate | diff | revisions | |
| lm32_load_store_unit.v | file | annotate | diff | revisions | |
| lm32_mc_arithmetic.v | file | annotate | diff | revisions | |
| lm32_monitor.v | file | annotate | diff | revisions | |
| lm32_multiplier.v | file | annotate | diff | revisions | |
| lm32_ram.v | file | annotate | diff | revisions | |
| lm32_shifter.v | file | annotate | diff | revisions | |
| lm32_trace.v | file | annotate | diff | revisions | |
| typea.v | file | annotate | diff | revisions | |
| typeb.v | file | annotate | diff | revisions |
1.1 diff -r 73de224304c1 -r d6c693415d59 lm32_cpu.v 1.2 --- a/lm32_cpu.v Sat Aug 06 00:02:46 2011 +0100 1.3 +++ b/lm32_cpu.v Sat Aug 06 01:26:56 2011 +0100 1.4 @@ -1298,15 +1298,15 @@ 1.5 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.6 if (rst_i == `TRUE) 1.7 begin 1.8 - regfile_raw_0 <= #1 1'b0; 1.9 - regfile_raw_1 <= #1 1'b0; 1.10 - w_result_d <= #1 32'b0; 1.11 + regfile_raw_0 <= 1'b0; 1.12 + regfile_raw_1 <= 1'b0; 1.13 + w_result_d <= 32'b0; 1.14 end 1.15 else 1.16 begin 1.17 - regfile_raw_0 <= #1 regfile_raw_0_nxt; 1.18 - regfile_raw_1 <= #1 regfile_raw_1_nxt; 1.19 - w_result_d <= #1 w_result; 1.20 + regfile_raw_0 <= regfile_raw_0_nxt; 1.21 + regfile_raw_1 <= regfile_raw_1_nxt; 1.22 + w_result_d <= w_result; 1.23 end 1.24 1.25 /*---------------------------------------------------------------------- 1.26 @@ -2132,14 +2132,14 @@ 1.27 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.28 begin 1.29 if (rst_i == `TRUE) 1.30 - eba <= #1 eba_reset[`LM32_PC_WIDTH+2-1:8]; 1.31 + eba <= eba_reset[`LM32_PC_WIDTH+2-1:8]; 1.32 else 1.33 begin 1.34 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE)) 1.35 - eba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.36 + eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.37 `ifdef CFG_HW_DEBUG_ENABLED 1.38 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA)) 1.39 - eba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.40 + eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.41 `endif 1.42 end 1.43 end 1.44 @@ -2149,14 +2149,14 @@ 1.45 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.46 begin 1.47 if (rst_i == `TRUE) 1.48 - deba <= #1 deba_reset[`LM32_PC_WIDTH+2-1:8]; 1.49 + deba <= deba_reset[`LM32_PC_WIDTH+2-1:8]; 1.50 else 1.51 begin 1.52 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE)) 1.53 - deba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.54 + deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 1.55 `ifdef CFG_HW_DEBUG_ENABLED 1.56 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA)) 1.57 - deba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.58 + deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 1.59 `endif 1.60 end 1.61 end 1.62 @@ -2167,9 +2167,9 @@ 1.63 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.64 begin 1.65 if (rst_i == `TRUE) 1.66 - cc <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.67 + cc <= {`LM32_WORD_WIDTH{1'b0}}; 1.68 else 1.69 - cc <= #1 cc + 1'b1; 1.70 + cc <= cc + 1'b1; 1.71 end 1.72 `endif 1.73 1.74 @@ -2178,15 +2178,15 @@ 1.75 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.76 begin 1.77 if (rst_i == `TRUE) 1.78 - data_bus_error_seen <= #1 `FALSE; 1.79 + data_bus_error_seen <= `FALSE; 1.80 else 1.81 begin 1.82 // Set flag when bus error is detected 1.83 if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE)) 1.84 - data_bus_error_seen <= #1 `TRUE; 1.85 + data_bus_error_seen <= `TRUE; 1.86 // Clear flag when exception is taken 1.87 if ((exception_m == `TRUE) && (kill_m == `FALSE)) 1.88 - data_bus_error_seen <= #1 `FALSE; 1.89 + data_bus_error_seen <= `FALSE; 1.90 end 1.91 end 1.92 `endif 1.93 @@ -2237,48 +2237,48 @@ 1.94 begin 1.95 if (rst_i == `TRUE) 1.96 begin 1.97 - valid_f <= #1 `FALSE; 1.98 - valid_d <= #1 `FALSE; 1.99 - valid_x <= #1 `FALSE; 1.100 - valid_m <= #1 `FALSE; 1.101 - valid_w <= #1 `FALSE; 1.102 + valid_f <= `FALSE; 1.103 + valid_d <= `FALSE; 1.104 + valid_x <= `FALSE; 1.105 + valid_m <= `FALSE; 1.106 + valid_w <= `FALSE; 1.107 end 1.108 else 1.109 begin 1.110 if ((kill_f == `TRUE) || (stall_a == `FALSE)) 1.111 `ifdef LM32_CACHE_ENABLED 1.112 - valid_f <= #1 valid_a; 1.113 + valid_f <= valid_a; 1.114 `else 1.115 - valid_f <= #1 `TRUE; 1.116 + valid_f <= `TRUE; 1.117 `endif 1.118 else if (stall_f == `FALSE) 1.119 - valid_f <= #1 `FALSE; 1.120 + valid_f <= `FALSE; 1.121 1.122 if (kill_d == `TRUE) 1.123 - valid_d <= #1 `FALSE; 1.124 + valid_d <= `FALSE; 1.125 else if (stall_f == `FALSE) 1.126 - valid_d <= #1 valid_f & !kill_f; 1.127 + valid_d <= valid_f & !kill_f; 1.128 else if (stall_d == `FALSE) 1.129 - valid_d <= #1 `FALSE; 1.130 + valid_d <= `FALSE; 1.131 1.132 if (stall_d == `FALSE) 1.133 - valid_x <= #1 valid_d & !kill_d; 1.134 + valid_x <= valid_d & !kill_d; 1.135 else if (kill_x == `TRUE) 1.136 - valid_x <= #1 `FALSE; 1.137 + valid_x <= `FALSE; 1.138 else if (stall_x == `FALSE) 1.139 - valid_x <= #1 `FALSE; 1.140 + valid_x <= `FALSE; 1.141 1.142 if (kill_m == `TRUE) 1.143 - valid_m <= #1 `FALSE; 1.144 + valid_m <= `FALSE; 1.145 else if (stall_x == `FALSE) 1.146 - valid_m <= #1 valid_x & !kill_x; 1.147 + valid_m <= valid_x & !kill_x; 1.148 else if (stall_m == `FALSE) 1.149 - valid_m <= #1 `FALSE; 1.150 + valid_m <= `FALSE; 1.151 1.152 if (stall_m == `FALSE) 1.153 - valid_w <= #1 valid_m & !kill_m; 1.154 + valid_w <= valid_m & !kill_m; 1.155 else 1.156 - valid_w <= #1 `FALSE; 1.157 + valid_w <= `FALSE; 1.158 end 1.159 end 1.160 1.161 @@ -2288,113 +2288,113 @@ 1.162 if (rst_i == `TRUE) 1.163 begin 1.164 `ifdef CFG_USER_ENABLED 1.165 - user_opcode <= #1 {`LM32_USER_OPCODE_WIDTH{1'b0}}; 1.166 + user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}}; 1.167 `endif 1.168 - operand_0_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.169 - operand_1_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.170 - store_operand_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.171 - branch_target_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.172 - x_result_sel_csr_x <= #1 `FALSE; 1.173 + operand_0_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.174 + operand_1_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.175 + store_operand_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.176 + branch_target_x <= {`LM32_WORD_WIDTH{1'b0}}; 1.177 + x_result_sel_csr_x <= `FALSE; 1.178 `ifdef LM32_MC_ARITHMETIC_ENABLED 1.179 - x_result_sel_mc_arith_x <= #1 `FALSE; 1.180 + x_result_sel_mc_arith_x <= `FALSE; 1.181 `endif 1.182 `ifdef LM32_NO_BARREL_SHIFT 1.183 - x_result_sel_shift_x <= #1 `FALSE; 1.184 + x_result_sel_shift_x <= `FALSE; 1.185 `endif 1.186 `ifdef CFG_SIGN_EXTEND_ENABLED 1.187 - x_result_sel_sext_x <= #1 `FALSE; 1.188 + x_result_sel_sext_x <= `FALSE; 1.189 `endif 1.190 - x_result_sel_logic_x <= #1 `FALSE; 1.191 + x_result_sel_logic_x <= `FALSE; 1.192 `ifdef CFG_USER_ENABLED 1.193 - x_result_sel_user_x <= #1 `FALSE; 1.194 + x_result_sel_user_x <= `FALSE; 1.195 `endif 1.196 - x_result_sel_add_x <= #1 `FALSE; 1.197 - m_result_sel_compare_x <= #1 `FALSE; 1.198 + x_result_sel_add_x <= `FALSE; 1.199 + m_result_sel_compare_x <= `FALSE; 1.200 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.201 - m_result_sel_shift_x <= #1 `FALSE; 1.202 + m_result_sel_shift_x <= `FALSE; 1.203 `endif 1.204 - w_result_sel_load_x <= #1 `FALSE; 1.205 + w_result_sel_load_x <= `FALSE; 1.206 `ifdef CFG_PL_MULTIPLY_ENABLED 1.207 - w_result_sel_mul_x <= #1 `FALSE; 1.208 + w_result_sel_mul_x <= `FALSE; 1.209 `endif 1.210 - x_bypass_enable_x <= #1 `FALSE; 1.211 - m_bypass_enable_x <= #1 `FALSE; 1.212 - write_enable_x <= #1 `FALSE; 1.213 - write_idx_x <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 1.214 - csr_x <= #1 {`LM32_CSR_WIDTH{1'b0}}; 1.215 - load_x <= #1 `FALSE; 1.216 - store_x <= #1 `FALSE; 1.217 - size_x <= #1 {`LM32_SIZE_WIDTH{1'b0}}; 1.218 - sign_extend_x <= #1 `FALSE; 1.219 - adder_op_x <= #1 `FALSE; 1.220 - adder_op_x_n <= #1 `FALSE; 1.221 - logic_op_x <= #1 4'h0; 1.222 + x_bypass_enable_x <= `FALSE; 1.223 + m_bypass_enable_x <= `FALSE; 1.224 + write_enable_x <= `FALSE; 1.225 + write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.226 + csr_x <= {`LM32_CSR_WIDTH{1'b0}}; 1.227 + load_x <= `FALSE; 1.228 + store_x <= `FALSE; 1.229 + size_x <= {`LM32_SIZE_WIDTH{1'b0}}; 1.230 + sign_extend_x <= `FALSE; 1.231 + adder_op_x <= `FALSE; 1.232 + adder_op_x_n <= `FALSE; 1.233 + logic_op_x <= 4'h0; 1.234 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.235 - direction_x <= #1 `FALSE; 1.236 + direction_x <= `FALSE; 1.237 `endif 1.238 `ifdef CFG_ROTATE_ENABLED 1.239 - rotate_x <= #1 `FALSE; 1.240 + rotate_x <= `FALSE; 1.241 1.242 `endif 1.243 - branch_x <= #1 `FALSE; 1.244 - branch_predict_x <= #1 `FALSE; 1.245 - branch_predict_taken_x <= #1 `FALSE; 1.246 - condition_x <= #1 `LM32_CONDITION_U1; 1.247 + branch_x <= `FALSE; 1.248 + branch_predict_x <= `FALSE; 1.249 + branch_predict_taken_x <= `FALSE; 1.250 + condition_x <= `LM32_CONDITION_U1; 1.251 `ifdef CFG_DEBUG_ENABLED 1.252 - break_x <= #1 `FALSE; 1.253 + break_x <= `FALSE; 1.254 `endif 1.255 - scall_x <= #1 `FALSE; 1.256 - eret_x <= #1 `FALSE; 1.257 + scall_x <= `FALSE; 1.258 + eret_x <= `FALSE; 1.259 `ifdef CFG_DEBUG_ENABLED 1.260 - bret_x <= #1 `FALSE; 1.261 + bret_x <= `FALSE; 1.262 `endif 1.263 `ifdef CFG_BUS_ERRORS_ENABLED 1.264 - bus_error_x <= #1 `FALSE; 1.265 - data_bus_error_exception_m <= #1 `FALSE; 1.266 + bus_error_x <= `FALSE; 1.267 + data_bus_error_exception_m <= `FALSE; 1.268 `endif 1.269 - csr_write_enable_x <= #1 `FALSE; 1.270 - operand_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.271 - branch_target_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.272 - m_result_sel_compare_m <= #1 `FALSE; 1.273 + csr_write_enable_x <= `FALSE; 1.274 + operand_m <= {`LM32_WORD_WIDTH{1'b0}}; 1.275 + branch_target_m <= {`LM32_WORD_WIDTH{1'b0}}; 1.276 + m_result_sel_compare_m <= `FALSE; 1.277 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.278 - m_result_sel_shift_m <= #1 `FALSE; 1.279 + m_result_sel_shift_m <= `FALSE; 1.280 `endif 1.281 - w_result_sel_load_m <= #1 `FALSE; 1.282 + w_result_sel_load_m <= `FALSE; 1.283 `ifdef CFG_PL_MULTIPLY_ENABLED 1.284 - w_result_sel_mul_m <= #1 `FALSE; 1.285 + w_result_sel_mul_m <= `FALSE; 1.286 `endif 1.287 - m_bypass_enable_m <= #1 `FALSE; 1.288 - branch_m <= #1 `FALSE; 1.289 - branch_predict_m <= #1 `FALSE; 1.290 - branch_predict_taken_m <= #1 `FALSE; 1.291 - exception_m <= #1 `FALSE; 1.292 - load_m <= #1 `FALSE; 1.293 - store_m <= #1 `FALSE; 1.294 - write_enable_m <= #1 `FALSE; 1.295 - write_idx_m <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 1.296 - condition_met_m <= #1 `FALSE; 1.297 + m_bypass_enable_m <= `FALSE; 1.298 + branch_m <= `FALSE; 1.299 + branch_predict_m <= `FALSE; 1.300 + branch_predict_taken_m <= `FALSE; 1.301 + exception_m <= `FALSE; 1.302 + load_m <= `FALSE; 1.303 + store_m <= `FALSE; 1.304 + write_enable_m <= `FALSE; 1.305 + write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.306 + condition_met_m <= `FALSE; 1.307 `ifdef CFG_DCACHE_ENABLED 1.308 - dflush_m <= #1 `FALSE; 1.309 + dflush_m <= `FALSE; 1.310 `endif 1.311 `ifdef CFG_DEBUG_ENABLED 1.312 - debug_exception_m <= #1 `FALSE; 1.313 - non_debug_exception_m <= #1 `FALSE; 1.314 + debug_exception_m <= `FALSE; 1.315 + non_debug_exception_m <= `FALSE; 1.316 `endif 1.317 - operand_w <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.318 - w_result_sel_load_w <= #1 `FALSE; 1.319 + operand_w <= {`LM32_WORD_WIDTH{1'b0}}; 1.320 + w_result_sel_load_w <= `FALSE; 1.321 `ifdef CFG_PL_MULTIPLY_ENABLED 1.322 - w_result_sel_mul_w <= #1 `FALSE; 1.323 + w_result_sel_mul_w <= `FALSE; 1.324 `endif 1.325 - write_idx_w <= #1 {`LM32_REG_IDX_WIDTH{1'b0}}; 1.326 - write_enable_w <= #1 `FALSE; 1.327 + write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}}; 1.328 + write_enable_w <= `FALSE; 1.329 `ifdef CFG_DEBUG_ENABLED 1.330 - debug_exception_w <= #1 `FALSE; 1.331 - non_debug_exception_w <= #1 `FALSE; 1.332 + debug_exception_w <= `FALSE; 1.333 + non_debug_exception_w <= `FALSE; 1.334 `else 1.335 - exception_w <= #1 `FALSE; 1.336 + exception_w <= `FALSE; 1.337 `endif 1.338 `ifdef CFG_BUS_ERRORS_ENABLED 1.339 - memop_pc_w <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.340 + memop_pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.341 `endif 1.342 end 1.343 else 1.344 @@ -2404,105 +2404,105 @@ 1.345 if (stall_x == `FALSE) 1.346 begin 1.347 `ifdef CFG_USER_ENABLED 1.348 - user_opcode <= #1 user_opcode_d; 1.349 + user_opcode <= user_opcode_d; 1.350 `endif 1.351 - operand_0_x <= #1 d_result_0; 1.352 - operand_1_x <= #1 d_result_1; 1.353 - store_operand_x <= #1 bypass_data_1; 1.354 - branch_target_x <= #1 branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 1.355 - x_result_sel_csr_x <= #1 x_result_sel_csr_d; 1.356 + operand_0_x <= d_result_0; 1.357 + operand_1_x <= d_result_1; 1.358 + store_operand_x <= bypass_data_1; 1.359 + branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 1.360 + x_result_sel_csr_x <= x_result_sel_csr_d; 1.361 `ifdef LM32_MC_ARITHMETIC_ENABLED 1.362 - x_result_sel_mc_arith_x <= #1 x_result_sel_mc_arith_d; 1.363 + x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d; 1.364 `endif 1.365 `ifdef LM32_NO_BARREL_SHIFT 1.366 - x_result_sel_shift_x <= #1 x_result_sel_shift_d; 1.367 + x_result_sel_shift_x <= x_result_sel_shift_d; 1.368 `endif 1.369 `ifdef CFG_SIGN_EXTEND_ENABLED 1.370 - x_result_sel_sext_x <= #1 x_result_sel_sext_d; 1.371 + x_result_sel_sext_x <= x_result_sel_sext_d; 1.372 `endif 1.373 - x_result_sel_logic_x <= #1 x_result_sel_logic_d; 1.374 + x_result_sel_logic_x <= x_result_sel_logic_d; 1.375 `ifdef CFG_USER_ENABLED 1.376 - x_result_sel_user_x <= #1 x_result_sel_user_d; 1.377 + x_result_sel_user_x <= x_result_sel_user_d; 1.378 `endif 1.379 - x_result_sel_add_x <= #1 x_result_sel_add_d; 1.380 - m_result_sel_compare_x <= #1 m_result_sel_compare_d; 1.381 + x_result_sel_add_x <= x_result_sel_add_d; 1.382 + m_result_sel_compare_x <= m_result_sel_compare_d; 1.383 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.384 - m_result_sel_shift_x <= #1 m_result_sel_shift_d; 1.385 + m_result_sel_shift_x <= m_result_sel_shift_d; 1.386 `endif 1.387 - w_result_sel_load_x <= #1 w_result_sel_load_d; 1.388 + w_result_sel_load_x <= w_result_sel_load_d; 1.389 `ifdef CFG_PL_MULTIPLY_ENABLED 1.390 - w_result_sel_mul_x <= #1 w_result_sel_mul_d; 1.391 + w_result_sel_mul_x <= w_result_sel_mul_d; 1.392 `endif 1.393 - x_bypass_enable_x <= #1 x_bypass_enable_d; 1.394 - m_bypass_enable_x <= #1 m_bypass_enable_d; 1.395 - load_x <= #1 load_d; 1.396 - store_x <= #1 store_d; 1.397 - branch_x <= #1 branch_d; 1.398 - branch_predict_x <= #1 branch_predict_d; 1.399 - branch_predict_taken_x <= #1 branch_predict_taken_d; 1.400 - write_idx_x <= #1 write_idx_d; 1.401 - csr_x <= #1 csr_d; 1.402 - size_x <= #1 size_d; 1.403 - sign_extend_x <= #1 sign_extend_d; 1.404 - adder_op_x <= #1 adder_op_d; 1.405 - adder_op_x_n <= #1 ~adder_op_d; 1.406 - logic_op_x <= #1 logic_op_d; 1.407 + x_bypass_enable_x <= x_bypass_enable_d; 1.408 + m_bypass_enable_x <= m_bypass_enable_d; 1.409 + load_x <= load_d; 1.410 + store_x <= store_d; 1.411 + branch_x <= branch_d; 1.412 + branch_predict_x <= branch_predict_d; 1.413 + branch_predict_taken_x <= branch_predict_taken_d; 1.414 + write_idx_x <= write_idx_d; 1.415 + csr_x <= csr_d; 1.416 + size_x <= size_d; 1.417 + sign_extend_x <= sign_extend_d; 1.418 + adder_op_x <= adder_op_d; 1.419 + adder_op_x_n <= ~adder_op_d; 1.420 + logic_op_x <= logic_op_d; 1.421 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.422 - direction_x <= #1 direction_d; 1.423 + direction_x <= direction_d; 1.424 `endif 1.425 `ifdef CFG_ROTATE_ENABLED 1.426 - rotate_x <= #1 rotate_d; 1.427 + rotate_x <= rotate_d; 1.428 `endif 1.429 - condition_x <= #1 condition_d; 1.430 - csr_write_enable_x <= #1 csr_write_enable_d; 1.431 + condition_x <= condition_d; 1.432 + csr_write_enable_x <= csr_write_enable_d; 1.433 `ifdef CFG_DEBUG_ENABLED 1.434 - break_x <= #1 break_d; 1.435 + break_x <= break_d; 1.436 `endif 1.437 - scall_x <= #1 scall_d; 1.438 + scall_x <= scall_d; 1.439 `ifdef CFG_BUS_ERRORS_ENABLED 1.440 - bus_error_x <= #1 bus_error_d; 1.441 + bus_error_x <= bus_error_d; 1.442 `endif 1.443 - eret_x <= #1 eret_d; 1.444 + eret_x <= eret_d; 1.445 `ifdef CFG_DEBUG_ENABLED 1.446 - bret_x <= #1 bret_d; 1.447 + bret_x <= bret_d; 1.448 `endif 1.449 - write_enable_x <= #1 write_enable_d; 1.450 + write_enable_x <= write_enable_d; 1.451 end 1.452 1.453 // X/M stage registers 1.454 1.455 if (stall_m == `FALSE) 1.456 begin 1.457 - operand_m <= #1 x_result; 1.458 - m_result_sel_compare_m <= #1 m_result_sel_compare_x; 1.459 + operand_m <= x_result; 1.460 + m_result_sel_compare_m <= m_result_sel_compare_x; 1.461 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.462 - m_result_sel_shift_m <= #1 m_result_sel_shift_x; 1.463 + m_result_sel_shift_m <= m_result_sel_shift_x; 1.464 `endif 1.465 if (exception_x == `TRUE) 1.466 begin 1.467 - w_result_sel_load_m <= #1 `FALSE; 1.468 + w_result_sel_load_m <= `FALSE; 1.469 `ifdef CFG_PL_MULTIPLY_ENABLED 1.470 - w_result_sel_mul_m <= #1 `FALSE; 1.471 + w_result_sel_mul_m <= `FALSE; 1.472 `endif 1.473 end 1.474 else 1.475 begin 1.476 - w_result_sel_load_m <= #1 w_result_sel_load_x; 1.477 + w_result_sel_load_m <= w_result_sel_load_x; 1.478 `ifdef CFG_PL_MULTIPLY_ENABLED 1.479 - w_result_sel_mul_m <= #1 w_result_sel_mul_x; 1.480 + w_result_sel_mul_m <= w_result_sel_mul_x; 1.481 `endif 1.482 end 1.483 - m_bypass_enable_m <= #1 m_bypass_enable_x; 1.484 + m_bypass_enable_m <= m_bypass_enable_x; 1.485 `ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.486 `endif 1.487 - load_m <= #1 load_x; 1.488 - store_m <= #1 store_x; 1.489 + load_m <= load_x; 1.490 + store_m <= store_x; 1.491 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.492 - branch_m <= #1 branch_x && !branch_taken_x; 1.493 + branch_m <= branch_x && !branch_taken_x; 1.494 `else 1.495 - branch_m <= #1 branch_x; 1.496 - branch_predict_m <= #1 branch_predict_x; 1.497 - branch_predict_taken_m <= #1 branch_predict_taken_x; 1.498 + branch_m <= branch_x; 1.499 + branch_predict_m <= branch_predict_x; 1.500 + branch_predict_taken_m <= branch_predict_taken_x; 1.501 `endif 1.502 `ifdef CFG_DEBUG_ENABLED 1.503 // Data bus errors are generated by the wishbone and are 1.504 @@ -2511,18 +2511,18 @@ 1.505 // in same cycle (causing a debug exception). Handle non 1.506 // -debug exception first! 1.507 if (non_debug_exception_x == `TRUE) 1.508 - write_idx_m <= #1 `LM32_EA_REG; 1.509 + write_idx_m <= `LM32_EA_REG; 1.510 else if (debug_exception_x == `TRUE) 1.511 - write_idx_m <= #1 `LM32_BA_REG; 1.512 + write_idx_m <= `LM32_BA_REG; 1.513 else 1.514 - write_idx_m <= #1 write_idx_x; 1.515 + write_idx_m <= write_idx_x; 1.516 `else 1.517 if (exception_x == `TRUE) 1.518 - write_idx_m <= #1 `LM32_EA_REG; 1.519 + write_idx_m <= `LM32_EA_REG; 1.520 else 1.521 - write_idx_m <= #1 write_idx_x; 1.522 + write_idx_m <= write_idx_x; 1.523 `endif 1.524 - condition_met_m <= #1 condition_met_x; 1.525 + condition_met_m <= condition_met_x; 1.526 `ifdef CFG_DEBUG_ENABLED 1.527 if (exception_x == `TRUE) 1.528 if ((dc_re == `TRUE) 1.529 @@ -2531,28 +2531,28 @@ 1.530 `endif 1.531 || ((debug_exception_x == `TRUE) 1.532 && (non_debug_exception_x == `FALSE))) 1.533 - branch_target_m <= #1 {deba, eid_x, {3{1'b0}}}; 1.534 + branch_target_m <= {deba, eid_x, {3{1'b0}}}; 1.535 else 1.536 - branch_target_m <= #1 {eba, eid_x, {3{1'b0}}}; 1.537 + branch_target_m <= {eba, eid_x, {3{1'b0}}}; 1.538 else 1.539 - branch_target_m <= #1 branch_target_x; 1.540 + branch_target_m <= branch_target_x; 1.541 `else 1.542 - branch_target_m <= #1 exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 1.543 + branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 1.544 `endif 1.545 `ifdef CFG_TRACE_ENABLED 1.546 - eid_m <= #1 eid_x; 1.547 + eid_m <= eid_x; 1.548 `endif 1.549 `ifdef CFG_DCACHE_ENABLED 1.550 - dflush_m <= #1 dflush_x; 1.551 + dflush_m <= dflush_x; 1.552 `endif 1.553 - eret_m <= #1 eret_q_x; 1.554 + eret_m <= eret_q_x; 1.555 `ifdef CFG_DEBUG_ENABLED 1.556 - bret_m <= #1 bret_q_x; 1.557 + bret_m <= bret_q_x; 1.558 `endif 1.559 - write_enable_m <= #1 exception_x == `TRUE ? `TRUE : write_enable_x; 1.560 + write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x; 1.561 `ifdef CFG_DEBUG_ENABLED 1.562 - debug_exception_m <= #1 debug_exception_x; 1.563 - non_debug_exception_m <= #1 non_debug_exception_x; 1.564 + debug_exception_m <= debug_exception_x; 1.565 + non_debug_exception_m <= non_debug_exception_x; 1.566 `endif 1.567 end 1.568 1.569 @@ -2560,11 +2560,11 @@ 1.570 if (stall_m == `FALSE) 1.571 begin 1.572 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 1.573 - exception_m <= #1 `TRUE; 1.574 + exception_m <= `TRUE; 1.575 else 1.576 - exception_m <= #1 `FALSE; 1.577 + exception_m <= `FALSE; 1.578 `ifdef CFG_BUS_ERRORS_ENABLED 1.579 - data_bus_error_exception_m <= #1 (data_bus_error_exception == `TRUE) 1.580 + data_bus_error_exception_m <= (data_bus_error_exception == `TRUE) 1.581 `ifdef CFG_DEBUG_ENABLED 1.582 && (reset_exception == `FALSE) 1.583 `endif 1.584 @@ -2574,28 +2574,28 @@ 1.585 1.586 // M/W stage registers 1.587 `ifdef CFG_BUS_ERRORS_ENABLED 1.588 - operand_w <= #1 exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 1.589 + operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 1.590 `else 1.591 - operand_w <= #1 exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 1.592 + operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 1.593 `endif 1.594 - w_result_sel_load_w <= #1 w_result_sel_load_m; 1.595 + w_result_sel_load_w <= w_result_sel_load_m; 1.596 `ifdef CFG_PL_MULTIPLY_ENABLED 1.597 - w_result_sel_mul_w <= #1 w_result_sel_mul_m; 1.598 + w_result_sel_mul_w <= w_result_sel_mul_m; 1.599 `endif 1.600 - write_idx_w <= #1 write_idx_m; 1.601 + write_idx_w <= write_idx_m; 1.602 `ifdef CFG_TRACE_ENABLED 1.603 - eid_w <= #1 eid_m; 1.604 - eret_w <= #1 eret_m; 1.605 + eid_w <= eid_m; 1.606 + eret_w <= eret_m; 1.607 `ifdef CFG_DEBUG_ENABLED 1.608 - bret_w <= #1 bret_m; 1.609 + bret_w <= bret_m; 1.610 `endif 1.611 `endif 1.612 - write_enable_w <= #1 write_enable_m; 1.613 + write_enable_w <= write_enable_m; 1.614 `ifdef CFG_DEBUG_ENABLED 1.615 - debug_exception_w <= #1 debug_exception_m; 1.616 - non_debug_exception_w <= #1 non_debug_exception_m; 1.617 + debug_exception_w <= debug_exception_m; 1.618 + non_debug_exception_w <= non_debug_exception_m; 1.619 `else 1.620 - exception_w <= #1 exception_m; 1.621 + exception_w <= exception_m; 1.622 `endif 1.623 `ifdef CFG_BUS_ERRORS_ENABLED 1.624 if ( (stall_m == `FALSE) 1.625 @@ -2604,7 +2604,7 @@ 1.626 || (store_q_m == `TRUE) 1.627 ) 1.628 ) 1.629 - memop_pc_w <= #1 pc_m; 1.630 + memop_pc_w <= pc_m; 1.631 `endif 1.632 end 1.633 end 1.634 @@ -2616,26 +2616,26 @@ 1.635 begin 1.636 if (rst_i == `TRUE) 1.637 begin 1.638 - use_buf <= #1 `FALSE; 1.639 - reg_data_buf_0 <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.640 - reg_data_buf_1 <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.641 + use_buf <= `FALSE; 1.642 + reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}}; 1.643 + reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}}; 1.644 end 1.645 else 1.646 begin 1.647 if (stall_d == `FALSE) 1.648 - use_buf <= #1 `FALSE; 1.649 + use_buf <= `FALSE; 1.650 else if (use_buf == `FALSE) 1.651 begin 1.652 - reg_data_buf_0 <= #1 reg_data_live_0; 1.653 - reg_data_buf_1 <= #1 reg_data_live_1; 1.654 - use_buf <= #1 `TRUE; 1.655 + reg_data_buf_0 <= reg_data_live_0; 1.656 + reg_data_buf_1 <= reg_data_live_1; 1.657 + use_buf <= `TRUE; 1.658 end 1.659 if (reg_write_enable_q_w == `TRUE) 1.660 begin 1.661 if (write_idx_w == read_idx_0_d) 1.662 - reg_data_buf_0 <= #1 w_result; 1.663 + reg_data_buf_0 <= w_result; 1.664 if (write_idx_w == read_idx_1_d) 1.665 - reg_data_buf_1 <= #1 w_result; 1.666 + reg_data_buf_1 <= w_result; 1.667 end 1.668 end 1.669 end 1.670 @@ -2647,42 +2647,42 @@ 1.671 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.672 begin 1.673 if (rst_i == `TRUE) begin 1.674 - registers[0] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.675 - registers[1] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.676 - registers[2] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.677 - registers[3] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.678 - registers[4] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.679 - registers[5] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.680 - registers[6] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.681 - registers[7] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.682 - registers[8] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.683 - registers[9] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.684 - registers[10] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.685 - registers[11] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.686 - registers[12] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.687 - registers[13] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.688 - registers[14] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.689 - registers[15] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.690 - registers[16] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.691 - registers[17] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.692 - registers[18] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.693 - registers[19] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.694 - registers[20] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.695 - registers[21] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.696 - registers[22] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.697 - registers[23] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.698 - registers[24] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.699 - registers[25] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.700 - registers[26] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.701 - registers[27] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.702 - registers[28] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.703 - registers[29] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.704 - registers[30] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.705 - registers[31] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.706 + registers[0] <= {`LM32_WORD_WIDTH{1'b0}}; 1.707 + registers[1] <= {`LM32_WORD_WIDTH{1'b0}}; 1.708 + registers[2] <= {`LM32_WORD_WIDTH{1'b0}}; 1.709 + registers[3] <= {`LM32_WORD_WIDTH{1'b0}}; 1.710 + registers[4] <= {`LM32_WORD_WIDTH{1'b0}}; 1.711 + registers[5] <= {`LM32_WORD_WIDTH{1'b0}}; 1.712 + registers[6] <= {`LM32_WORD_WIDTH{1'b0}}; 1.713 + registers[7] <= {`LM32_WORD_WIDTH{1'b0}}; 1.714 + registers[8] <= {`LM32_WORD_WIDTH{1'b0}}; 1.715 + registers[9] <= {`LM32_WORD_WIDTH{1'b0}}; 1.716 + registers[10] <= {`LM32_WORD_WIDTH{1'b0}}; 1.717 + registers[11] <= {`LM32_WORD_WIDTH{1'b0}}; 1.718 + registers[12] <= {`LM32_WORD_WIDTH{1'b0}}; 1.719 + registers[13] <= {`LM32_WORD_WIDTH{1'b0}}; 1.720 + registers[14] <= {`LM32_WORD_WIDTH{1'b0}}; 1.721 + registers[15] <= {`LM32_WORD_WIDTH{1'b0}}; 1.722 + registers[16] <= {`LM32_WORD_WIDTH{1'b0}}; 1.723 + registers[17] <= {`LM32_WORD_WIDTH{1'b0}}; 1.724 + registers[18] <= {`LM32_WORD_WIDTH{1'b0}}; 1.725 + registers[19] <= {`LM32_WORD_WIDTH{1'b0}}; 1.726 + registers[20] <= {`LM32_WORD_WIDTH{1'b0}}; 1.727 + registers[21] <= {`LM32_WORD_WIDTH{1'b0}}; 1.728 + registers[22] <= {`LM32_WORD_WIDTH{1'b0}}; 1.729 + registers[23] <= {`LM32_WORD_WIDTH{1'b0}}; 1.730 + registers[24] <= {`LM32_WORD_WIDTH{1'b0}}; 1.731 + registers[25] <= {`LM32_WORD_WIDTH{1'b0}}; 1.732 + registers[26] <= {`LM32_WORD_WIDTH{1'b0}}; 1.733 + registers[27] <= {`LM32_WORD_WIDTH{1'b0}}; 1.734 + registers[28] <= {`LM32_WORD_WIDTH{1'b0}}; 1.735 + registers[29] <= {`LM32_WORD_WIDTH{1'b0}}; 1.736 + registers[30] <= {`LM32_WORD_WIDTH{1'b0}}; 1.737 + registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 1.738 end 1.739 else begin 1.740 if (reg_write_enable_q_w == `TRUE) 1.741 - registers[write_idx_w] <= #1 w_result; 1.742 + registers[write_idx_w] <= w_result; 1.743 end 1.744 end 1.745 `endif 1.746 @@ -2693,19 +2693,19 @@ 1.747 begin 1.748 if (rst_i == `TRUE) 1.749 begin 1.750 - trace_pc_valid <= #1 `FALSE; 1.751 - trace_pc <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.752 - trace_exception <= #1 `FALSE; 1.753 - trace_eid <= #1 `LM32_EID_RESET; 1.754 - trace_eret <= #1 `FALSE; 1.755 + trace_pc_valid <= `FALSE; 1.756 + trace_pc <= {`LM32_PC_WIDTH{1'b0}}; 1.757 + trace_exception <= `FALSE; 1.758 + trace_eid <= `LM32_EID_RESET; 1.759 + trace_eret <= `FALSE; 1.760 `ifdef CFG_DEBUG_ENABLED 1.761 - trace_bret <= #1 `FALSE; 1.762 + trace_bret <= `FALSE; 1.763 `endif 1.764 - pc_c <= #1 `CFG_EBA_RESET/4; 1.765 + pc_c <= `CFG_EBA_RESET/4; 1.766 end 1.767 else 1.768 begin 1.769 - trace_pc_valid <= #1 `FALSE; 1.770 + trace_pc_valid <= `FALSE; 1.771 // Has an exception occured 1.772 `ifdef CFG_DEBUG_ENABLED 1.773 if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE)) 1.774 @@ -2713,13 +2713,13 @@ 1.775 if (exception_q_w == `TRUE) 1.776 `endif 1.777 begin 1.778 - trace_exception <= #1 `TRUE; 1.779 - trace_pc_valid <= #1 `TRUE; 1.780 - trace_pc <= #1 pc_w; 1.781 - trace_eid <= #1 eid_w; 1.782 + trace_exception <= `TRUE; 1.783 + trace_pc_valid <= `TRUE; 1.784 + trace_pc <= pc_w; 1.785 + trace_eid <= eid_w; 1.786 end 1.787 else 1.788 - trace_exception <= #1 `FALSE; 1.789 + trace_exception <= `FALSE; 1.790 1.791 if ((valid_w == `TRUE) && (!kill_w)) 1.792 begin 1.793 @@ -2727,22 +2727,22 @@ 1.794 if (pc_c + 1'b1 != pc_w) 1.795 begin 1.796 // Non-sequential instruction 1.797 - trace_pc_valid <= #1 `TRUE; 1.798 - trace_pc <= #1 pc_w; 1.799 + trace_pc_valid <= `TRUE; 1.800 + trace_pc <= pc_w; 1.801 end 1.802 // Record PC so we can determine if next instruction is sequential or not 1.803 - pc_c <= #1 pc_w; 1.804 + pc_c <= pc_w; 1.805 // Indicate if it was an eret/bret instruction 1.806 - trace_eret <= #1 eret_w; 1.807 + trace_eret <= eret_w; 1.808 `ifdef CFG_DEBUG_ENABLED 1.809 - trace_bret <= #1 bret_w; 1.810 + trace_bret <= bret_w; 1.811 `endif 1.812 end 1.813 else 1.814 begin 1.815 - trace_eret <= #1 `FALSE; 1.816 + trace_eret <= `FALSE; 1.817 `ifdef CFG_DEBUG_ENABLED 1.818 - trace_bret <= #1 `FALSE; 1.819 + trace_bret <= `FALSE; 1.820 `endif 1.821 end 1.822 end
2.1 diff -r 73de224304c1 -r d6c693415d59 lm32_dcache.v 2.2 --- a/lm32_dcache.v Sat Aug 06 00:02:46 2011 +0100 2.3 +++ b/lm32_dcache.v Sat Aug 06 01:26:56 2011 +0100 2.4 @@ -441,11 +441,11 @@ 2.5 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 2.6 begin 2.7 if (rst_i == `TRUE) 2.8 - refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1}; 2.9 + refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 2.10 else 2.11 begin 2.12 if (refill_request == `TRUE) 2.13 - refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]}; 2.14 + refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 2.15 end 2.16 end 2.17 end 2.18 @@ -455,9 +455,9 @@ 2.19 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 2.20 begin 2.21 if (rst_i == `TRUE) 2.22 - refilling <= #1 `FALSE; 2.23 + refilling <= `FALSE; 2.24 else 2.25 - refilling <= #1 refill; 2.26 + refilling <= refill; 2.27 end 2.28 2.29 // Instruction cache control FSM 2.30 @@ -465,11 +465,11 @@ 2.31 begin 2.32 if (rst_i == `TRUE) 2.33 begin 2.34 - state <= #1 `LM32_DC_STATE_FLUSH; 2.35 - flush_set <= #1 {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 2.36 - refill_request <= #1 `FALSE; 2.37 - refill_address <= #1 {`LM32_WORD_WIDTH{1'bx}}; 2.38 - restart_request <= #1 `FALSE; 2.39 + state <= `LM32_DC_STATE_FLUSH; 2.40 + flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 2.41 + refill_request <= `FALSE; 2.42 + refill_address <= {`LM32_WORD_WIDTH{1'bx}}; 2.43 + restart_request <= `FALSE; 2.44 end 2.45 else 2.46 begin 2.47 @@ -479,35 +479,35 @@ 2.48 `LM32_DC_STATE_FLUSH: 2.49 begin 2.50 if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}}) 2.51 - state <= #1 `LM32_DC_STATE_CHECK; 2.52 - flush_set <= #1 flush_set - 1'b1; 2.53 + state <= `LM32_DC_STATE_CHECK; 2.54 + flush_set <= flush_set - 1'b1; 2.55 end 2.56 2.57 // Check for cache misses 2.58 `LM32_DC_STATE_CHECK: 2.59 begin 2.60 if (stall_a == `FALSE) 2.61 - restart_request <= #1 `FALSE; 2.62 + restart_request <= `FALSE; 2.63 if (miss == `TRUE) 2.64 begin 2.65 - refill_request <= #1 `TRUE; 2.66 - refill_address <= #1 address_m; 2.67 - state <= #1 `LM32_DC_STATE_REFILL; 2.68 + refill_request <= `TRUE; 2.69 + refill_address <= address_m; 2.70 + state <= `LM32_DC_STATE_REFILL; 2.71 end 2.72 else if (dflush == `TRUE) 2.73 - state <= #1 `LM32_DC_STATE_FLUSH; 2.74 + state <= `LM32_DC_STATE_FLUSH; 2.75 end 2.76 2.77 // Refill a cache line 2.78 `LM32_DC_STATE_REFILL: 2.79 begin 2.80 - refill_request <= #1 `FALSE; 2.81 + refill_request <= `FALSE; 2.82 if (refill_ready == `TRUE) 2.83 begin 2.84 if (last_refill == `TRUE) 2.85 begin 2.86 - restart_request <= #1 `TRUE; 2.87 - state <= #1 `LM32_DC_STATE_CHECK; 2.88 + restart_request <= `TRUE; 2.89 + state <= `LM32_DC_STATE_CHECK; 2.90 end 2.91 end 2.92 end 2.93 @@ -523,7 +523,7 @@ 2.94 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 2.95 begin 2.96 if (rst_i == `TRUE) 2.97 - refill_offset <= #1 {addr_offset_width{1'b0}}; 2.98 + refill_offset <= {addr_offset_width{1'b0}}; 2.99 else 2.100 begin 2.101 case (state) 2.102 @@ -532,14 +532,14 @@ 2.103 `LM32_DC_STATE_CHECK: 2.104 begin 2.105 if (miss == `TRUE) 2.106 - refill_offset <= #1 {addr_offset_width{1'b0}}; 2.107 + refill_offset <= {addr_offset_width{1'b0}}; 2.108 end 2.109 2.110 // Refill a cache line 2.111 `LM32_DC_STATE_REFILL: 2.112 begin 2.113 if (refill_ready == `TRUE) 2.114 - refill_offset <= #1 refill_offset + 1'b1; 2.115 + refill_offset <= refill_offset + 1'b1; 2.116 end 2.117 2.118 endcase
3.1 diff -r 73de224304c1 -r d6c693415d59 lm32_debug.v 3.2 --- a/lm32_debug.v Sat Aug 06 00:02:46 2011 +0100 3.3 +++ b/lm32_debug.v Sat Aug 06 01:26:56 2011 +0100 3.4 @@ -247,15 +247,15 @@ 3.5 begin 3.6 if (rst_i == `TRUE) 3.7 begin 3.8 - bp_a[i] <= #1 {`LM32_PC_WIDTH{1'bx}}; 3.9 - bp_e[i] <= #1 `FALSE; 3.10 + bp_a[i] <= {`LM32_PC_WIDTH{1'bx}}; 3.11 + bp_e[i] <= `FALSE; 3.12 end 3.13 else 3.14 begin 3.15 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i)) 3.16 begin 3.17 - bp_a[i] <= #1 debug_csr_write_data[`LM32_PC_RNG]; 3.18 - bp_e[i] <= #1 debug_csr_write_data[0]; 3.19 + bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG]; 3.20 + bp_e[i] <= debug_csr_write_data[0]; 3.21 end 3.22 end 3.23 end 3.24 @@ -270,17 +270,17 @@ 3.25 begin 3.26 if (rst_i == `TRUE) 3.27 begin 3.28 - wp[i] <= #1 {`LM32_WORD_WIDTH{1'bx}}; 3.29 - wpc_c[i] <= #1 `LM32_WPC_C_DISABLED; 3.30 + wp[i] <= {`LM32_WORD_WIDTH{1'bx}}; 3.31 + wpc_c[i] <= `LM32_WPC_C_DISABLED; 3.32 end 3.33 else 3.34 begin 3.35 if (debug_csr_write_enable == `TRUE) 3.36 begin 3.37 if (debug_csr == `LM32_CSR_DC) 3.38 - wpc_c[i] <= #1 debug_csr_write_data[3+i*2:2+i*2]; 3.39 + wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; 3.40 if (debug_csr == `LM32_CSR_WP0 + i) 3.41 - wp[i] <= #1 debug_csr_write_data; 3.42 + wp[i] <= debug_csr_write_data; 3.43 end 3.44 end 3.45 end 3.46 @@ -291,11 +291,11 @@ 3.47 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 3.48 begin 3.49 if (rst_i == `TRUE) 3.50 - dc_re <= #1 `FALSE; 3.51 + dc_re <= `FALSE; 3.52 else 3.53 begin 3.54 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 3.55 - dc_re <= #1 debug_csr_write_data[1]; 3.56 + dc_re <= debug_csr_write_data[1]; 3.57 end 3.58 end 3.59 3.60 @@ -305,18 +305,18 @@ 3.61 begin 3.62 if (rst_i == `TRUE) 3.63 begin 3.64 - state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 3.65 - dc_ss <= #1 `FALSE; 3.66 + state <= `LM32_DEBUG_SS_STATE_IDLE; 3.67 + dc_ss <= `FALSE; 3.68 end 3.69 else 3.70 begin 3.71 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 3.72 begin 3.73 - dc_ss <= #1 debug_csr_write_data[0]; 3.74 + dc_ss <= debug_csr_write_data[0]; 3.75 if (debug_csr_write_data[0] == `FALSE) 3.76 - state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 3.77 + state <= `LM32_DEBUG_SS_STATE_IDLE; 3.78 else 3.79 - state <= #1 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 3.80 + state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 3.81 end 3.82 case (state) 3.83 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET: 3.84 @@ -327,26 +327,26 @@ 3.85 ) 3.86 && (stall_x == `FALSE) 3.87 ) 3.88 - state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 3.89 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 3.90 end 3.91 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN: 3.92 begin 3.93 // Wait for an instruction to be executed 3.94 if ((q_x == `TRUE) && (stall_x == `FALSE)) 3.95 - state <= #1 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 3.96 + state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 3.97 end 3.98 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT: 3.99 begin 3.100 // Wait for exception to be raised 3.101 `ifdef CFG_DCACHE_ENABLED 3.102 if (dcache_refill_request == `TRUE) 3.103 - state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 3.104 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 3.105 else 3.106 `endif 3.107 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 3.108 begin 3.109 - dc_ss <= #1 `FALSE; 3.110 - state <= #1 `LM32_DEBUG_SS_STATE_RESTART; 3.111 + dc_ss <= `FALSE; 3.112 + state <= `LM32_DEBUG_SS_STATE_RESTART; 3.113 end 3.114 end 3.115 `LM32_DEBUG_SS_STATE_RESTART: 3.116 @@ -354,10 +354,10 @@ 3.117 // Watch to see if stepped instruction is restarted due to a cache miss 3.118 `ifdef CFG_DCACHE_ENABLED 3.119 if (dcache_refill_request == `TRUE) 3.120 - state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 3.121 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 3.122 else 3.123 `endif 3.124 - state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 3.125 + state <= `LM32_DEBUG_SS_STATE_IDLE; 3.126 end 3.127 endcase 3.128 end
4.1 diff -r 73de224304c1 -r d6c693415d59 lm32_icache.v 4.2 --- a/lm32_icache.v Sat Aug 06 00:02:46 2011 +0100 4.3 +++ b/lm32_icache.v Sat Aug 06 01:26:56 2011 +0100 4.4 @@ -380,11 +380,11 @@ 4.5 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 4.6 begin 4.7 if (rst_i == `TRUE) 4.8 - refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1}; 4.9 + refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 4.10 else 4.11 begin 4.12 if (miss == `TRUE) 4.13 - refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]}; 4.14 + refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 4.15 end 4.16 end 4.17 end 4.18 @@ -394,9 +394,9 @@ 4.19 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 4.20 begin 4.21 if (rst_i == `TRUE) 4.22 - refilling <= #1 `FALSE; 4.23 + refilling <= `FALSE; 4.24 else 4.25 - refilling <= #1 refill; 4.26 + refilling <= refill; 4.27 end 4.28 4.29 // Instruction cache control FSM 4.30 @@ -404,10 +404,10 @@ 4.31 begin 4.32 if (rst_i == `TRUE) 4.33 begin 4.34 - state <= #1 `LM32_IC_STATE_FLUSH_INIT; 4.35 - flush_set <= #1 {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 4.36 - refill_address <= #1 {`LM32_PC_WIDTH{1'bx}}; 4.37 - restart_request <= #1 `FALSE; 4.38 + state <= `LM32_IC_STATE_FLUSH_INIT; 4.39 + flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 4.40 + refill_address <= {`LM32_PC_WIDTH{1'bx}}; 4.41 + restart_request <= `FALSE; 4.42 end 4.43 else 4.44 begin 4.45 @@ -417,8 +417,8 @@ 4.46 `LM32_IC_STATE_FLUSH_INIT: 4.47 begin 4.48 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 4.49 - state <= #1 `LM32_IC_STATE_CHECK; 4.50 - flush_set <= #1 flush_set - 1'b1; 4.51 + state <= `LM32_IC_STATE_CHECK; 4.52 + flush_set <= flush_set - 1'b1; 4.53 end 4.54 4.55 // Flush the cache in response to an write to the ICC CSR 4.56 @@ -427,28 +427,28 @@ 4.57 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 4.58 `ifdef CFG_IROM_ENABLED 4.59 if (select_f) 4.60 - state <= #1 `LM32_IC_STATE_REFILL; 4.61 + state <= `LM32_IC_STATE_REFILL; 4.62 else 4.63 `endif 4.64 - state <= #1 `LM32_IC_STATE_CHECK; 4.65 + state <= `LM32_IC_STATE_CHECK; 4.66 4.67 - flush_set <= #1 flush_set - 1'b1; 4.68 + flush_set <= flush_set - 1'b1; 4.69 end 4.70 4.71 // Check for cache misses 4.72 `LM32_IC_STATE_CHECK: 4.73 begin 4.74 if (stall_a == `FALSE) 4.75 - restart_request <= #1 `FALSE; 4.76 + restart_request <= `FALSE; 4.77 if (iflush == `TRUE) 4.78 begin 4.79 - refill_address <= #1 address_f; 4.80 - state <= #1 `LM32_IC_STATE_FLUSH; 4.81 + refill_address <= address_f; 4.82 + state <= `LM32_IC_STATE_FLUSH; 4.83 end 4.84 else if (miss == `TRUE) 4.85 begin 4.86 - refill_address <= #1 address_f; 4.87 - state <= #1 `LM32_IC_STATE_REFILL; 4.88 + refill_address <= address_f; 4.89 + state <= `LM32_IC_STATE_REFILL; 4.90 end 4.91 end 4.92 4.93 @@ -459,8 +459,8 @@ 4.94 begin 4.95 if (last_refill == `TRUE) 4.96 begin 4.97 - restart_request <= #1 `TRUE; 4.98 - state <= #1 `LM32_IC_STATE_CHECK; 4.99 + restart_request <= `TRUE; 4.100 + state <= `LM32_IC_STATE_CHECK; 4.101 end 4.102 end 4.103 end 4.104 @@ -476,7 +476,7 @@ 4.105 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 4.106 begin 4.107 if (rst_i == `TRUE) 4.108 - refill_offset <= #1 {addr_offset_width{1'b0}}; 4.109 + refill_offset <= {addr_offset_width{1'b0}}; 4.110 else 4.111 begin 4.112 case (state) 4.113 @@ -485,16 +485,16 @@ 4.114 `LM32_IC_STATE_CHECK: 4.115 begin 4.116 if (iflush == `TRUE) 4.117 - refill_offset <= #1 {addr_offset_width{1'b0}}; 4.118 + refill_offset <= {addr_offset_width{1'b0}}; 4.119 else if (miss == `TRUE) 4.120 - refill_offset <= #1 {addr_offset_width{1'b0}}; 4.121 + refill_offset <= {addr_offset_width{1'b0}}; 4.122 end 4.123 4.124 // Refill a cache line 4.125 `LM32_IC_STATE_REFILL: 4.126 begin 4.127 if (refill_ready == `TRUE) 4.128 - refill_offset <= #1 refill_offset + 1'b1; 4.129 + refill_offset <= refill_offset + 1'b1; 4.130 end 4.131 4.132 endcase
5.1 diff -r 73de224304c1 -r d6c693415d59 lm32_instruction_unit.v 5.2 --- a/lm32_instruction_unit.v Sat Aug 06 00:02:46 2011 +0100 5.3 +++ b/lm32_instruction_unit.v Sat Aug 06 01:26:56 2011 +0100 5.4 @@ -587,31 +587,31 @@ 5.5 `ifdef CFG_DEBUG_ENABLED 5.6 `ifdef CFG_ALTERNATE_EBA 5.7 if (at_debug == `TRUE) 5.8 - pc_f <= #1 (`CFG_DEBA_RESET-4)/4; 5.9 + pc_f <= (`CFG_DEBA_RESET-4)/4; 5.10 else 5.11 - pc_f <= #1 (`CFG_EBA_RESET-4)/4; 5.12 + pc_f <= (`CFG_EBA_RESET-4)/4; 5.13 `else 5.14 - pc_f <= #1 (`CFG_EBA_RESET-4)/4; 5.15 + pc_f <= (`CFG_EBA_RESET-4)/4; 5.16 `endif 5.17 `else 5.18 - pc_f <= #1 (`CFG_EBA_RESET-4)/4; 5.19 + pc_f <= (`CFG_EBA_RESET-4)/4; 5.20 `endif 5.21 - pc_d <= #1 {`LM32_PC_WIDTH{1'b0}}; 5.22 - pc_x <= #1 {`LM32_PC_WIDTH{1'b0}}; 5.23 - pc_m <= #1 {`LM32_PC_WIDTH{1'b0}}; 5.24 - pc_w <= #1 {`LM32_PC_WIDTH{1'b0}}; 5.25 + pc_d <= {`LM32_PC_WIDTH{1'b0}}; 5.26 + pc_x <= {`LM32_PC_WIDTH{1'b0}}; 5.27 + pc_m <= {`LM32_PC_WIDTH{1'b0}}; 5.28 + pc_w <= {`LM32_PC_WIDTH{1'b0}}; 5.29 end 5.30 else 5.31 begin 5.32 if (stall_f == `FALSE) 5.33 - pc_f <= #1 pc_a; 5.34 + pc_f <= pc_a; 5.35 if (stall_d == `FALSE) 5.36 - pc_d <= #1 pc_f; 5.37 + pc_d <= pc_f; 5.38 if (stall_x == `FALSE) 5.39 - pc_x <= #1 pc_d; 5.40 + pc_x <= pc_d; 5.41 if (stall_m == `FALSE) 5.42 - pc_m <= #1 pc_x; 5.43 - pc_w <= #1 pc_m; 5.44 + pc_m <= pc_x; 5.45 + pc_w <= pc_m; 5.46 end 5.47 end 5.48 5.49 @@ -620,24 +620,24 @@ 5.50 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 5.51 begin 5.52 if (rst_i == `TRUE) 5.53 - restart_address <= #1 {`LM32_PC_WIDTH{1'b0}}; 5.54 + restart_address <= {`LM32_PC_WIDTH{1'b0}}; 5.55 else 5.56 begin 5.57 `ifdef CFG_DCACHE_ENABLED 5.58 `ifdef CFG_ICACHE_ENABLED 5.59 // D-cache restart address must take priority, otherwise instructions will be lost 5.60 if (dcache_refill_request == `TRUE) 5.61 - restart_address <= #1 pc_w; 5.62 + restart_address <= pc_w; 5.63 else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request)) 5.64 - restart_address <= #1 icache_refill_address; 5.65 + restart_address <= icache_refill_address; 5.66 `else 5.67 if (dcache_refill_request == `TRUE) 5.68 - restart_address <= #1 pc_w; 5.69 + restart_address <= pc_w; 5.70 `endif 5.71 `else 5.72 `ifdef CFG_ICACHE_ENABLED 5.73 if (icache_refill_request == `TRUE) 5.74 - restart_address <= #1 icache_refill_address; 5.75 + restart_address <= icache_refill_address; 5.76 `endif 5.77 `endif 5.78 end 5.79 @@ -649,11 +649,11 @@ 5.80 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 5.81 begin 5.82 if (rst_i == `TRUE) 5.83 - irom_select_f <= #1 `FALSE; 5.84 + irom_select_f <= `FALSE; 5.85 else 5.86 begin 5.87 if (stall_f == `FALSE) 5.88 - irom_select_f <= #1 irom_select_a; 5.89 + irom_select_f <= irom_select_a; 5.90 end 5.91 end 5.92 `endif 5.93 @@ -678,25 +678,25 @@ 5.94 begin 5.95 if (rst_i == `TRUE) 5.96 begin 5.97 - i_cyc_o <= #1 `FALSE; 5.98 - i_stb_o <= #1 `FALSE; 5.99 - i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 5.100 - i_cti_o <= #1 `LM32_CTYPE_END; 5.101 - i_lock_o <= #1 `FALSE; 5.102 - icache_refill_data <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 5.103 - icache_refill_ready <= #1 `FALSE; 5.104 + i_cyc_o <= `FALSE; 5.105 + i_stb_o <= `FALSE; 5.106 + i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 5.107 + i_cti_o <= `LM32_CTYPE_END; 5.108 + i_lock_o <= `FALSE; 5.109 + icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 5.110 + icache_refill_ready <= `FALSE; 5.111 `ifdef CFG_BUS_ERRORS_ENABLED 5.112 - bus_error_f <= #1 `FALSE; 5.113 + bus_error_f <= `FALSE; 5.114 `endif 5.115 `ifdef CFG_HW_DEBUG_ENABLED 5.116 - i_we_o <= #1 `FALSE; 5.117 - i_sel_o <= #1 4'b1111; 5.118 - jtag_access <= #1 `FALSE; 5.119 + i_we_o <= `FALSE; 5.120 + i_sel_o <= 4'b1111; 5.121 + jtag_access <= `FALSE; 5.122 `endif 5.123 end 5.124 else 5.125 begin 5.126 - icache_refill_ready <= #1 `FALSE; 5.127 + icache_refill_ready <= `FALSE; 5.128 // Is a cycle in progress? 5.129 if (i_cyc_o == `TRUE) 5.130 begin 5.131 @@ -706,10 +706,10 @@ 5.132 `ifdef CFG_HW_DEBUG_ENABLED 5.133 if (jtag_access == `TRUE) 5.134 begin 5.135 - i_cyc_o <= #1 `FALSE; 5.136 - i_stb_o <= #1 `FALSE; 5.137 - i_we_o <= #1 `FALSE; 5.138 - jtag_access <= #1 `FALSE; 5.139 + i_cyc_o <= `FALSE; 5.140 + i_stb_o <= `FALSE; 5.141 + i_we_o <= `FALSE; 5.142 + jtag_access <= `FALSE; 5.143 end 5.144 else 5.145 `endif 5.146 @@ -717,22 +717,22 @@ 5.147 if (last_word == `TRUE) 5.148 begin 5.149 // Cache line fill complete 5.150 - i_cyc_o <= #1 `FALSE; 5.151 - i_stb_o <= #1 `FALSE; 5.152 - i_lock_o <= #1 `FALSE; 5.153 + i_cyc_o <= `FALSE; 5.154 + i_stb_o <= `FALSE; 5.155 + i_lock_o <= `FALSE; 5.156 end 5.157 // Fetch next word in cache line 5.158 - i_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 5.159 - i_cti_o <= #1 next_cycle_type; 5.160 + i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 5.161 + i_cti_o <= next_cycle_type; 5.162 // Write fetched data into instruction cache 5.163 - icache_refill_ready <= #1 `TRUE; 5.164 - icache_refill_data <= #1 i_dat_i; 5.165 + icache_refill_ready <= `TRUE; 5.166 + icache_refill_data <= i_dat_i; 5.167 end 5.168 end 5.169 `ifdef CFG_BUS_ERRORS_ENABLED 5.170 if (i_err_i == `TRUE) 5.171 begin 5.172 - bus_error_f <= #1 `TRUE; 5.173 + bus_error_f <= `TRUE; 5.174 $display ("Instruction bus error. Address: %x", i_adr_o); 5.175 end 5.176 `endif 5.177 @@ -743,15 +743,15 @@ 5.178 begin 5.179 // Read first word of cache line 5.180 `ifdef CFG_HW_DEBUG_ENABLED 5.181 - i_sel_o <= #1 4'b1111; 5.182 + i_sel_o <= 4'b1111; 5.183 `endif 5.184 - i_adr_o <= #1 {first_address, 2'b00}; 5.185 - i_cyc_o <= #1 `TRUE; 5.186 - i_stb_o <= #1 `TRUE; 5.187 - i_cti_o <= #1 first_cycle_type; 5.188 - //i_lock_o <= #1 `TRUE; 5.189 + i_adr_o <= {first_address, 2'b00}; 5.190 + i_cyc_o <= `TRUE; 5.191 + i_stb_o <= `TRUE; 5.192 + i_cti_o <= first_cycle_type; 5.193 + //i_lock_o <= `TRUE; 5.194 `ifdef CFG_BUS_ERRORS_ENABLED 5.195 - bus_error_f <= #1 `FALSE; 5.196 + bus_error_f <= `FALSE; 5.197 `endif 5.198 end 5.199 `ifdef CFG_HW_DEBUG_ENABLED 5.200 @@ -760,18 +760,18 @@ 5.201 if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE)) 5.202 begin 5.203 case (jtag_address[1:0]) 5.204 - 2'b00: i_sel_o <= #1 4'b1000; 5.205 - 2'b01: i_sel_o <= #1 4'b0100; 5.206 - 2'b10: i_sel_o <= #1 4'b0010; 5.207 - 2'b11: i_sel_o <= #1 4'b0001; 5.208 + 2'b00: i_sel_o <= 4'b1000; 5.209 + 2'b01: i_sel_o <= 4'b0100; 5.210 + 2'b10: i_sel_o <= 4'b0010; 5.211 + 2'b11: i_sel_o <= 4'b0001; 5.212 endcase 5.213 - i_adr_o <= #1 jtag_address; 5.214 - i_dat_o <= #1 {4{jtag_write_data}}; 5.215 - i_cyc_o <= #1 `TRUE; 5.216 - i_stb_o <= #1 `TRUE; 5.217 - i_we_o <= #1 jtag_write_enable; 5.218 - i_cti_o <= #1 `LM32_CTYPE_END; 5.219 - jtag_access <= #1 `TRUE; 5.220 + i_adr_o <= jtag_address; 5.221 + i_dat_o <= {4{jtag_write_data}}; 5.222 + i_cyc_o <= `TRUE; 5.223 + i_stb_o <= `TRUE; 5.224 + i_we_o <= jtag_write_enable; 5.225 + i_cti_o <= `LM32_CTYPE_END; 5.226 + jtag_access <= `TRUE; 5.227 end 5.228 end 5.229 `endif 5.230 @@ -780,10 +780,10 @@ 5.231 // continually generated if exception handler is cached 5.232 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH 5.233 if (branch_taken_x == `TRUE) 5.234 - bus_error_f <= #1 `FALSE; 5.235 + bus_error_f <= `FALSE; 5.236 `endif 5.237 if (branch_taken_m == `TRUE) 5.238 - bus_error_f <= #1 `FALSE; 5.239 + bus_error_f <= `FALSE; 5.240 `endif 5.241 end 5.242 end 5.243 @@ -793,14 +793,14 @@ 5.244 begin 5.245 if (rst_i == `TRUE) 5.246 begin 5.247 - i_cyc_o <= #1 `FALSE; 5.248 - i_stb_o <= #1 `FALSE; 5.249 - i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 5.250 - i_cti_o <= #1 `LM32_CTYPE_END; 5.251 - i_lock_o <= #1 `FALSE; 5.252 - wb_data_f <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 5.253 + i_cyc_o <= `FALSE; 5.254 + i_stb_o <= `FALSE; 5.255 + i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 5.256 + i_cti_o <= `LM32_CTYPE_END; 5.257 + i_lock_o <= `FALSE; 5.258 + wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 5.259 `ifdef CFG_BUS_ERRORS_ENABLED 5.260 - bus_error_f <= #1 `FALSE; 5.261 + bus_error_f <= `FALSE; 5.262 `endif 5.263 end 5.264 else 5.265 @@ -812,15 +812,15 @@ 5.266 if((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 5.267 begin 5.268 // Cycle complete 5.269 - i_cyc_o <= #1 `FALSE; 5.270 - i_stb_o <= #1 `FALSE; 5.271 + i_cyc_o <= `FALSE; 5.272 + i_stb_o <= `FALSE; 5.273 // Register fetched instruction 5.274 - wb_data_f <= #1 i_dat_i; 5.275 + wb_data_f <= i_dat_i; 5.276 end 5.277 `ifdef CFG_BUS_ERRORS_ENABLED 5.278 if (i_err_i == `TRUE) 5.279 begin 5.280 - bus_error_f <= #1 `TRUE; 5.281 + bus_error_f <= `TRUE; 5.282 $display ("Instruction bus error. Address: %x", i_adr_o); 5.283 end 5.284 `endif 5.285 @@ -836,13 +836,13 @@ 5.286 begin 5.287 // Fetch instruction 5.288 `ifdef CFG_HW_DEBUG_ENABLED 5.289 - i_sel_o <= #1 4'b1111; 5.290 + i_sel_o <= 4'b1111; 5.291 `endif 5.292 - i_adr_o <= #1 {pc_a, 2'b00}; 5.293 - i_cyc_o <= #1 `TRUE; 5.294 - i_stb_o <= #1 `TRUE; 5.295 + i_adr_o <= {pc_a, 2'b00}; 5.296 + i_cyc_o <= `TRUE; 5.297 + i_stb_o <= `TRUE; 5.298 `ifdef CFG_BUS_ERRORS_ENABLED 5.299 - bus_error_f <= #1 `FALSE; 5.300 + bus_error_f <= `FALSE; 5.301 `endif 5.302 end 5.303 else 5.304 @@ -854,7 +854,7 @@ 5.305 ) 5.306 begin 5.307 `ifdef CFG_BUS_ERRORS_ENABLED 5.308 - bus_error_f <= #1 `FALSE; 5.309 + bus_error_f <= `FALSE; 5.310 `endif 5.311 end 5.312 end 5.313 @@ -869,18 +869,18 @@ 5.314 begin 5.315 if (rst_i == `TRUE) 5.316 begin 5.317 - instruction_d <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 5.318 + instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 5.319 `ifdef CFG_BUS_ERRORS_ENABLED 5.320 - bus_error_d <= #1 `FALSE; 5.321 + bus_error_d <= `FALSE; 5.322 `endif 5.323 end 5.324 else 5.325 begin 5.326 if (stall_d == `FALSE) 5.327 begin 5.328 - instruction_d <= #1 instruction_f; 5.329 + instruction_d <= instruction_f; 5.330 `ifdef CFG_BUS_ERRORS_ENABLED 5.331 - bus_error_d <= #1 bus_error_f; 5.332 + bus_error_d <= bus_error_f; 5.333 `endif 5.334 end 5.335 end
6.1 diff -r 73de224304c1 -r d6c693415d59 lm32_interrupt.v 6.2 --- a/lm32_interrupt.v Sat Aug 06 00:02:46 2011 +0100 6.3 +++ b/lm32_interrupt.v Sat Aug 06 01:26:56 2011 +0100 6.4 @@ -220,64 +220,64 @@ 6.5 begin 6.6 if (rst_i == `TRUE) 6.7 begin 6.8 - ie <= #1 `FALSE; 6.9 - eie <= #1 `FALSE; 6.10 + ie <= `FALSE; 6.11 + eie <= `FALSE; 6.12 `ifdef CFG_DEBUG_ENABLED 6.13 - bie <= #1 `FALSE; 6.14 + bie <= `FALSE; 6.15 `endif 6.16 - im <= #1 {interrupts{1'b0}}; 6.17 - ip <= #1 {interrupts{1'b0}}; 6.18 + im <= {interrupts{1'b0}}; 6.19 + ip <= {interrupts{1'b0}}; 6.20 end 6.21 else 6.22 begin 6.23 // Set IP bit when interrupt line is asserted 6.24 - ip <= #1 asserted; 6.25 + ip <= asserted; 6.26 `ifdef CFG_DEBUG_ENABLED 6.27 if (non_debug_exception == `TRUE) 6.28 begin 6.29 // Save and then clear interrupt enable 6.30 - eie <= #1 ie; 6.31 - ie <= #1 `FALSE; 6.32 + eie <= ie; 6.33 + ie <= `FALSE; 6.34 end 6.35 else if (debug_exception == `TRUE) 6.36 begin 6.37 // Save and then clear interrupt enable 6.38 - bie <= #1 ie; 6.39 - ie <= #1 `FALSE; 6.40 + bie <= ie; 6.41 + ie <= `FALSE; 6.42 end 6.43 `else 6.44 if (exception == `TRUE) 6.45 begin 6.46 // Save and then clear interrupt enable 6.47 - eie <= #1 ie; 6.48 - ie <= #1 `FALSE; 6.49 + eie <= ie; 6.50 + ie <= `FALSE; 6.51 end 6.52 `endif 6.53 else if (stall_x == `FALSE) 6.54 begin 6.55 if (eret_q_x == `TRUE) 6.56 // Restore interrupt enable 6.57 - ie <= #1 eie; 6.58 + ie <= eie; 6.59 `ifdef CFG_DEBUG_ENABLED 6.60 else if (bret_q_x == `TRUE) 6.61 // Restore interrupt enable 6.62 - ie <= #1 bie; 6.63 + ie <= bie; 6.64 `endif 6.65 else if (csr_write_enable == `TRUE) 6.66 begin 6.67 // Handle wcsr write 6.68 if (csr == `LM32_CSR_IE) 6.69 begin 6.70 - ie <= #1 csr_write_data[0]; 6.71 - eie <= #1 csr_write_data[1]; 6.72 + ie <= csr_write_data[0]; 6.73 + eie <= csr_write_data[1]; 6.74 `ifdef CFG_DEBUG_ENABLED 6.75 - bie <= #1 csr_write_data[2]; 6.76 + bie <= csr_write_data[2]; 6.77 `endif 6.78 end 6.79 if (csr == `LM32_CSR_IM) 6.80 - im <= #1 csr_write_data[interrupts-1:0]; 6.81 + im <= csr_write_data[interrupts-1:0]; 6.82 if (csr == `LM32_CSR_IP) 6.83 - ip <= #1 asserted & ~csr_write_data[interrupts-1:0]; 6.84 + ip <= asserted & ~csr_write_data[interrupts-1:0]; 6.85 end 6.86 end 6.87 end 6.88 @@ -290,61 +290,61 @@ 6.89 begin 6.90 if (rst_i == `TRUE) 6.91 begin 6.92 - ie <= #1 `FALSE; 6.93 - eie <= #1 `FALSE; 6.94 + ie <= `FALSE; 6.95 + eie <= `FALSE; 6.96 `ifdef CFG_DEBUG_ENABLED 6.97 - bie <= #1 `FALSE; 6.98 + bie <= `FALSE; 6.99 `endif 6.100 - ip <= #1 {interrupts{1'b0}}; 6.101 + ip <= {interrupts{1'b0}}; 6.102 end 6.103 else 6.104 begin 6.105 // Set IP bit when interrupt line is asserted 6.106 - ip <= #1 asserted; 6.107 + ip <= asserted; 6.108 `ifdef CFG_DEBUG_ENABLED 6.109 if (non_debug_exception == `TRUE) 6.110 begin 6.111 // Save and then clear interrupt enable 6.112 - eie <= #1 ie; 6.113 - ie <= #1 `FALSE; 6.114 + eie <= ie; 6.115 + ie <= `FALSE; 6.116 end 6.117 else if (debug_exception == `TRUE) 6.118 begin 6.119 // Save and then clear interrupt enable 6.120 - bie <= #1 ie; 6.121 - ie <= #1 `FALSE; 6.122 + bie <= ie; 6.123 + ie <= `FALSE; 6.124 end 6.125 `else 6.126 if (exception == `TRUE) 6.127 begin 6.128 // Save and then clear interrupt enable 6.129 - eie <= #1 ie; 6.130 - ie <= #1 `FALSE; 6.131 + eie <= ie; 6.132 + ie <= `FALSE; 6.133 end 6.134 `endif 6.135 else if (stall_x == `FALSE) 6.136 begin 6.137 if (eret_q_x == `TRUE) 6.138 // Restore interrupt enable 6.139 - ie <= #1 eie; 6.140 + ie <= eie; 6.141 `ifdef CFG_DEBUG_ENABLED 6.142 else if (bret_q_x == `TRUE) 6.143 // Restore interrupt enable 6.144 - ie <= #1 bie; 6.145 + ie <= bie; 6.146 `endif 6.147 else if (csr_write_enable == `TRUE) 6.148 begin 6.149 // Handle wcsr write 6.150 if (csr == `LM32_CSR_IE) 6.151 begin 6.152 - ie <= #1 csr_write_data[0]; 6.153 - eie <= #1 csr_write_data[1]; 6.154 + ie <= csr_write_data[0]; 6.155 + eie <= csr_write_data[1]; 6.156 `ifdef CFG_DEBUG_ENABLED 6.157 - bie <= #1 csr_write_data[2]; 6.158 + bie <= csr_write_data[2]; 6.159 `endif 6.160 end 6.161 if (csr == `LM32_CSR_IP) 6.162 - ip <= #1 asserted & ~csr_write_data[interrupts-1:0]; 6.163 + ip <= asserted & ~csr_write_data[interrupts-1:0]; 6.164 end 6.165 end 6.166 end
7.1 diff -r 73de224304c1 -r d6c693415d59 lm32_jtag.v 7.2 --- a/lm32_jtag.v Sat Aug 06 00:02:46 2011 +0100 7.3 +++ b/lm32_jtag.v Sat Aug 06 01:26:56 2011 +0100 7.4 @@ -257,9 +257,9 @@ 7.5 always @(negedge jtag_update `CFG_RESET_SENSITIVITY) 7.6 begin 7.7 if (rst_i == `TRUE) 7.8 - rx_toggle <= #1 1'b0; 7.9 + rx_toggle <= 1'b0; 7.10 else 7.11 - rx_toggle <= #1 ~rx_toggle; 7.12 + rx_toggle <= ~rx_toggle; 7.13 end 7.14 7.15 always @(*) 7.16 @@ -273,15 +273,15 @@ 7.17 begin 7.18 if (rst_i == `TRUE) 7.19 begin 7.20 - rx_toggle_r <= #1 1'b0; 7.21 - rx_toggle_r_r <= #1 1'b0; 7.22 - rx_toggle_r_r_r <= #1 1'b0; 7.23 + rx_toggle_r <= 1'b0; 7.24 + rx_toggle_r_r <= 1'b0; 7.25 + rx_toggle_r_r_r <= 1'b0; 7.26 end 7.27 else 7.28 begin 7.29 - rx_toggle_r <= #1 rx_toggle; 7.30 - rx_toggle_r_r <= #1 rx_toggle_r; 7.31 - rx_toggle_r_r_r <= #1 rx_toggle_r_r; 7.32 + rx_toggle_r <= rx_toggle; 7.33 + rx_toggle_r_r <= rx_toggle_r; 7.34 + rx_toggle_r_r_r <= rx_toggle_r_r; 7.35 end 7.36 end 7.37 7.38 @@ -290,24 +290,24 @@ 7.39 begin 7.40 if (rst_i == `TRUE) 7.41 begin 7.42 - state <= #1 `LM32_JTAG_STATE_READ_COMMAND; 7.43 - command <= #1 4'b0000; 7.44 - jtag_reg_d <= #1 8'h00; 7.45 + state <= `LM32_JTAG_STATE_READ_COMMAND; 7.46 + command <= 4'b0000; 7.47 + jtag_reg_d <= 8'h00; 7.48 `ifdef CFG_HW_DEBUG_ENABLED 7.49 - processing <= #1 `FALSE; 7.50 - jtag_csr_write_enable <= #1 `FALSE; 7.51 - jtag_read_enable <= #1 `FALSE; 7.52 - jtag_write_enable <= #1 `FALSE; 7.53 + processing <= `FALSE; 7.54 + jtag_csr_write_enable <= `FALSE; 7.55 + jtag_read_enable <= `FALSE; 7.56 + jtag_write_enable <= `FALSE; 7.57 `endif 7.58 `ifdef CFG_DEBUG_ENABLED 7.59 - jtag_break <= #1 `FALSE; 7.60 - jtag_reset <= #1 `FALSE; 7.61 + jtag_break <= `FALSE; 7.62 + jtag_reset <= `FALSE; 7.63 `endif 7.64 `ifdef CFG_JTAG_UART_ENABLED 7.65 - uart_tx_byte <= #1 8'h00; 7.66 - uart_tx_valid <= #1 `FALSE; 7.67 - uart_rx_byte <= #1 8'h00; 7.68 - uart_rx_valid <= #1 `FALSE; 7.69 + uart_tx_byte <= 8'h00; 7.70 + uart_tx_valid <= `FALSE; 7.71 + uart_rx_byte <= 8'h00; 7.72 + uart_rx_valid <= `FALSE; 7.73 `endif 7.74 end 7.75 else 7.76 @@ -319,13 +319,13 @@ 7.77 `LM32_CSR_JTX: 7.78 begin 7.79 // Set flag indicating data is available 7.80 - uart_tx_byte <= #1 csr_write_data[`LM32_BYTE_0_RNG]; 7.81 - uart_tx_valid <= #1 `TRUE; 7.82 + uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG]; 7.83 + uart_tx_valid <= `TRUE; 7.84 end 7.85 `LM32_CSR_JRX: 7.86 begin 7.87 // Clear flag indidicating data has been received 7.88 - uart_rx_valid <= #1 `FALSE; 7.89 + uart_rx_valid <= `FALSE; 7.90 end 7.91 endcase 7.92 end 7.93 @@ -334,8 +334,8 @@ 7.94 // When an exception has occured, clear the requests 7.95 if (exception_q_w == `TRUE) 7.96 begin 7.97 - jtag_break <= #1 `FALSE; 7.98 - jtag_reset <= #1 `FALSE; 7.99 + jtag_break <= `FALSE; 7.100 + jtag_reset <= `FALSE; 7.101 end 7.102 `endif 7.103 case (state) 7.104 @@ -344,7 +344,7 @@ 7.105 // Wait for rx register to toggle which indicates new data is available 7.106 if (rx_toggle_r_r != rx_toggle_r_r_r) 7.107 begin 7.108 - command <= #1 rx_byte[7:4]; 7.109 + command <= rx_byte[7:4]; 7.110 case (rx_addr) 7.111 `ifdef CFG_DEBUG_ENABLED 7.112 `LM32_DP: 7.113 @@ -352,37 +352,37 @@ 7.114 case (rx_byte[7:4]) 7.115 `ifdef CFG_HW_DEBUG_ENABLED 7.116 `LM32_DP_READ_MEMORY: 7.117 - state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; 7.118 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 7.119 `LM32_DP_READ_SEQUENTIAL: 7.120 begin 7.121 - {jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1; 7.122 - state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; 7.123 + {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 7.124 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 7.125 end 7.126 `LM32_DP_WRITE_MEMORY: 7.127 - state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; 7.128 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 7.129 `LM32_DP_WRITE_SEQUENTIAL: 7.130 begin 7.131 - {jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1; 7.132 - state <= #1 5; 7.133 + {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 7.134 + state <= 5; 7.135 end 7.136 `LM32_DP_WRITE_CSR: 7.137 - state <= #1 `LM32_JTAG_STATE_READ_BYTE_0; 7.138 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 7.139 `endif 7.140 `LM32_DP_BREAK: 7.141 begin 7.142 `ifdef CFG_JTAG_UART_ENABLED 7.143 - uart_rx_valid <= #1 `FALSE; 7.144 - uart_tx_valid <= #1 `FALSE; 7.145 + uart_rx_valid <= `FALSE; 7.146 + uart_tx_valid <= `FALSE; 7.147 `endif 7.148 - jtag_break <= #1 `TRUE; 7.149 + jtag_break <= `TRUE; 7.150 end 7.151 `LM32_DP_RESET: 7.152 begin 7.153 `ifdef CFG_JTAG_UART_ENABLED 7.154 - uart_rx_valid <= #1 `FALSE; 7.155 - uart_tx_valid <= #1 `FALSE; 7.156 + uart_rx_valid <= `FALSE; 7.157 + uart_tx_valid <= `FALSE; 7.158 `endif 7.159 - jtag_reset <= #1 `TRUE; 7.160 + jtag_reset <= `TRUE; 7.161 end 7.162 endcase 7.163 end 7.164 @@ -390,13 +390,13 @@ 7.165 `ifdef CFG_JTAG_UART_ENABLED 7.166 `LM32_TX: 7.167 begin 7.168 - uart_rx_byte <= #1 rx_byte; 7.169 - uart_rx_valid <= #1 `TRUE; 7.170 + uart_rx_byte <= rx_byte; 7.171 + uart_rx_valid <= `TRUE; 7.172 end 7.173 `LM32_RX: 7.174 begin 7.175 - jtag_reg_d <= #1 uart_tx_byte; 7.176 - uart_tx_valid <= #1 `FALSE; 7.177 + jtag_reg_d <= uart_tx_byte; 7.178 + uart_tx_valid <= `FALSE; 7.179 end 7.180 `endif 7.181 default: 7.182 @@ -409,43 +409,43 @@ 7.183 begin 7.184 if (rx_toggle_r_r != rx_toggle_r_r_r) 7.185 begin 7.186 - jtag_byte_0 <= #1 rx_byte; 7.187 - state <= #1 `LM32_JTAG_STATE_READ_BYTE_1; 7.188 + jtag_byte_0 <= rx_byte; 7.189 + state <= `LM32_JTAG_STATE_READ_BYTE_1; 7.190 end 7.191 end 7.192 `LM32_JTAG_STATE_READ_BYTE_1: 7.193 begin 7.194 if (rx_toggle_r_r != rx_toggle_r_r_r) 7.195 begin 7.196 - jtag_byte_1 <= #1 rx_byte; 7.197 - state <= #1 `LM32_JTAG_STATE_READ_BYTE_2; 7.198 + jtag_byte_1 <= rx_byte; 7.199 + state <= `LM32_JTAG_STATE_READ_BYTE_2; 7.200 end 7.201 end 7.202 `LM32_JTAG_STATE_READ_BYTE_2: 7.203 begin 7.204 if (rx_toggle_r_r != rx_toggle_r_r_r) 7.205 begin 7.206 - jtag_byte_2 <= #1 rx_byte; 7.207 - state <= #1 `LM32_JTAG_STATE_READ_BYTE_3; 7.208 + jtag_byte_2 <= rx_byte; 7.209 + state <= `LM32_JTAG_STATE_READ_BYTE_3; 7.210 end 7.211 end 7.212 `LM32_JTAG_STATE_READ_BYTE_3: 7.213 begin 7.214 if (rx_toggle_r_r != rx_toggle_r_r_r) 7.215 begin 7.216 - jtag_byte_3 <= #1 rx_byte; 7.217 + jtag_byte_3 <= rx_byte; 7.218 if (command == `LM32_DP_READ_MEMORY) 7.219 - state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; 7.220 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 7.221 else 7.222 - state <= #1 `LM32_JTAG_STATE_READ_BYTE_4; 7.223 + state <= `LM32_JTAG_STATE_READ_BYTE_4; 7.224 end 7.225 end 7.226 `LM32_JTAG_STATE_READ_BYTE_4: 7.227 begin 7.228 if (rx_toggle_r_r != rx_toggle_r_r_r) 7.229 begin 7.230 - jtag_byte_4 <= #1 rx_byte; 7.231 - state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND; 7.232 + jtag_byte_4 <= rx_byte; 7.233 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 7.234 end 7.235 end 7.236 `LM32_JTAG_STATE_PROCESS_COMMAND: 7.237 @@ -454,22 +454,22 @@ 7.238 `LM32_DP_READ_MEMORY, 7.239 `LM32_DP_READ_SEQUENTIAL: 7.240 begin 7.241 - jtag_read_enable <= #1 `TRUE; 7.242 - processing <= #1 `TRUE; 7.243 - state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 7.244 + jtag_read_enable <= `TRUE; 7.245 + processing <= `TRUE; 7.246 + state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 7.247 end 7.248 `LM32_DP_WRITE_MEMORY, 7.249 `LM32_DP_WRITE_SEQUENTIAL: 7.250 begin 7.251 - jtag_write_enable <= #1 `TRUE; 7.252 - processing <= #1 `TRUE; 7.253 - state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 7.254 + jtag_write_enable <= `TRUE; 7.255 + processing <= `TRUE; 7.256 + state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 7.257 end 7.258 `LM32_DP_WRITE_CSR: 7.259 begin 7.260 - jtag_csr_write_enable <= #1 `TRUE; 7.261 - processing <= #1 `TRUE; 7.262 - state <= #1 `LM32_JTAG_STATE_WAIT_FOR_CSR; 7.263 + jtag_csr_write_enable <= `TRUE; 7.264 + processing <= `TRUE; 7.265 + state <= `LM32_JTAG_STATE_WAIT_FOR_CSR; 7.266 end 7.267 endcase 7.268 end 7.269 @@ -477,18 +477,18 @@ 7.270 begin 7.271 if (jtag_access_complete == `TRUE) 7.272 begin 7.273 - jtag_read_enable <= #1 `FALSE; 7.274 - jtag_reg_d <= #1 jtag_read_data; 7.275 - jtag_write_enable <= #1 `FALSE; 7.276 - processing <= #1 `FALSE; 7.277 - state <= #1 `LM32_JTAG_STATE_READ_COMMAND; 7.278 + jtag_read_enable <= `FALSE; 7.279 + jtag_reg_d <= jtag_read_data; 7.280 + jtag_write_enable <= `FALSE; 7.281 + processing <= `FALSE; 7.282 + state <= `LM32_JTAG_STATE_READ_COMMAND; 7.283 end 7.284 end 7.285 `LM32_JTAG_STATE_WAIT_FOR_CSR: 7.286 begin 7.287 - jtag_csr_write_enable <= #1 `FALSE; 7.288 - processing <= #1 `FALSE; 7.289 - state <= #1 `LM32_JTAG_STATE_READ_COMMAND; 7.290 + jtag_csr_write_enable <= `FALSE; 7.291 + processing <= `FALSE; 7.292 + state <= `LM32_JTAG_STATE_READ_COMMAND; 7.293 end 7.294 `endif 7.295 endcase
8.1 diff -r 73de224304c1 -r d6c693415d59 lm32_load_store_unit.v 8.2 --- a/lm32_load_store_unit.v Sat Aug 06 00:02:46 2011 +0100 8.3 +++ b/lm32_load_store_unit.v Sat Aug 06 01:26:56 2011 +0100 8.4 @@ -343,13 +343,13 @@ 8.5 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 8.6 if (rst_i == `TRUE) 8.7 begin 8.8 - dram_bypass_en <= #1 `FALSE; 8.9 - dram_bypass_data <= #1 0; 8.10 + dram_bypass_en <= `FALSE; 8.11 + dram_bypass_data <= 0; 8.12 end 8.13 else 8.14 begin 8.15 if (stall_x == `FALSE) 8.16 - dram_bypass_data <= #1 dram_store_data_m; 8.17 + dram_bypass_data <= dram_store_data_m; 8.18 8.19 if ( (stall_m == `FALSE) 8.20 && (stall_x == `FALSE) 8.21 @@ -359,12 +359,12 @@ 8.22 ) 8.23 && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2]) 8.24 ) 8.25 - dram_bypass_en <= #1 `TRUE; 8.26 + dram_bypass_en <= `TRUE; 8.27 else 8.28 if ( (dram_bypass_en == `TRUE) 8.29 && (stall_x == `FALSE) 8.30 ) 8.31 - dram_bypass_en <= #1 `FALSE; 8.32 + dram_bypass_en <= `FALSE; 8.33 end 8.34 8.35 assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out; 8.36 @@ -624,26 +624,26 @@ 8.37 begin 8.38 if (rst_i == `TRUE) 8.39 begin 8.40 - d_cyc_o <= #1 `FALSE; 8.41 - d_stb_o <= #1 `FALSE; 8.42 - d_dat_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 8.43 - d_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 8.44 - d_sel_o <= #1 {`LM32_BYTE_SELECT_WIDTH{`FALSE}}; 8.45 - d_we_o <= #1 `FALSE; 8.46 - d_cti_o <= #1 `LM32_CTYPE_END; 8.47 - d_lock_o <= #1 `FALSE; 8.48 - wb_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 8.49 - wb_load_complete <= #1 `FALSE; 8.50 - stall_wb_load <= #1 `FALSE; 8.51 + d_cyc_o <= `FALSE; 8.52 + d_stb_o <= `FALSE; 8.53 + d_dat_o <= {`LM32_WORD_WIDTH{1'b0}}; 8.54 + d_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 8.55 + d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}}; 8.56 + d_we_o <= `FALSE; 8.57 + d_cti_o <= `LM32_CTYPE_END; 8.58 + d_lock_o <= `FALSE; 8.59 + wb_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 8.60 + wb_load_complete <= `FALSE; 8.61 + stall_wb_load <= `FALSE; 8.62 `ifdef CFG_DCACHE_ENABLED 8.63 - dcache_refill_ready <= #1 `FALSE; 8.64 + dcache_refill_ready <= `FALSE; 8.65 `endif 8.66 end 8.67 else 8.68 begin 8.69 `ifdef CFG_DCACHE_ENABLED 8.70 // Refill ready should only be asserted for a single cycle 8.71 - dcache_refill_ready <= #1 `FALSE; 8.72 + dcache_refill_ready <= `FALSE; 8.73 `endif 8.74 // Is a Wishbone cycle already in progress? 8.75 if (d_cyc_o == `TRUE) 8.76 @@ -655,25 +655,25 @@ 8.77 if ((dcache_refilling == `TRUE) && (!last_word)) 8.78 begin 8.79 // Fetch next word of cache line 8.80 - d_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 8.81 + d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 8.82 end 8.83 else 8.84 `endif 8.85 begin 8.86 // Refill/access complete 8.87 - d_cyc_o <= #1 `FALSE; 8.88 - d_stb_o <= #1 `FALSE; 8.89 - d_lock_o <= #1 `FALSE; 8.90 + d_cyc_o <= `FALSE; 8.91 + d_stb_o <= `FALSE; 8.92 + d_lock_o <= `FALSE; 8.93 end 8.94 `ifdef CFG_DCACHE_ENABLED 8.95 - d_cti_o <= #1 next_cycle_type; 8.96 + d_cti_o <= next_cycle_type; 8.97 // If we are performing a refill, indicate to cache next word of data is ready 8.98 - dcache_refill_ready <= #1 dcache_refilling; 8.99 + dcache_refill_ready <= dcache_refilling; 8.100 `endif 8.101 // Register data read from Wishbone interface 8.102 - wb_data_m <= #1 d_dat_i; 8.103 + wb_data_m <= d_dat_i; 8.104 // Don't set when stores complete - otherwise we'll deadlock if load in m stage 8.105 - wb_load_complete <= #1 !d_we_o; 8.106 + wb_load_complete <= !d_we_o; 8.107 end 8.108 // synthesis translate_off 8.109 if (d_err_i == `TRUE) 8.110 @@ -686,13 +686,13 @@ 8.111 if (dcache_refill_request == `TRUE) 8.112 begin 8.113 // Start cache refill 8.114 - d_adr_o <= #1 first_address; 8.115 - d_cyc_o <= #1 `TRUE; 8.116 - d_sel_o <= #1 {`LM32_WORD_WIDTH/8{`TRUE}}; 8.117 - d_stb_o <= #1 `TRUE; 8.118 - d_we_o <= #1 `FALSE; 8.119 - d_cti_o <= #1 first_cycle_type; 8.120 - //d_lock_o <= #1 `TRUE; 8.121 + d_adr_o <= first_address; 8.122 + d_cyc_o <= `TRUE; 8.123 + d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}}; 8.124 + d_stb_o <= `TRUE; 8.125 + d_we_o <= `FALSE; 8.126 + d_cti_o <= first_cycle_type; 8.127 + //d_lock_o <= `TRUE; 8.128 end 8.129 else 8.130 `endif 8.131 @@ -707,13 +707,13 @@ 8.132 ) 8.133 begin 8.134 // Data cache is write through, so all stores go to memory 8.135 - d_dat_o <= #1 store_data_m; 8.136 - d_adr_o <= #1 load_store_address_m; 8.137 - d_cyc_o <= #1 `TRUE; 8.138 - d_sel_o <= #1 byte_enable_m; 8.139 - d_stb_o <= #1 `TRUE; 8.140 - d_we_o <= #1 `TRUE; 8.141 - d_cti_o <= #1 `LM32_CTYPE_END; 8.142 + d_dat_o <= store_data_m; 8.143 + d_adr_o <= load_store_address_m; 8.144 + d_cyc_o <= `TRUE; 8.145 + d_sel_o <= byte_enable_m; 8.146 + d_stb_o <= `TRUE; 8.147 + d_we_o <= `TRUE; 8.148 + d_cti_o <= `LM32_CTYPE_END; 8.149 end 8.150 else if ( (load_q_m == `TRUE) 8.151 && (wb_select_m == `TRUE) 8.152 @@ -722,24 +722,24 @@ 8.153 ) 8.154 begin 8.155 // Read requested address 8.156 - stall_wb_load <= #1 `FALSE; 8.157 - d_adr_o <= #1 load_store_address_m; 8.158 - d_cyc_o <= #1 `TRUE; 8.159 - d_sel_o <= #1 byte_enable_m; 8.160 - d_stb_o <= #1 `TRUE; 8.161 - d_we_o <= #1 `FALSE; 8.162 - d_cti_o <= #1 `LM32_CTYPE_END; 8.163 + stall_wb_load <= `FALSE; 8.164 + d_adr_o <= load_store_address_m; 8.165 + d_cyc_o <= `TRUE; 8.166 + d_sel_o <= byte_enable_m; 8.167 + d_stb_o <= `TRUE; 8.168 + d_we_o <= `FALSE; 8.169 + d_cti_o <= `LM32_CTYPE_END; 8.170 end 8.171 end 8.172 // Clear load/store complete flag when instruction leaves M stage 8.173 if (stall_m == `FALSE) 8.174 - wb_load_complete <= #1 `FALSE; 8.175 + wb_load_complete <= `FALSE; 8.176 // When a Wishbone load first enters the M stage, we need to stall it 8.177 if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE)) 8.178 - stall_wb_load <= #1 `TRUE; 8.179 + stall_wb_load <= `TRUE; 8.180 // Clear stall request if load instruction is killed 8.181 if ((kill_m == `TRUE) || (exception_m == `TRUE)) 8.182 - stall_wb_load <= #1 `FALSE; 8.183 + stall_wb_load <= `FALSE; 8.184 end 8.185 end 8.186 8.187 @@ -750,39 +750,39 @@ 8.188 begin 8.189 if (rst_i == `TRUE) 8.190 begin 8.191 - sign_extend_m <= #1 `FALSE; 8.192 - size_m <= #1 2'b00; 8.193 - byte_enable_m <= #1 `FALSE; 8.194 - store_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}}; 8.195 + sign_extend_m <= `FALSE; 8.196 + size_m <= 2'b00; 8.197 + byte_enable_m <= `FALSE; 8.198 + store_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 8.199 `ifdef CFG_DCACHE_ENABLED 8.200 - dcache_select_m <= #1 `FALSE; 8.201 + dcache_select_m <= `FALSE; 8.202 `endif 8.203 `ifdef CFG_DRAM_ENABLED 8.204 - dram_select_m <= #1 `FALSE; 8.205 + dram_select_m <= `FALSE; 8.206 `endif 8.207 `ifdef CFG_IROM_ENABLED 8.208 - irom_select_m <= #1 `FALSE; 8.209 + irom_select_m <= `FALSE; 8.210 `endif 8.211 - wb_select_m <= #1 `FALSE; 8.212 + wb_select_m <= `FALSE; 8.213 end 8.214 else 8.215 begin 8.216 if (stall_m == `FALSE) 8.217 begin 8.218 - sign_extend_m <= #1 sign_extend_x; 8.219 - size_m <= #1 size_x; 8.220 - byte_enable_m <= #1 byte_enable_x; 8.221 - store_data_m <= #1 store_data_x; 8.222 + sign_extend_m <= sign_extend_x; 8.223 + size_m <= size_x; 8.224 + byte_enable_m <= byte_enable_x; 8.225 + store_data_m <= store_data_x; 8.226 `ifdef CFG_DCACHE_ENABLED 8.227 - dcache_select_m <= #1 dcache_select_x; 8.228 + dcache_select_m <= dcache_select_x; 8.229 `endif 8.230 `ifdef CFG_DRAM_ENABLED 8.231 - dram_select_m <= #1 dram_select_x; 8.232 + dram_select_m <= dram_select_x; 8.233 `endif 8.234 `ifdef CFG_IROM_ENABLED 8.235 - irom_select_m <= #1 irom_select_x; 8.236 + irom_select_m <= irom_select_x; 8.237 `endif 8.238 - wb_select_m <= #1 wb_select_x; 8.239 + wb_select_m <= wb_select_x; 8.240 end 8.241 end 8.242 end 8.243 @@ -792,15 +792,15 @@ 8.244 begin 8.245 if (rst_i == `TRUE) 8.246 begin 8.247 - size_w <= #1 2'b00; 8.248 - data_w <= #1 {`LM32_WORD_WIDTH{1'b0}}; 8.249 - sign_extend_w <= #1 `FALSE; 8.250 + size_w <= 2'b00; 8.251 + data_w <= {`LM32_WORD_WIDTH{1'b0}}; 8.252 + sign_extend_w <= `FALSE; 8.253 end 8.254 else 8.255 begin 8.256 - size_w <= #1 size_m; 8.257 - data_w <= #1 data_m; 8.258 - sign_extend_w <= #1 sign_extend_m; 8.259 + size_w <= size_m; 8.260 + data_w <= data_m; 8.261 + sign_extend_w <= sign_extend_m; 8.262 end 8.263 end 8.264
9.1 diff -r 73de224304c1 -r d6c693415d59 lm32_mc_arithmetic.v 9.2 --- a/lm32_mc_arithmetic.v Sat Aug 06 00:02:46 2011 +0100 9.3 +++ b/lm32_mc_arithmetic.v Sat Aug 06 01:26:56 2011 +0100 9.4 @@ -170,59 +170,59 @@ 9.5 begin 9.6 if (rst_i == `TRUE) 9.7 begin 9.8 - cycles <= #1 {6{1'b0}}; 9.9 - p <= #1 {`LM32_WORD_WIDTH{1'b0}}; 9.10 - a <= #1 {`LM32_WORD_WIDTH{1'b0}}; 9.11 - b <= #1 {`LM32_WORD_WIDTH{1'b0}}; 9.12 + cycles <= {6{1'b0}}; 9.13 + p <= {`LM32_WORD_WIDTH{1'b0}}; 9.14 + a <= {`LM32_WORD_WIDTH{1'b0}}; 9.15 + b <= {`LM32_WORD_WIDTH{1'b0}}; 9.16 `ifdef CFG_MC_BARREL_SHIFT_ENABLED 9.17 - sign_extend_x <= #1 1'b0; 9.18 + sign_extend_x <= 1'b0; 9.19 `endif 9.20 `ifdef CFG_MC_DIVIDE_ENABLED 9.21 - divide_by_zero_x <= #1 `FALSE; 9.22 + divide_by_zero_x <= `FALSE; 9.23 `endif 9.24 - result_x <= #1 {`LM32_WORD_WIDTH{1'b0}}; 9.25 - state <= #1 `LM32_MC_STATE_IDLE; 9.26 + result_x <= {`LM32_WORD_WIDTH{1'b0}}; 9.27 + state <= `LM32_MC_STATE_IDLE; 9.28 end 9.29 else 9.30 begin 9.31 `ifdef CFG_MC_DIVIDE_ENABLED 9.32 - divide_by_zero_x <= #1 `FALSE; 9.33 + divide_by_zero_x <= `FALSE; 9.34 `endif 9.35 case (state) 9.36 `LM32_MC_STATE_IDLE: 9.37 begin 9.38 if (stall_d == `FALSE) 9.39 begin 9.40 - cycles <= #1 `LM32_WORD_WIDTH; 9.41 - p <= #1 32'b0; 9.42 - a <= #1 operand_0_d; 9.43 - b <= #1 operand_1_d; 9.44 + cycles <= `LM32_WORD_WIDTH; 9.45 + p <= 32'b0; 9.46 + a <= operand_0_d; 9.47 + b <= operand_1_d; 9.48 `ifdef CFG_MC_DIVIDE_ENABLED 9.49 if (divide_d == `TRUE) 9.50 - state <= #1 `LM32_MC_STATE_DIVIDE; 9.51 + state <= `LM32_MC_STATE_DIVIDE; 9.52 if (modulus_d == `TRUE) 9.53 - state <= #1 `LM32_MC_STATE_MODULUS; 9.54 + state <= `LM32_MC_STATE_MODULUS; 9.55 `endif 9.56 `ifdef CFG_MC_MULTIPLY_ENABLED 9.57 if (multiply_d == `TRUE) 9.58 - state <= #1 `LM32_MC_STATE_MULTIPLY; 9.59 + state <= `LM32_MC_STATE_MULTIPLY; 9.60 `endif 9.61 `ifdef CFG_MC_BARREL_SHIFT_ENABLED 9.62 if (shift_left_d == `TRUE) 9.63 begin 9.64 - state <= #1 `LM32_MC_STATE_SHIFT_LEFT; 9.65 - sign_extend_x <= #1 sign_extend_d; 9.66 - cycles <= #1 operand_1_d[4:0]; 9.67 - a <= #1 operand_0_d; 9.68 - b <= #1 operand_0_d; 9.69 + state <= `LM32_MC_STATE_SHIFT_LEFT; 9.70 + sign_extend_x <= sign_extend_d; 9.71 + cycles <= operand_1_d[4:0]; 9.72 + a <= operand_0_d; 9.73 + b <= operand_0_d; 9.74 end 9.75 if (shift_right_d == `TRUE) 9.76 begin 9.77 - state <= #1 `LM32_MC_STATE_SHIFT_RIGHT; 9.78 - sign_extend_x <= #1 sign_extend_d; 9.79 - cycles <= #1 operand_1_d[4:0]; 9.80 - a <= #1 operand_0_d; 9.81 - b <= #1 operand_0_d; 9.82 + state <= `LM32_MC_STATE_SHIFT_RIGHT; 9.83 + sign_extend_x <= sign_extend_d; 9.84 + cycles <= operand_1_d[4:0]; 9.85 + a <= operand_0_d; 9.86 + b <= operand_0_d; 9.87 end 9.88 `endif 9.89 end 9.90 @@ -232,74 +232,74 @@ 9.91 begin 9.92 if (t[32] == 1'b0) 9.93 begin 9.94 - p <= #1 t[31:0]; 9.95 - a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 9.96 + p <= t[31:0]; 9.97 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 9.98 end 9.99 else 9.100 begin 9.101 - p <= #1 {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 9.102 - a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.103 + p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 9.104 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.105 end 9.106 - result_x <= #1 a; 9.107 + result_x <= a; 9.108 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 9.109 begin 9.110 // Check for divide by zero 9.111 - divide_by_zero_x <= #1 b == {`LM32_WORD_WIDTH{1'b0}}; 9.112 - state <= #1 `LM32_MC_STATE_IDLE; 9.113 + divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}}; 9.114 + state <= `LM32_MC_STATE_IDLE; 9.115 end 9.116 - cycles <= #1 cycles - 1'b1; 9.117 + cycles <= cycles - 1'b1; 9.118 end 9.119 `LM32_MC_STATE_MODULUS: 9.120 begin 9.121 if (t[32] == 1'b0) 9.122 begin 9.123 - p <= #1 t[31:0]; 9.124 - a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 9.125 + p <= t[31:0]; 9.126 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 9.127 end 9.128 else 9.129 begin 9.130 - p <= #1 {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 9.131 - a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.132 + p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 9.133 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.134 end 9.135 - result_x <= #1 p; 9.136 + result_x <= p; 9.137 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 9.138 begin 9.139 // Check for divide by zero 9.140 - divide_by_zero_x <= #1 b == {`LM32_WORD_WIDTH{1'b0}}; 9.141 - state <= #1 `LM32_MC_STATE_IDLE; 9.142 + divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}}; 9.143 + state <= `LM32_MC_STATE_IDLE; 9.144 end 9.145 - cycles <= #1 cycles - 1'b1; 9.146 + cycles <= cycles - 1'b1; 9.147 end 9.148 `endif 9.149 `ifdef CFG_MC_MULTIPLY_ENABLED 9.150 `LM32_MC_STATE_MULTIPLY: 9.151 begin 9.152 if (b[0] == 1'b1) 9.153 - p <= #1 p + a; 9.154 - b <= #1 {1'b0, b[`LM32_WORD_WIDTH-1:1]}; 9.155 - a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.156 - result_x <= #1 p; 9.157 + p <= p + a; 9.158 + b <= {1'b0, b[`LM32_WORD_WIDTH-1:1]}; 9.159 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.160 + result_x <= p; 9.161 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 9.162 - state <= #1 `LM32_MC_STATE_IDLE; 9.163 - cycles <= #1 cycles - 1'b1; 9.164 + state <= `LM32_MC_STATE_IDLE; 9.165 + cycles <= cycles - 1'b1; 9.166 end 9.167 `endif 9.168 `ifdef CFG_MC_BARREL_SHIFT_ENABLED 9.169 `LM32_MC_STATE_SHIFT_LEFT: 9.170 begin 9.171 - a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.172 - result_x <= #1 a; 9.173 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 9.174 + result_x <= a; 9.175 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 9.176 - state <= #1 `LM32_MC_STATE_IDLE; 9.177 - cycles <= #1 cycles - 1'b1; 9.178 + state <= `LM32_MC_STATE_IDLE; 9.179 + cycles <= cycles - 1'b1; 9.180 end 9.181 `LM32_MC_STATE_SHIFT_RIGHT: 9.182 begin 9.183 - b <= #1 {fill_value, b[`LM32_WORD_WIDTH-1:1]}; 9.184 - result_x <= #1 b; 9.185 + b <= {fill_value, b[`LM32_WORD_WIDTH-1:1]}; 9.186 + result_x <= b; 9.187 if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 9.188 - state <= #1 `LM32_MC_STATE_IDLE; 9.189 - cycles <= #1 cycles - 1'b1; 9.190 + state <= `LM32_MC_STATE_IDLE; 9.191 + cycles <= cycles - 1'b1; 9.192 end 9.193 `endif 9.194 endcase
10.1 diff -r 73de224304c1 -r d6c693415d59 lm32_monitor.v 10.2 --- a/lm32_monitor.v Sat Aug 06 00:02:46 2011 +0100 10.3 +++ b/lm32_monitor.v Sat Aug 06 01:26:56 2011 +0100 10.4 @@ -144,10 +144,10 @@ 10.5 begin 10.6 if (rst_i == `TRUE) 10.7 begin 10.8 - write_enable <= #1 `FALSE; 10.9 - MON_ACK_O <= #1 `FALSE; 10.10 - MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}}; 10.11 - state <= #1 2'b00; 10.12 + write_enable <= `FALSE; 10.13 + MON_ACK_O <= `FALSE; 10.14 + MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 10.15 + state <= 2'b00; 10.16 end 10.17 else 10.18 begin 10.19 @@ -155,33 +155,33 @@ 10.20 2'b01: 10.21 begin 10.22 // Output read data to Wishbone 10.23 - MON_ACK_O <= #1 `TRUE; 10.24 - MON_DAT_O <= #1 data; 10.25 + MON_ACK_O <= `TRUE; 10.26 + MON_DAT_O <= data; 10.27 // Sub-word writes are performed using read-modify-write 10.28 // as the Lattice EBRs don't support byte enables 10.29 if (MON_WE_I == `TRUE) 10.30 - write_enable <= #1 `TRUE; 10.31 - write_data[7:0] <= #1 MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0]; 10.32 - write_data[15:8] <= #1 MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8]; 10.33 - write_data[23:16] <= #1 MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16]; 10.34 - write_data[31:24] <= #1 MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24]; 10.35 - state <= #1 2'b10; 10.36 + write_enable <= `TRUE; 10.37 + write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0]; 10.38 + write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8]; 10.39 + write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16]; 10.40 + write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24]; 10.41 + state <= 2'b10; 10.42 end 10.43 2'b10: 10.44 begin 10.45 // Wishbone access occurs in this cycle 10.46 - write_enable <= #1 `FALSE; 10.47 - MON_ACK_O <= #1 `FALSE; 10.48 - MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}}; 10.49 - state <= #1 2'b00; 10.50 + write_enable <= `FALSE; 10.51 + MON_ACK_O <= `FALSE; 10.52 + MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 10.53 + state <= 2'b00; 10.54 end 10.55 default: 10.56 begin 10.57 - write_enable <= #1 `FALSE; 10.58 - MON_ACK_O <= #1 `FALSE; 10.59 + write_enable <= `FALSE; 10.60 + MON_ACK_O <= `FALSE; 10.61 // Wait for a Wishbone access 10.62 if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE)) 10.63 - state <= #1 2'b01; 10.64 + state <= 2'b01; 10.65 end 10.66 endcase 10.67 end
11.1 diff -r 73de224304c1 -r d6c693415d59 lm32_multiplier.v 11.2 --- a/lm32_multiplier.v Sat Aug 06 00:02:46 2011 +0100 11.3 +++ b/lm32_multiplier.v Sat Aug 06 01:26:56 2011 +0100 11.4 @@ -99,21 +99,21 @@ 11.5 begin 11.6 if (rst_i == `TRUE) 11.7 begin 11.8 - muliplicand <= #1 {`LM32_WORD_WIDTH{1'b0}}; 11.9 - multiplier <= #1 {`LM32_WORD_WIDTH{1'b0}}; 11.10 - product <= #1 {`LM32_WORD_WIDTH{1'b0}}; 11.11 - result <= #1 {`LM32_WORD_WIDTH{1'b0}}; 11.12 + muliplicand <= {`LM32_WORD_WIDTH{1'b0}}; 11.13 + multiplier <= {`LM32_WORD_WIDTH{1'b0}}; 11.14 + product <= {`LM32_WORD_WIDTH{1'b0}}; 11.15 + result <= {`LM32_WORD_WIDTH{1'b0}}; 11.16 end 11.17 else 11.18 begin 11.19 if (stall_x == `FALSE) 11.20 begin 11.21 - muliplicand <= #1 operand_0; 11.22 - multiplier <= #1 operand_1; 11.23 + muliplicand <= operand_0; 11.24 + multiplier <= operand_1; 11.25 end 11.26 if (stall_m == `FALSE) 11.27 - product <= #1 muliplicand * multiplier; 11.28 - result <= #1 product; 11.29 + product <= muliplicand * multiplier; 11.30 + result <= product; 11.31 end 11.32 end 11.33
12.1 diff -r 73de224304c1 -r d6c693415d59 lm32_ram.v 12.2 --- a/lm32_ram.v Sat Aug 06 00:02:46 2011 +0100 12.3 +++ b/lm32_ram.v Sat Aug 06 01:26:56 2011 +0100 12.4 @@ -191,13 +191,13 @@ 12.5 always @(posedge read_clk) 12.6 if (reset) 12.7 begin 12.8 - raw_data <= #1 0; 12.9 - raw <= #1 1'b0; 12.10 + raw_data <= 0; 12.11 + raw <= 1'b0; 12.12 end 12.13 else 12.14 begin 12.15 - raw_data <= #1 raw_data_nxt; 12.16 - raw <= #1 raw_nxt; 12.17 + raw_data <= raw_data_nxt; 12.18 + raw <= raw_nxt; 12.19 end 12.20 12.21 pmi_ram_dp_true 12.22 @@ -273,7 +273,7 @@ 12.23 12.24 always @(posedge read_clk) 12.25 if (enable_read) 12.26 - ra <= #1 read_address; 12.27 + ra <= read_address; 12.28 end 12.29 12.30 else 12.31 @@ -296,12 +296,12 @@ 12.32 // Write port 12.33 always @(posedge write_clk) 12.34 if ((write_enable == `TRUE) && (enable_write == `TRUE)) 12.35 - mem[write_address] <= #1 write_data; 12.36 + mem[write_address] <= write_data; 12.37 12.38 // Register read address for use on next cycle 12.39 always @(posedge read_clk) 12.40 if (enable_read) 12.41 - ra <= #1 read_address; 12.42 + ra <= read_address; 12.43 12.44 end 12.45
13.1 diff -r 73de224304c1 -r d6c693415d59 lm32_shifter.v 13.2 --- a/lm32_shifter.v Sat Aug 06 00:02:46 2011 +0100 13.3 +++ b/lm32_shifter.v Sat Aug 06 01:26:56 2011 +0100 13.4 @@ -139,15 +139,15 @@ 13.5 begin 13.6 if (rst_i == `TRUE) 13.7 begin 13.8 - right_shift_result <= #1 {`LM32_WORD_WIDTH{1'b0}}; 13.9 - direction_m <= #1 `FALSE; 13.10 + right_shift_result <= {`LM32_WORD_WIDTH{1'b0}}; 13.11 + direction_m <= `FALSE; 13.12 end 13.13 else 13.14 begin 13.15 if (stall_x == `FALSE) 13.16 begin 13.17 - right_shift_result <= #1 {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG]; 13.18 - direction_m <= #1 direction_x; 13.19 + right_shift_result <= {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG]; 13.20 + direction_m <= direction_x; 13.21 end 13.22 end 13.23 end
14.1 diff -r 73de224304c1 -r d6c693415d59 lm32_trace.v 14.2 --- a/lm32_trace.v Sat Aug 06 00:02:46 2011 +0100 14.3 +++ b/lm32_trace.v Sat Aug 06 01:26:56 2011 +0100 14.4 @@ -146,65 +146,65 @@ 14.5 assign dat_o = (rw_creg ? reg_dat_o : trace_dat_o); 14.6 14.7 initial begin 14.8 - trig_type <= #1 0; 14.9 - stop_type <= #1 0; 14.10 - trace_len <= #1 0; 14.11 - pc_low <= #1 0; 14.12 - pc_high <= #1 0; 14.13 - trace_start <= #1 0; 14.14 - trace_stop <= #1 0; 14.15 - ack_o <= #1 0; 14.16 - reg_dat_o <= #1 0; 14.17 - mem_valid <= #1 0; 14.18 - started <= #1 0; 14.19 - capturing <= #1 0; 14.20 + trig_type <= 0; 14.21 + stop_type <= 0; 14.22 + trace_len <= 0; 14.23 + pc_low <= 0; 14.24 + pc_high <= 0; 14.25 + trace_start <= 0; 14.26 + trace_stop <= 0; 14.27 + ack_o <= 0; 14.28 + reg_dat_o <= 0; 14.29 + mem_valid <= 0; 14.30 + started <= 0; 14.31 + capturing <= 0; 14.32 end 14.33 14.34 // the host side control 14.35 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.36 begin 14.37 if (rst_i == `TRUE) begin 14.38 - trig_type <= #1 0; 14.39 - trace_stop <= #1 0; 14.40 - trace_start <= #1 0; 14.41 - pc_low <= #1 0; 14.42 - pc_high <= #1 0; 14.43 - ack_o <= #1 0; 14.44 + trig_type <= 0; 14.45 + trace_stop <= 0; 14.46 + trace_start <= 0; 14.47 + pc_low <= 0; 14.48 + pc_high <= 0; 14.49 + ack_o <= 0; 14.50 end else begin 14.51 if (stb_i == `TRUE && ack_o == `FALSE) begin 14.52 if (rw_creg) begin // control register access 14.53 - ack_o <= #1 `TRUE; 14.54 + ack_o <= `TRUE; 14.55 if (we_i == `TRUE) begin 14.56 case ({adr_i[11:2],2'b0}) 14.57 // write to trig type 14.58 12'd0: 14.59 begin 14.60 if (sel_i[0]) begin 14.61 - trig_type[4:0] <= #1 dat_i[4:0]; 14.62 + trig_type[4:0] <= dat_i[4:0]; 14.63 end 14.64 if (sel_i[3]) begin 14.65 - trace_start <= #1 dat_i[31]; 14.66 - trace_stop <= #1 dat_i[30]; 14.67 + trace_start <= dat_i[31]; 14.68 + trace_stop <= dat_i[30]; 14.69 end 14.70 end 14.71 12'd8: 14.72 begin 14.73 - if (sel_i[3]) pc_low[31:24] <= #1 dat_i[31:24]; 14.74 - if (sel_i[2]) pc_low[23:16] <= #1 dat_i[23:16]; 14.75 - if (sel_i[1]) pc_low[15:8] <= #1 dat_i[15:8]; 14.76 - if (sel_i[0]) pc_low[7:0] <= #1 dat_i[7:0]; 14.77 + if (sel_i[3]) pc_low[31:24] <= dat_i[31:24]; 14.78 + if (sel_i[2]) pc_low[23:16] <= dat_i[23:16]; 14.79 + if (sel_i[1]) pc_low[15:8] <= dat_i[15:8]; 14.80 + if (sel_i[0]) pc_low[7:0] <= dat_i[7:0]; 14.81 end 14.82 12'd12: 14.83 begin 14.84 - if (sel_i[3]) pc_high[31:24] <= #1 dat_i[31:24]; 14.85 - if (sel_i[2]) pc_high[23:16] <= #1 dat_i[23:16]; 14.86 - if (sel_i[1]) pc_high[15:8] <= #1 dat_i[15:8]; 14.87 - if (sel_i[0]) pc_high[7:0] <= #1 dat_i[7:0]; 14.88 + if (sel_i[3]) pc_high[31:24] <= dat_i[31:24]; 14.89 + if (sel_i[2]) pc_high[23:16] <= dat_i[23:16]; 14.90 + if (sel_i[1]) pc_high[15:8] <= dat_i[15:8]; 14.91 + if (sel_i[0]) pc_high[7:0] <= dat_i[7:0]; 14.92 end 14.93 12'd16: 14.94 begin 14.95 if (sel_i[0])begin 14.96 - stop_type[4:0] <= #1 dat_i[4:0]; 14.97 + stop_type[4:0] <= dat_i[4:0]; 14.98 end 14.99 end 14.100 endcase 14.101 @@ -212,27 +212,27 @@ 14.102 case ({adr_i[11:2],2'b0}) 14.103 // read the trig type 14.104 12'd0: 14.105 - reg_dat_o <= #1 {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 14.106 + reg_dat_o <= {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 14.107 12'd4: 14.108 - reg_dat_o <= #1 trace_len; 14.109 + reg_dat_o <= trace_len; 14.110 12'd8: 14.111 - reg_dat_o <= #1 pc_low; 14.112 + reg_dat_o <= pc_low; 14.113 12'd12: 14.114 - reg_dat_o <= #1 pc_high; 14.115 + reg_dat_o <= pc_high; 14.116 default: 14.117 - reg_dat_o <= #1 {27'b0,stop_type}; 14.118 + reg_dat_o <= {27'b0,stop_type}; 14.119 endcase 14.120 end // else: !if(we_i == `TRUE) 14.121 end else // read / write memory 14.122 if (we_i == `FALSE) begin 14.123 - ack_o <= #1 `TRUE; 14.124 + ack_o <= `TRUE; 14.125 end else 14.126 - ack_o <= #1 `FALSE; 14.127 + ack_o <= `FALSE; 14.128 // not allowed to write to trace memory 14.129 end else begin // if (stb_i == `TRUE) 14.130 - trace_start <= #1 `FALSE; 14.131 - trace_stop <= #1 `FALSE; 14.132 - ack_o <= #1 `FALSE; 14.133 + trace_start <= `FALSE; 14.134 + trace_stop <= `FALSE; 14.135 + ack_o <= `FALSE; 14.136 end // else: !if(stb_i == `TRUE) 14.137 end // else: !if(rst_i == `TRUE) 14.138 end 14.139 @@ -268,31 +268,31 @@ 14.140 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.141 begin 14.142 if (rst_i == `TRUE) begin 14.143 - tstate <= #1 0; 14.144 - trace_we <= #1 0; 14.145 - trace_len <= #1 0; 14.146 - ovrflw <= #1 `FALSE; 14.147 - mem_valid <= #1 0; 14.148 - started <= #1 0; 14.149 - capturing <= #1 0; 14.150 + tstate <= 0; 14.151 + trace_we <= 0; 14.152 + trace_len <= 0; 14.153 + ovrflw <= `FALSE; 14.154 + mem_valid <= 0; 14.155 + started <= 0; 14.156 + capturing <= 0; 14.157 end else begin 14.158 case (tstate) 14.159 3'd0: 14.160 // start capture 14.161 if (trace_start) begin 14.162 - tstate <= #1 3'd1; 14.163 - mem_valid <= #1 0; 14.164 - started <= #1 1; 14.165 + tstate <= 3'd1; 14.166 + mem_valid <= 0; 14.167 + started <= 1; 14.168 end 14.169 3'd1: 14.170 begin 14.171 // wait for trigger 14.172 if (trace_begin) begin 14.173 - capturing <= #1 1; 14.174 - tstate <= #1 3'd2; 14.175 - trace_we <= #1 `TRUE; 14.176 - trace_len <= #1 0; 14.177 - ovrflw <= #1 `FALSE; 14.178 + capturing <= 1; 14.179 + tstate <= 3'd2; 14.180 + trace_we <= `TRUE; 14.181 + trace_len <= 0; 14.182 + ovrflw <= `FALSE; 14.183 end 14.184 end // case: 3'd1 14.185 14.186 @@ -300,18 +300,18 @@ 14.187 begin 14.188 if (trace_pc_valid) begin 14.189 if (trace_len[mem_addr_width]) 14.190 - trace_len <= #1 0; 14.191 + trace_len <= 0; 14.192 else 14.193 - trace_len <= #1 trace_len + 1; 14.194 + trace_len <= trace_len + 1; 14.195 end 14.196 - if (!ovrflw) ovrflw <= #1 trace_len[mem_addr_width]; 14.197 + if (!ovrflw) ovrflw <= trace_len[mem_addr_width]; 14.198 // wait for stop condition 14.199 if (trace_end) begin 14.200 - tstate <= #1 3'd0; 14.201 - trace_we <= #1 0; 14.202 - mem_valid <= #1 1; 14.203 - started <= #1 0; 14.204 - capturing <= #1 0; 14.205 + tstate <= 3'd0; 14.206 + trace_we <= 0; 14.207 + mem_valid <= 1; 14.208 + started <= 0; 14.209 + capturing <= 0; 14.210 end 14.211 end // case: 3'd2 14.212 endcase
15.1 diff -r 73de224304c1 -r d6c693415d59 typea.v 15.2 --- a/typea.v Sat Aug 06 00:02:46 2011 +0100 15.3 +++ b/typea.v Sat Aug 06 01:26:56 2011 +0100 15.4 @@ -80,13 +80,13 @@ 15.5 always @ (negedge CLK or negedge RESET_N) 15.6 begin 15.7 if (RESET_N == 1'b0) 15.8 - tdoInt <= #1 1'b0; 15.9 + tdoInt <= 1'b0; 15.10 else if (CLK == 1'b0) 15.11 if (CLKEN == 1'b1) 15.12 if (CAPTURE_DR == 1'b0) 15.13 - tdoInt <= #1 TDI; 15.14 + tdoInt <= TDI; 15.15 else 15.16 - tdoInt <= #1 DATA_IN; 15.17 + tdoInt <= DATA_IN; 15.18 end 15.19 15.20 assign TDO = tdoInt; 15.21 @@ -94,9 +94,9 @@ 15.22 always @ (negedge CLK or negedge RESET_N) 15.23 begin 15.24 if (RESET_N == 1'b0) 15.25 - DATA_OUT <= #1 1'b0; 15.26 + DATA_OUT <= 1'b0; 15.27 else if (CLK == 1'b0) 15.28 if (UPDATE_DR == 1'b1) 15.29 - DATA_OUT <= #1 tdoInt; 15.30 + DATA_OUT <= tdoInt; 15.31 end 15.32 endmodule
16.1 diff -r 73de224304c1 -r d6c693415d59 typeb.v 16.2 --- a/typeb.v Sat Aug 06 00:02:46 2011 +0100 16.3 +++ b/typeb.v Sat Aug 06 01:26:56 2011 +0100 16.4 @@ -64,13 +64,13 @@ 16.5 always @ (negedge CLK or negedge RESET_N) 16.6 begin 16.7 if (RESET_N== 1'b0) 16.8 - tdoInt <= #1 1'b0; 16.9 + tdoInt <= 1'b0; 16.10 else if (CLK == 1'b0) 16.11 if (CLKEN==1'b1) 16.12 if (CAPTURE_DR==1'b0) 16.13 - tdoInt <= #1 TDI; 16.14 + tdoInt <= TDI; 16.15 else 16.16 - tdoInt <= #1 DATA_IN; 16.17 + tdoInt <= DATA_IN; 16.18 end 16.19 16.20 assign TDO = tdoInt;